557 lines
14 KiB
C
557 lines
14 KiB
C
/*
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* AXI clkgen driver
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*
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* Copyright 2012-2013 Analog Devices Inc.
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* Author: Lars-Peter Clausen <lars@metafoo.de>
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*
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* Licensed under the GPL-2.
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*
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*/
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#include <linux/platform_device.h>
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#include <linux/clk-provider.h>
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#include <linux/clk.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/module.h>
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#include <linux/err.h>
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#define AXI_CLKGEN_V1_REG_UPDATE_ENABLE 0x04
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#define AXI_CLKGEN_V1_REG_CLK_OUT1 0x08
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#define AXI_CLKGEN_V1_REG_CLK_OUT2 0x0c
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#define AXI_CLKGEN_V1_REG_CLK_DIV 0x10
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#define AXI_CLKGEN_V1_REG_CLK_FB1 0x14
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#define AXI_CLKGEN_V1_REG_CLK_FB2 0x18
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#define AXI_CLKGEN_V1_REG_LOCK1 0x1c
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#define AXI_CLKGEN_V1_REG_LOCK2 0x20
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#define AXI_CLKGEN_V1_REG_LOCK3 0x24
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#define AXI_CLKGEN_V1_REG_FILTER1 0x28
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#define AXI_CLKGEN_V1_REG_FILTER2 0x2c
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#define AXI_CLKGEN_V2_REG_RESET 0x40
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#define AXI_CLKGEN_V2_REG_DRP_CNTRL 0x70
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#define AXI_CLKGEN_V2_REG_DRP_STATUS 0x74
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#define AXI_CLKGEN_V2_RESET_MMCM_ENABLE BIT(1)
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#define AXI_CLKGEN_V2_RESET_ENABLE BIT(0)
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#define AXI_CLKGEN_V2_DRP_CNTRL_SEL BIT(29)
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#define AXI_CLKGEN_V2_DRP_CNTRL_READ BIT(28)
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#define AXI_CLKGEN_V2_DRP_STATUS_BUSY BIT(16)
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#define MMCM_REG_CLKOUT0_1 0x08
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#define MMCM_REG_CLKOUT0_2 0x09
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#define MMCM_REG_CLK_FB1 0x14
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#define MMCM_REG_CLK_FB2 0x15
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#define MMCM_REG_CLK_DIV 0x16
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#define MMCM_REG_LOCK1 0x18
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#define MMCM_REG_LOCK2 0x19
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#define MMCM_REG_LOCK3 0x1a
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#define MMCM_REG_FILTER1 0x4e
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#define MMCM_REG_FILTER2 0x4f
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struct axi_clkgen;
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struct axi_clkgen_mmcm_ops {
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void (*enable)(struct axi_clkgen *axi_clkgen, bool enable);
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int (*write)(struct axi_clkgen *axi_clkgen, unsigned int reg,
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unsigned int val, unsigned int mask);
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int (*read)(struct axi_clkgen *axi_clkgen, unsigned int reg,
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unsigned int *val);
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};
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struct axi_clkgen {
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void __iomem *base;
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const struct axi_clkgen_mmcm_ops *mmcm_ops;
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struct clk_hw clk_hw;
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};
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static void axi_clkgen_mmcm_enable(struct axi_clkgen *axi_clkgen,
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bool enable)
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{
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axi_clkgen->mmcm_ops->enable(axi_clkgen, enable);
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}
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static int axi_clkgen_mmcm_write(struct axi_clkgen *axi_clkgen,
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unsigned int reg, unsigned int val, unsigned int mask)
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{
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return axi_clkgen->mmcm_ops->write(axi_clkgen, reg, val, mask);
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}
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static int axi_clkgen_mmcm_read(struct axi_clkgen *axi_clkgen,
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unsigned int reg, unsigned int *val)
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{
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return axi_clkgen->mmcm_ops->read(axi_clkgen, reg, val);
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}
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static uint32_t axi_clkgen_lookup_filter(unsigned int m)
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{
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switch (m) {
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case 0:
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return 0x01001990;
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case 1:
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return 0x01001190;
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case 2:
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return 0x01009890;
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case 3:
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return 0x01001890;
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case 4:
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return 0x01008890;
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case 5 ... 8:
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return 0x01009090;
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case 9 ... 11:
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return 0x01000890;
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case 12:
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return 0x08009090;
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case 13 ... 22:
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return 0x01001090;
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case 23 ... 36:
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return 0x01008090;
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case 37 ... 46:
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return 0x08001090;
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default:
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return 0x08008090;
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}
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}
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static const uint32_t axi_clkgen_lock_table[] = {
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0x060603e8, 0x060603e8, 0x080803e8, 0x0b0b03e8,
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0x0e0e03e8, 0x111103e8, 0x131303e8, 0x161603e8,
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0x191903e8, 0x1c1c03e8, 0x1f1f0384, 0x1f1f0339,
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0x1f1f02ee, 0x1f1f02bc, 0x1f1f028a, 0x1f1f0271,
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0x1f1f023f, 0x1f1f0226, 0x1f1f020d, 0x1f1f01f4,
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0x1f1f01db, 0x1f1f01c2, 0x1f1f01a9, 0x1f1f0190,
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0x1f1f0190, 0x1f1f0177, 0x1f1f015e, 0x1f1f015e,
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0x1f1f0145, 0x1f1f0145, 0x1f1f012c, 0x1f1f012c,
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0x1f1f012c, 0x1f1f0113, 0x1f1f0113, 0x1f1f0113,
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};
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static uint32_t axi_clkgen_lookup_lock(unsigned int m)
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{
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if (m < ARRAY_SIZE(axi_clkgen_lock_table))
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return axi_clkgen_lock_table[m];
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return 0x1f1f00fa;
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}
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static const unsigned int fpfd_min = 10000;
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static const unsigned int fpfd_max = 300000;
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static const unsigned int fvco_min = 600000;
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static const unsigned int fvco_max = 1200000;
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static void axi_clkgen_calc_params(unsigned long fin, unsigned long fout,
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unsigned int *best_d, unsigned int *best_m, unsigned int *best_dout)
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{
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unsigned long d, d_min, d_max, _d_min, _d_max;
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unsigned long m, m_min, m_max;
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unsigned long f, dout, best_f, fvco;
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fin /= 1000;
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fout /= 1000;
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best_f = ULONG_MAX;
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*best_d = 0;
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*best_m = 0;
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*best_dout = 0;
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d_min = max_t(unsigned long, DIV_ROUND_UP(fin, fpfd_max), 1);
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d_max = min_t(unsigned long, fin / fpfd_min, 80);
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m_min = max_t(unsigned long, DIV_ROUND_UP(fvco_min, fin) * d_min, 1);
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m_max = min_t(unsigned long, fvco_max * d_max / fin, 64);
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for (m = m_min; m <= m_max; m++) {
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_d_min = max(d_min, DIV_ROUND_UP(fin * m, fvco_max));
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_d_max = min(d_max, fin * m / fvco_min);
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for (d = _d_min; d <= _d_max; d++) {
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fvco = fin * m / d;
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dout = DIV_ROUND_CLOSEST(fvco, fout);
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dout = clamp_t(unsigned long, dout, 1, 128);
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f = fvco / dout;
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if (abs(f - fout) < abs(best_f - fout)) {
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best_f = f;
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*best_d = d;
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*best_m = m;
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*best_dout = dout;
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if (best_f == fout)
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return;
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}
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}
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}
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}
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static void axi_clkgen_calc_clk_params(unsigned int divider, unsigned int *low,
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unsigned int *high, unsigned int *edge, unsigned int *nocount)
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{
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if (divider == 1)
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*nocount = 1;
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else
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*nocount = 0;
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*high = divider / 2;
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*edge = divider % 2;
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*low = divider - *high;
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}
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static void axi_clkgen_write(struct axi_clkgen *axi_clkgen,
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unsigned int reg, unsigned int val)
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{
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writel(val, axi_clkgen->base + reg);
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}
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static void axi_clkgen_read(struct axi_clkgen *axi_clkgen,
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unsigned int reg, unsigned int *val)
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{
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*val = readl(axi_clkgen->base + reg);
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}
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static unsigned int axi_clkgen_v1_map_mmcm_reg(unsigned int reg)
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{
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switch (reg) {
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case MMCM_REG_CLKOUT0_1:
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return AXI_CLKGEN_V1_REG_CLK_OUT1;
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case MMCM_REG_CLKOUT0_2:
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return AXI_CLKGEN_V1_REG_CLK_OUT2;
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case MMCM_REG_CLK_FB1:
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return AXI_CLKGEN_V1_REG_CLK_FB1;
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case MMCM_REG_CLK_FB2:
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return AXI_CLKGEN_V1_REG_CLK_FB2;
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case MMCM_REG_CLK_DIV:
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return AXI_CLKGEN_V1_REG_CLK_DIV;
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case MMCM_REG_LOCK1:
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return AXI_CLKGEN_V1_REG_LOCK1;
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case MMCM_REG_LOCK2:
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return AXI_CLKGEN_V1_REG_LOCK2;
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case MMCM_REG_LOCK3:
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return AXI_CLKGEN_V1_REG_LOCK3;
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case MMCM_REG_FILTER1:
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return AXI_CLKGEN_V1_REG_FILTER1;
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case MMCM_REG_FILTER2:
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return AXI_CLKGEN_V1_REG_FILTER2;
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default:
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return 0;
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}
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}
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static int axi_clkgen_v1_mmcm_write(struct axi_clkgen *axi_clkgen,
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unsigned int reg, unsigned int val, unsigned int mask)
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{
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reg = axi_clkgen_v1_map_mmcm_reg(reg);
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if (reg == 0)
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return -EINVAL;
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axi_clkgen_write(axi_clkgen, reg, val);
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return 0;
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}
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static int axi_clkgen_v1_mmcm_read(struct axi_clkgen *axi_clkgen,
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unsigned int reg, unsigned int *val)
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{
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reg = axi_clkgen_v1_map_mmcm_reg(reg);
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if (reg == 0)
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return -EINVAL;
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axi_clkgen_read(axi_clkgen, reg, val);
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return 0;
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}
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static void axi_clkgen_v1_mmcm_enable(struct axi_clkgen *axi_clkgen,
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bool enable)
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{
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axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V1_REG_UPDATE_ENABLE, enable);
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}
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static const struct axi_clkgen_mmcm_ops axi_clkgen_v1_mmcm_ops = {
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.write = axi_clkgen_v1_mmcm_write,
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.read = axi_clkgen_v1_mmcm_read,
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.enable = axi_clkgen_v1_mmcm_enable,
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};
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static int axi_clkgen_wait_non_busy(struct axi_clkgen *axi_clkgen)
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{
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unsigned int timeout = 10000;
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unsigned int val;
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do {
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axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_STATUS, &val);
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} while ((val & AXI_CLKGEN_V2_DRP_STATUS_BUSY) && --timeout);
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if (val & AXI_CLKGEN_V2_DRP_STATUS_BUSY)
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return -EIO;
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return val & 0xffff;
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}
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static int axi_clkgen_v2_mmcm_read(struct axi_clkgen *axi_clkgen,
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unsigned int reg, unsigned int *val)
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{
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unsigned int reg_val;
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int ret;
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ret = axi_clkgen_wait_non_busy(axi_clkgen);
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if (ret < 0)
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return ret;
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reg_val = AXI_CLKGEN_V2_DRP_CNTRL_SEL | AXI_CLKGEN_V2_DRP_CNTRL_READ;
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reg_val |= (reg << 16);
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axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val);
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ret = axi_clkgen_wait_non_busy(axi_clkgen);
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if (ret < 0)
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return ret;
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*val = ret;
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return 0;
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}
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static int axi_clkgen_v2_mmcm_write(struct axi_clkgen *axi_clkgen,
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unsigned int reg, unsigned int val, unsigned int mask)
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{
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unsigned int reg_val = 0;
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int ret;
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ret = axi_clkgen_wait_non_busy(axi_clkgen);
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if (ret < 0)
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return ret;
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if (mask != 0xffff) {
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axi_clkgen_v2_mmcm_read(axi_clkgen, reg, ®_val);
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reg_val &= ~mask;
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}
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reg_val |= AXI_CLKGEN_V2_DRP_CNTRL_SEL | (reg << 16) | (val & mask);
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axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val);
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return 0;
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}
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static void axi_clkgen_v2_mmcm_enable(struct axi_clkgen *axi_clkgen,
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bool enable)
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{
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unsigned int val = AXI_CLKGEN_V2_RESET_ENABLE;
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if (enable)
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val |= AXI_CLKGEN_V2_RESET_MMCM_ENABLE;
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axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_RESET, val);
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}
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static const struct axi_clkgen_mmcm_ops axi_clkgen_v2_mmcm_ops = {
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.write = axi_clkgen_v2_mmcm_write,
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.read = axi_clkgen_v2_mmcm_read,
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.enable = axi_clkgen_v2_mmcm_enable,
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};
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static struct axi_clkgen *clk_hw_to_axi_clkgen(struct clk_hw *clk_hw)
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{
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return container_of(clk_hw, struct axi_clkgen, clk_hw);
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}
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static int axi_clkgen_set_rate(struct clk_hw *clk_hw,
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unsigned long rate, unsigned long parent_rate)
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{
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struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
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unsigned int d, m, dout;
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unsigned int nocount;
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unsigned int high;
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unsigned int edge;
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unsigned int low;
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uint32_t filter;
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uint32_t lock;
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if (parent_rate == 0 || rate == 0)
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return -EINVAL;
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axi_clkgen_calc_params(parent_rate, rate, &d, &m, &dout);
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if (d == 0 || dout == 0 || m == 0)
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return -EINVAL;
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filter = axi_clkgen_lookup_filter(m - 1);
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lock = axi_clkgen_lookup_lock(m - 1);
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axi_clkgen_calc_clk_params(dout, &low, &high, &edge, &nocount);
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axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLKOUT0_1,
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(high << 6) | low, 0xefff);
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axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLKOUT0_2,
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(edge << 7) | (nocount << 6), 0x03ff);
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axi_clkgen_calc_clk_params(d, &low, &high, &edge, &nocount);
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axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_DIV,
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(edge << 13) | (nocount << 12) | (high << 6) | low, 0x3fff);
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axi_clkgen_calc_clk_params(m, &low, &high, &edge, &nocount);
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axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_FB1,
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(high << 6) | low, 0xefff);
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axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_FB2,
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(edge << 7) | (nocount << 6), 0x03ff);
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axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK1, lock & 0x3ff, 0x3ff);
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axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK2,
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(((lock >> 16) & 0x1f) << 10) | 0x1, 0x7fff);
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axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK3,
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(((lock >> 24) & 0x1f) << 10) | 0x3e9, 0x7fff);
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axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER1, filter >> 16, 0x9900);
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axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER2, filter, 0x9900);
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return 0;
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}
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static long axi_clkgen_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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unsigned int d, m, dout;
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axi_clkgen_calc_params(*parent_rate, rate, &d, &m, &dout);
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if (d == 0 || dout == 0 || m == 0)
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return -EINVAL;
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return *parent_rate / d * m / dout;
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}
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static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw,
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unsigned long parent_rate)
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{
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struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
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unsigned int d, m, dout;
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unsigned int reg;
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unsigned long long tmp;
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axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLKOUT0_1, ®);
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dout = (reg & 0x3f) + ((reg >> 6) & 0x3f);
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axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_DIV, ®);
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d = (reg & 0x3f) + ((reg >> 6) & 0x3f);
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axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_FB1, ®);
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m = (reg & 0x3f) + ((reg >> 6) & 0x3f);
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if (d == 0 || dout == 0)
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return 0;
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tmp = (unsigned long long)(parent_rate / d) * m;
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do_div(tmp, dout);
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if (tmp > ULONG_MAX)
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return ULONG_MAX;
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return tmp;
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}
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static int axi_clkgen_enable(struct clk_hw *clk_hw)
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{
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struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
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axi_clkgen_mmcm_enable(axi_clkgen, true);
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return 0;
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}
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static void axi_clkgen_disable(struct clk_hw *clk_hw)
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{
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struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
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axi_clkgen_mmcm_enable(axi_clkgen, false);
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}
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static const struct clk_ops axi_clkgen_ops = {
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.recalc_rate = axi_clkgen_recalc_rate,
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.round_rate = axi_clkgen_round_rate,
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.set_rate = axi_clkgen_set_rate,
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.enable = axi_clkgen_enable,
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.disable = axi_clkgen_disable,
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};
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static const struct of_device_id axi_clkgen_ids[] = {
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{
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.compatible = "adi,axi-clkgen-1.00.a",
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.data = &axi_clkgen_v1_mmcm_ops
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}, {
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.compatible = "adi,axi-clkgen-2.00.a",
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.data = &axi_clkgen_v2_mmcm_ops,
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},
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{ },
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};
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MODULE_DEVICE_TABLE(of, axi_clkgen_ids);
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static int axi_clkgen_probe(struct platform_device *pdev)
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{
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const struct of_device_id *id;
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struct axi_clkgen *axi_clkgen;
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struct clk_init_data init;
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const char *parent_name;
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const char *clk_name;
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struct resource *mem;
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struct clk *clk;
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|
|
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if (!pdev->dev.of_node)
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return -ENODEV;
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|
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id = of_match_node(axi_clkgen_ids, pdev->dev.of_node);
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if (!id)
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return -ENODEV;
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|
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axi_clkgen = devm_kzalloc(&pdev->dev, sizeof(*axi_clkgen), GFP_KERNEL);
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if (!axi_clkgen)
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return -ENOMEM;
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|
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axi_clkgen->mmcm_ops = id->data;
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|
|
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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axi_clkgen->base = devm_ioremap_resource(&pdev->dev, mem);
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if (IS_ERR(axi_clkgen->base))
|
|
return PTR_ERR(axi_clkgen->base);
|
|
|
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parent_name = of_clk_get_parent_name(pdev->dev.of_node, 0);
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if (!parent_name)
|
|
return -EINVAL;
|
|
|
|
clk_name = pdev->dev.of_node->name;
|
|
of_property_read_string(pdev->dev.of_node, "clock-output-names",
|
|
&clk_name);
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|
|
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init.name = clk_name;
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init.ops = &axi_clkgen_ops;
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init.flags = CLK_SET_RATE_GATE;
|
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init.parent_names = &parent_name;
|
|
init.num_parents = 1;
|
|
|
|
axi_clkgen_mmcm_enable(axi_clkgen, false);
|
|
|
|
axi_clkgen->clk_hw.init = &init;
|
|
clk = devm_clk_register(&pdev->dev, &axi_clkgen->clk_hw);
|
|
if (IS_ERR(clk))
|
|
return PTR_ERR(clk);
|
|
|
|
return of_clk_add_provider(pdev->dev.of_node, of_clk_src_simple_get,
|
|
clk);
|
|
}
|
|
|
|
static int axi_clkgen_remove(struct platform_device *pdev)
|
|
{
|
|
of_clk_del_provider(pdev->dev.of_node);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver axi_clkgen_driver = {
|
|
.driver = {
|
|
.name = "adi-axi-clkgen",
|
|
.of_match_table = axi_clkgen_ids,
|
|
},
|
|
.probe = axi_clkgen_probe,
|
|
.remove = axi_clkgen_remove,
|
|
};
|
|
module_platform_driver(axi_clkgen_driver);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
|
|
MODULE_DESCRIPTION("Driver for the Analog Devices' AXI clkgen pcore clock generator");
|