5 Commits

Author	SHA1	Message	Date
zhengly123	9303ddda8e	Add Conv operator and naive CPU implemenation (#5) ... * Add: Conv definition * Add: tensor copy data from vector * Add: CPU conv kernel * Fix: replace Int32 with UInt32 in DataType Co-authored-by: Liyan Zheng <liyan-zheng@outlook.com>	2022-08-17 14:16:01 +08:00
Liyan Zheng	8b685ae4a6	Update: OpAttrs -> OpPerfKey	2022-08-09 14:58:45 +08:00
Liyan Zheng	b7e2096a26	Add: nnet code	2022-08-08 16:02:07 +08:00
Liyan Zheng	6c356d5b42	Add: kernel registry and naive Matmul kernel	2022-08-06 15:58:40 +08:00
Liyan Zheng	e6101b0336	Add: graph, tensor, and operator	2022-07-31 21:44:03 +08:00