These are all either recently unused due to the removal of CFLAGS/etc,
or have been exported by Soong and are no longer necessary.
Change-Id: I5930d43fda21acc8202b3d8ea010fbefb6ae4cf1
The current 32-bit configuration for generic x86_64 targets inherits some
variables (SSE4 support) from the 64-bit configuration, and overrides
the make variables used for other configurations (SSSE3). Ideally, these
would be using different variables, but until then, unify the
configuration for x86_64 targets so that everything is consistent.
Bug: 28694691
Change-Id: I47e67299d4c632e7491d7e73dc0fc6480ef08006
Sandy Bridge actually doesn't have all of these options. For example AVX is only
available on the higher-end SKUs (not on Celeron G550).
Change-Id: Ib595a9a6b464626d0c88525c6aaa4d69176645cc
Otherwise wrong set of memory/string functions is chosen when building atom
image (in Bionic we have libc/arch-x86/atom/atom.mk). Plus this naming is
consistent with other x86 architectures.
Change-Id: I21e899534e7ce10530474a22ceba770422b39d8d
Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
Atomic functions used in external/libcxx/include/atomic when compiled with Clang
will require intrinsic functions exist only for prescott or newer CPUs.
BUG: 17530542
Change-Id: I0c9660ed2ffa75b940981eb8165d88934b39aec5
For ndk docs change, please refer to:
https://android-review.googlesource.com/#/c/110100/
Change-Id: I8428e7a979eb02441066aeeee43ce693d4d0dc8d
Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
Delete x86_64-atom.mk as we don't support 64-bit on old Atom.
Change-Id: I0b9ab61cd9b840f32c30059cb3ba9704c733c42a
Signed-off-by: Varvara Rainchik <varvara.rainchik@intel.com>
This is used for Baytrail targets.
Change-Id: I5a2fa6dbb8217a326ee09f5ea434885718ab3f0c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
Signed-off-by: Fengwei Yin <fengwei.yin@intel.com>
ARCH_X86_HAVE_MMX, ARCH_X86_HAVE_SSE, ARCH_X86_HAVE_SSE2,
and ARCH_X86_HAVE_SSE3 were all always on. There are no longer any makefiles
or code that are conditional on any of these, so let's just remove them
rather than encourage anyone to mess with knobs that don't work.
Change-Id: I5ee095e8041eecff4554ad4801894fbfca69093f
Author: Negreanu Marius Adrian <adrian.m.negreanu@intel.com>
Author: Andrew Boie <andrew.p.boie@intel.com>
Author: Daniel Leung <daniel.leung@intel.com>
Currently, x86 target only has generic i686 and x86-atom
as arch variants. This patch adds the ability to have
more than two arch variants. Defining a new arch variant
is similiar to ARM targets, by adding a new file in
core/combo/arch/x86. These files also define what
capabilities the targeting CPU has (e.g. having SSE2,
SSE3, etc.).
We define arch variants for Sandy Bridge, Ivy Bridge,
Haswell; upcoming arches can be easily added to this
set with future patches.
Change-Id: Iafbce10d205e860738db4a216ff603f9a84d7311
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This is the result of a recent conversation around the x86 ABI
and its relationship with how we build platform images. Briefly:
- We want to use feature-based macros like ARCH_X86_HAVE_$FEATURE
instead of relying on explicit compiler macros like -DUSE_$FEATURE
- We want to allow for other x86-based arch variants, e.g. if
someone wants to build Android for a CPU that doesn't support
the NDK x86 ABI. However, we need to ensure these are not
tagged compatible by mistake (see check at the end of TARGET_linux-x86.mk)
- There are several flags which use is dubious now that we have
a dedicated toolchain to build all the x86 stuff. Comment them
as 'to be considered for removal'. We'll do the proper checks
later.
Change-Id: I7768d7c34d73e274cbf4c09ae831b55280d6bb58
Colin Cross