2007-09-16 05:07:45 +08:00
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/*******************************************************************************
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Intel 10 Gigabit PCI Express Linux driver
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2011-02-23 17:58:39 +08:00
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Copyright(c) 1999 - 2011 Intel Corporation.
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2007-09-16 05:07:45 +08:00
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Contact Information:
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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#ifndef _IXGBE_COMMON_H_
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#define _IXGBE_COMMON_H_
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#include "ixgbe_type.h"
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2011-01-28 10:28:31 +08:00
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#include "ixgbe.h"
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2007-09-16 05:07:45 +08:00
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2010-05-14 01:33:41 +08:00
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u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw);
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2008-09-12 10:59:59 +08:00
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s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw);
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s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw);
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s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw);
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2011-03-18 16:18:22 +08:00
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s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw);
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2008-09-12 10:59:59 +08:00
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s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw);
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2010-12-03 11:32:58 +08:00
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s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
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u32 pba_num_size);
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2008-09-12 10:59:59 +08:00
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s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr);
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s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw);
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2009-02-27 23:44:30 +08:00
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void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw);
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2008-09-12 10:59:59 +08:00
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s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw);
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s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index);
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s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index);
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s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw);
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2009-02-27 23:44:30 +08:00
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s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
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2011-04-20 16:49:06 +08:00
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s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
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u16 words, u16 *data);
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2010-05-14 01:33:41 +08:00
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s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data);
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2011-04-20 16:49:06 +08:00
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s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
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u16 words, u16 *data);
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2011-03-24 08:57:50 +08:00
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s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
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2011-04-20 16:49:06 +08:00
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s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
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u16 words, u16 *data);
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2008-09-12 10:59:59 +08:00
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s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
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u16 *data);
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2011-04-20 16:49:06 +08:00
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s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
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u16 words, u16 *data);
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2010-11-17 11:27:15 +08:00
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u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw);
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2008-09-12 10:59:59 +08:00
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s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
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u16 *checksum_val);
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s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw);
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s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
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u32 enable_addr);
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s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index);
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s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw);
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2010-03-24 06:58:01 +08:00
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s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
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struct net_device *netdev);
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2008-09-12 10:59:59 +08:00
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s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw);
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s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw);
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2009-02-27 23:44:30 +08:00
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s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval);
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2009-06-04 19:11:13 +08:00
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s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packtetbuf_num);
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2009-02-07 13:46:54 +08:00
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s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw);
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2007-09-16 05:07:45 +08:00
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2008-09-12 10:59:59 +08:00
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s32 ixgbe_validate_mac_addr(u8 *mac_addr);
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2007-09-16 05:07:45 +08:00
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s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask);
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void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask);
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s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
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2010-05-14 01:33:41 +08:00
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s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr);
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s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
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s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
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s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw);
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s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan,
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u32 vind, bool vlan_on);
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s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw);
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s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw,
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ixgbe_link_speed *speed,
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bool *link_up, bool link_up_wait_to_complete);
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2010-11-17 11:27:15 +08:00
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s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
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u16 *wwpn_prefix);
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2009-04-08 21:20:31 +08:00
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s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index);
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s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index);
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2010-11-18 11:02:52 +08:00
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void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf);
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void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf);
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2011-03-31 17:36:18 +08:00
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s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps);
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2009-04-08 21:20:31 +08:00
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2007-09-16 05:07:45 +08:00
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#define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
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2009-02-27 23:44:30 +08:00
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#ifndef writeq
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#define writeq(val, addr) writel((u32) (val), addr); \
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writel((u32) (val >> 32), (addr + 4));
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#endif
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#define IXGBE_WRITE_REG64(a, reg, value) writeq((value), ((a)->hw_addr + (reg)))
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2007-09-16 05:07:45 +08:00
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#define IXGBE_READ_REG(a, reg) readl((a)->hw_addr + (reg))
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#define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) (\
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writel((value), ((a)->hw_addr + (reg) + ((offset) << 2))))
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#define IXGBE_READ_REG_ARRAY(a, reg, offset) (\
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readl((a)->hw_addr + (reg) + ((offset) << 2)))
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#define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS)
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#define hw_dbg(hw, format, arg...) \
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2011-01-28 10:28:31 +08:00
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netdev_dbg(((struct ixgbe_adapter *)(hw->back))->netdev, format, ##arg)
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2010-06-04 00:53:41 +08:00
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#define e_dev_info(format, arg...) \
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dev_info(&adapter->pdev->dev, format, ## arg)
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#define e_dev_warn(format, arg...) \
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dev_warn(&adapter->pdev->dev, format, ## arg)
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#define e_dev_err(format, arg...) \
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dev_err(&adapter->pdev->dev, format, ## arg)
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#define e_dev_notice(format, arg...) \
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dev_notice(&adapter->pdev->dev, format, ## arg)
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2010-07-02 04:05:12 +08:00
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#define e_info(msglvl, format, arg...) \
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netif_info(adapter, msglvl, adapter->netdev, format, ## arg)
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#define e_err(msglvl, format, arg...) \
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netif_err(adapter, msglvl, adapter->netdev, format, ## arg)
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#define e_warn(msglvl, format, arg...) \
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netif_warn(adapter, msglvl, adapter->netdev, format, ## arg)
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#define e_crit(msglvl, format, arg...) \
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netif_crit(adapter, msglvl, adapter->netdev, format, ## arg)
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2007-09-16 05:07:45 +08:00
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#endif /* IXGBE_COMMON */
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