2014-07-25 00:04:10 +08:00
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/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _INTEL_LRC_H_
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#define _INTEL_LRC_H_
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2014-08-07 20:23:20 +08:00
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/* Execlists regs */
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#define RING_ELSP(ring) ((ring)->mmio_base+0x230)
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#define RING_EXECLIST_STATUS(ring) ((ring)->mmio_base+0x234)
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#define RING_CONTEXT_CONTROL(ring) ((ring)->mmio_base+0x244)
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#define RING_CONTEXT_STATUS_BUF(ring) ((ring)->mmio_base+0x370)
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#define RING_CONTEXT_STATUS_PTR(ring) ((ring)->mmio_base+0x3a0)
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2014-07-25 00:04:22 +08:00
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/* Logical Rings */
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void intel_logical_ring_stop(struct intel_engine_cs *ring);
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void intel_logical_ring_cleanup(struct intel_engine_cs *ring);
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int intel_logical_rings_init(struct drm_device *dev);
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2014-07-25 00:04:29 +08:00
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int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf);
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2014-07-25 00:04:26 +08:00
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void intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf);
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2014-07-25 00:04:48 +08:00
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/**
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* intel_logical_ring_advance() - advance the ringbuffer tail
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* @ringbuf: Ringbuffer to advance.
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*
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* The tail is only updated in our logical ringbuffer struct.
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*/
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2014-07-25 00:04:26 +08:00
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static inline void intel_logical_ring_advance(struct intel_ringbuffer *ringbuf)
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{
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ringbuf->tail &= ringbuf->size - 1;
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}
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2014-07-25 00:04:48 +08:00
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/**
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* intel_logical_ring_emit() - write a DWORD to the ringbuffer.
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* @ringbuf: Ringbuffer to write to.
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* @data: DWORD to write.
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*/
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2014-07-25 00:04:26 +08:00
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static inline void intel_logical_ring_emit(struct intel_ringbuffer *ringbuf,
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u32 data)
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{
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iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
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ringbuf->tail += 4;
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}
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int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf, int num_dwords);
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2014-07-25 00:04:12 +08:00
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/* Logical Ring Contexts */
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2014-08-21 18:40:54 +08:00
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int intel_lr_context_render_state_init(struct intel_engine_cs *ring,
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struct intel_context *ctx);
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2014-07-25 00:04:12 +08:00
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void intel_lr_context_free(struct intel_context *ctx);
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int intel_lr_context_deferred_create(struct intel_context *ctx,
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struct intel_engine_cs *ring);
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2014-07-25 00:04:11 +08:00
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/* Execlists */
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int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists);
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2014-07-25 00:04:22 +08:00
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int intel_execlists_submission(struct drm_device *dev, struct drm_file *file,
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struct intel_engine_cs *ring,
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struct intel_context *ctx,
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struct drm_i915_gem_execbuffer2 *args,
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struct list_head *vmas,
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struct drm_i915_gem_object *batch_obj,
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u64 exec_start, u32 flags);
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2014-07-25 00:04:36 +08:00
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u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj);
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2014-07-25 00:04:11 +08:00
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2014-07-25 00:04:48 +08:00
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/**
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* struct intel_ctx_submit_request - queued context submission request
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* @ctx: Context to submit to the ELSP.
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* @ring: Engine to submit it to.
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* @tail: how far in the context's ringbuffer this request goes to.
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* @execlist_link: link in the submission queue.
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* @work: workqueue for processing this request in a bottom half.
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* @elsp_submitted: no. of times this request has been sent to the ELSP.
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*
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* The ELSP only accepts two elements at a time, so we queue context/tail
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* pairs on a given queue (ring->execlist_queue) until the hardware is
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* available. The queue serves a double purpose: we also use it to keep track
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* of the up to 2 contexts currently in the hardware (usually one in execution
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* and the other queued up by the GPU): We only remove elements from the head
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* of the queue when the hardware informs us that an element has been
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* completed.
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*
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* All accesses to the queue are mediated by a spinlock (ring->execlist_lock).
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*/
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2014-07-25 00:04:38 +08:00
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struct intel_ctx_submit_request {
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struct intel_context *ctx;
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struct intel_engine_cs *ring;
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u32 tail;
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struct list_head execlist_link;
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drm/i915/bdw: Handle context switch events
Handle all context status events in the context status buffer on every
context switch interrupt. We only remove work from the execlist queue
after a context status buffer reports that it has completed and we only
attempt to schedule new contexts on interrupt when a previously submitted
context completes (unless no contexts are queued, which means the GPU is
free).
We canot call intel_runtime_pm_get() in an interrupt (or with a spinlock
grabbed, FWIW), because it might sleep, which is not a nice thing to do.
Instead, do the runtime_pm get/put together with the create/destroy request,
and handle the forcewake get/put directly.
Signed-off-by: Thomas Daniel <thomas.daniel@intel.com>
v2: Unreferencing the context when we are freeing the request might free
the backing bo, which requires the struct_mutex to be grabbed, so defer
unreferencing and freeing to a bottom half.
v3:
- Ack the interrupt inmediately, before trying to handle it (fix for
missing interrupts by Bob Beckett <robert.beckett@intel.com>).
- Update the Context Status Buffer Read Pointer, just in case (spotted
by Damien Lespiau).
v4: New namespace and multiple rebase changes.
v5: Squash with "drm/i915/bdw: Do not call intel_runtime_pm_get() in an
interrupt", as suggested by Daniel.
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
[danvet: Checkpatch ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-25 00:04:39 +08:00
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struct work_struct work;
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drm/i915/bdw: Avoid non-lite-restore preemptions
In the current Execlists feeding mechanism, full preemption is not
supported yet: only lite-restores are allowed (this is: the GPU
simply samples a new tail pointer for the context currently in
execution).
But we have identified an scenario in which a full preemption occurs:
1) We submit two contexts for execution (A & B).
2) The GPU finishes with the first one (A), switches to the second one
(B) and informs us.
3) We submit B again (hoping to cause a lite restore) together with C,
but in the time we spend writing to the ELSP, the GPU finishes B.
4) The GPU start executing B again (since we told it so).
5) We receive a B finished interrupt and, mistakenly, we submit C (again)
and D, causing a full preemption of B.
The race is avoided by keeping track of how many times a context has been
submitted to the hardware and by better discriminating the received context
switch interrupts: in the example, when we have submitted B twice, we won´t
submit C and D as soon as we receive the notification that B is completed
because we were expecting to get a LITE_RESTORE and we didn´t, so we know a
second completion will be received shortly.
Without this explicit checking, somehow, the batch buffer execution order
gets messed with. This can be verified with the IGT test I sent together with
the series. I don´t know the exact mechanism by which the pre-emption messes
with the execution order but, since other people is working on the Scheduler
+ Preemption on Execlists, I didn´t try to fix it. In these series, only Lite
Restores are supported (other kind of preemptions WARN).
v2: elsp_submitted belongs in the new intel_ctx_submit_request. Several
rebase changes.
v3: Clarify how the race is avoided, as requested by Daniel.
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
[danvet: Align function parameters ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-25 00:04:40 +08:00
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int elsp_submitted;
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2014-07-25 00:04:38 +08:00
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};
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drm/i915/bdw: Handle context switch events
Handle all context status events in the context status buffer on every
context switch interrupt. We only remove work from the execlist queue
after a context status buffer reports that it has completed and we only
attempt to schedule new contexts on interrupt when a previously submitted
context completes (unless no contexts are queued, which means the GPU is
free).
We canot call intel_runtime_pm_get() in an interrupt (or with a spinlock
grabbed, FWIW), because it might sleep, which is not a nice thing to do.
Instead, do the runtime_pm get/put together with the create/destroy request,
and handle the forcewake get/put directly.
Signed-off-by: Thomas Daniel <thomas.daniel@intel.com>
v2: Unreferencing the context when we are freeing the request might free
the backing bo, which requires the struct_mutex to be grabbed, so defer
unreferencing and freeing to a bottom half.
v3:
- Ack the interrupt inmediately, before trying to handle it (fix for
missing interrupts by Bob Beckett <robert.beckett@intel.com>).
- Update the Context Status Buffer Read Pointer, just in case (spotted
by Damien Lespiau).
v4: New namespace and multiple rebase changes.
v5: Squash with "drm/i915/bdw: Do not call intel_runtime_pm_get() in an
interrupt", as suggested by Daniel.
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
[danvet: Checkpatch ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-25 00:04:39 +08:00
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void intel_execlists_handle_ctx_events(struct intel_engine_cs *ring);
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2014-07-25 00:04:10 +08:00
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#endif /* _INTEL_LRC_H_ */
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