2013-09-12 16:36:16 +08:00
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/*
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* arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority
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*
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* Copyright 2012 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <asm/blackfin.h>
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#include <asm/scb.h>
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struct scb_mi_prio scb_data[] = {
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#ifdef CONFIG_SCB0_MI0
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{ REG_SCB0_ARBR0, REG_SCB0_ARBW0, 32, {
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CONFIG_SCB0_MI0_SLOT0,
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CONFIG_SCB0_MI0_SLOT1,
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CONFIG_SCB0_MI0_SLOT2,
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CONFIG_SCB0_MI0_SLOT3,
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CONFIG_SCB0_MI0_SLOT4,
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CONFIG_SCB0_MI0_SLOT5,
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CONFIG_SCB0_MI0_SLOT6,
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CONFIG_SCB0_MI0_SLOT7,
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CONFIG_SCB0_MI0_SLOT8,
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CONFIG_SCB0_MI0_SLOT9,
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CONFIG_SCB0_MI0_SLOT10,
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CONFIG_SCB0_MI0_SLOT11,
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CONFIG_SCB0_MI0_SLOT12,
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CONFIG_SCB0_MI0_SLOT13,
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CONFIG_SCB0_MI0_SLOT14,
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CONFIG_SCB0_MI0_SLOT15,
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CONFIG_SCB0_MI0_SLOT16,
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CONFIG_SCB0_MI0_SLOT17,
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CONFIG_SCB0_MI0_SLOT18,
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CONFIG_SCB0_MI0_SLOT19,
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CONFIG_SCB0_MI0_SLOT20,
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CONFIG_SCB0_MI0_SLOT21,
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CONFIG_SCB0_MI0_SLOT22,
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CONFIG_SCB0_MI0_SLOT23,
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CONFIG_SCB0_MI0_SLOT24,
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CONFIG_SCB0_MI0_SLOT25,
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CONFIG_SCB0_MI0_SLOT26,
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CONFIG_SCB0_MI0_SLOT27,
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CONFIG_SCB0_MI0_SLOT28,
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CONFIG_SCB0_MI0_SLOT29,
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CONFIG_SCB0_MI0_SLOT30,
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CONFIG_SCB0_MI0_SLOT31
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},
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},
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#endif
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#ifdef CONFIG_SCB0_MI1
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{ REG_SCB0_ARBR1, REG_SCB0_ARBW1, 32, {
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CONFIG_SCB0_MI1_SLOT0,
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CONFIG_SCB0_MI1_SLOT1,
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CONFIG_SCB0_MI1_SLOT2,
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CONFIG_SCB0_MI1_SLOT3,
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CONFIG_SCB0_MI1_SLOT4,
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CONFIG_SCB0_MI1_SLOT5,
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CONFIG_SCB0_MI1_SLOT6,
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CONFIG_SCB0_MI1_SLOT7,
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CONFIG_SCB0_MI1_SLOT8,
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CONFIG_SCB0_MI1_SLOT9,
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CONFIG_SCB0_MI1_SLOT10,
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CONFIG_SCB0_MI1_SLOT11,
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CONFIG_SCB0_MI1_SLOT12,
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CONFIG_SCB0_MI1_SLOT13,
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CONFIG_SCB0_MI1_SLOT14,
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CONFIG_SCB0_MI1_SLOT15,
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CONFIG_SCB0_MI1_SLOT16,
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CONFIG_SCB0_MI1_SLOT17,
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CONFIG_SCB0_MI1_SLOT18,
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CONFIG_SCB0_MI1_SLOT19,
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CONFIG_SCB0_MI1_SLOT20,
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CONFIG_SCB0_MI1_SLOT21,
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CONFIG_SCB0_MI1_SLOT22,
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CONFIG_SCB0_MI1_SLOT23,
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CONFIG_SCB0_MI1_SLOT24,
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CONFIG_SCB0_MI1_SLOT25,
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CONFIG_SCB0_MI1_SLOT26,
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CONFIG_SCB0_MI1_SLOT27,
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CONFIG_SCB0_MI1_SLOT28,
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CONFIG_SCB0_MI1_SLOT29,
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CONFIG_SCB0_MI1_SLOT30,
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CONFIG_SCB0_MI1_SLOT31
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},
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},
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#endif
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#ifdef CONFIG_SCB0_MI2
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{ REG_SCB0_ARBR2, REG_SCB0_ARBW2, 32, {
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CONFIG_SCB0_MI2_SLOT0,
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CONFIG_SCB0_MI2_SLOT1,
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CONFIG_SCB0_MI2_SLOT2,
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CONFIG_SCB0_MI2_SLOT3,
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CONFIG_SCB0_MI2_SLOT4,
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CONFIG_SCB0_MI2_SLOT5,
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CONFIG_SCB0_MI2_SLOT6,
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CONFIG_SCB0_MI2_SLOT7,
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CONFIG_SCB0_MI2_SLOT8,
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CONFIG_SCB0_MI2_SLOT9,
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CONFIG_SCB0_MI2_SLOT10,
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CONFIG_SCB0_MI2_SLOT11,
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CONFIG_SCB0_MI2_SLOT12,
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CONFIG_SCB0_MI2_SLOT13,
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CONFIG_SCB0_MI2_SLOT14,
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CONFIG_SCB0_MI2_SLOT15,
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CONFIG_SCB0_MI2_SLOT16,
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CONFIG_SCB0_MI2_SLOT17,
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CONFIG_SCB0_MI2_SLOT18,
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CONFIG_SCB0_MI2_SLOT19,
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CONFIG_SCB0_MI2_SLOT20,
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CONFIG_SCB0_MI2_SLOT21,
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CONFIG_SCB0_MI2_SLOT22,
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CONFIG_SCB0_MI2_SLOT23,
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CONFIG_SCB0_MI2_SLOT24,
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CONFIG_SCB0_MI2_SLOT25,
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CONFIG_SCB0_MI2_SLOT26,
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CONFIG_SCB0_MI2_SLOT27,
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CONFIG_SCB0_MI2_SLOT28,
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CONFIG_SCB0_MI2_SLOT29,
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CONFIG_SCB0_MI2_SLOT30,
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CONFIG_SCB0_MI2_SLOT31
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},
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},
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#endif
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#ifdef CONFIG_SCB0_MI3
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{ REG_SCB0_ARBR3, REG_SCB0_ARBW3, 32, {
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CONFIG_SCB0_MI3_SLOT0,
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CONFIG_SCB0_MI3_SLOT1,
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CONFIG_SCB0_MI3_SLOT2,
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CONFIG_SCB0_MI3_SLOT3,
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CONFIG_SCB0_MI3_SLOT4,
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CONFIG_SCB0_MI3_SLOT5,
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CONFIG_SCB0_MI3_SLOT6,
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CONFIG_SCB0_MI3_SLOT7,
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CONFIG_SCB0_MI3_SLOT8,
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CONFIG_SCB0_MI3_SLOT9,
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CONFIG_SCB0_MI3_SLOT10,
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CONFIG_SCB0_MI3_SLOT11,
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CONFIG_SCB0_MI3_SLOT12,
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CONFIG_SCB0_MI3_SLOT13,
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CONFIG_SCB0_MI3_SLOT14,
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CONFIG_SCB0_MI3_SLOT15,
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CONFIG_SCB0_MI3_SLOT16,
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CONFIG_SCB0_MI3_SLOT17,
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CONFIG_SCB0_MI3_SLOT18,
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CONFIG_SCB0_MI3_SLOT19,
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CONFIG_SCB0_MI3_SLOT20,
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CONFIG_SCB0_MI3_SLOT21,
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CONFIG_SCB0_MI3_SLOT22,
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CONFIG_SCB0_MI3_SLOT23,
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CONFIG_SCB0_MI3_SLOT24,
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CONFIG_SCB0_MI3_SLOT25,
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CONFIG_SCB0_MI3_SLOT26,
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CONFIG_SCB0_MI3_SLOT27,
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CONFIG_SCB0_MI3_SLOT28,
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CONFIG_SCB0_MI3_SLOT29,
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CONFIG_SCB0_MI3_SLOT30,
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CONFIG_SCB0_MI3_SLOT31
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},
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},
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#endif
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#ifdef CONFIG_SCB0_MI4
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{ REG_SCB0_ARBR4, REG_SCB4_ARBW0, 32, {
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CONFIG_SCB0_MI4_SLOT0,
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CONFIG_SCB0_MI4_SLOT1,
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CONFIG_SCB0_MI4_SLOT2,
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CONFIG_SCB0_MI4_SLOT3,
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CONFIG_SCB0_MI4_SLOT4,
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CONFIG_SCB0_MI4_SLOT5,
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CONFIG_SCB0_MI4_SLOT6,
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CONFIG_SCB0_MI4_SLOT7,
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CONFIG_SCB0_MI4_SLOT8,
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CONFIG_SCB0_MI4_SLOT9,
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CONFIG_SCB0_MI4_SLOT10,
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CONFIG_SCB0_MI4_SLOT11,
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CONFIG_SCB0_MI4_SLOT12,
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CONFIG_SCB0_MI4_SLOT13,
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CONFIG_SCB0_MI4_SLOT14,
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CONFIG_SCB0_MI4_SLOT15,
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CONFIG_SCB0_MI4_SLOT16,
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CONFIG_SCB0_MI4_SLOT17,
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CONFIG_SCB0_MI4_SLOT18,
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CONFIG_SCB0_MI4_SLOT19,
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CONFIG_SCB0_MI4_SLOT20,
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CONFIG_SCB0_MI4_SLOT21,
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CONFIG_SCB0_MI4_SLOT22,
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CONFIG_SCB0_MI4_SLOT23,
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CONFIG_SCB0_MI4_SLOT24,
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CONFIG_SCB0_MI4_SLOT25,
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CONFIG_SCB0_MI4_SLOT26,
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CONFIG_SCB0_MI4_SLOT27,
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CONFIG_SCB0_MI4_SLOT28,
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CONFIG_SCB0_MI4_SLOT29,
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CONFIG_SCB0_MI4_SLOT30,
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CONFIG_SCB0_MI4_SLOT31
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},
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},
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#endif
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#ifdef CONFIG_SCB0_MI5
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{ REG_SCB0_ARBR5, REG_SCB0_ARBW5, 16, {
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CONFIG_SCB0_MI5_SLOT0,
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CONFIG_SCB0_MI5_SLOT1,
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CONFIG_SCB0_MI5_SLOT2,
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CONFIG_SCB0_MI5_SLOT3,
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CONFIG_SCB0_MI5_SLOT4,
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CONFIG_SCB0_MI5_SLOT5,
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CONFIG_SCB0_MI5_SLOT6,
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CONFIG_SCB0_MI5_SLOT7,
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CONFIG_SCB0_MI5_SLOT8,
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CONFIG_SCB0_MI5_SLOT9,
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CONFIG_SCB0_MI5_SLOT10,
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CONFIG_SCB0_MI5_SLOT11,
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CONFIG_SCB0_MI5_SLOT12,
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CONFIG_SCB0_MI5_SLOT13,
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CONFIG_SCB0_MI5_SLOT14,
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2012-11-15 12:32:26 +08:00
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CONFIG_SCB0_MI5_SLOT15
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},
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},
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#endif
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#ifdef CONFIG_SCB1_MI0
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{ REG_SCB1_ARBR0, REG_SCB1_ARBW0, 20, {
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CONFIG_SCB1_MI0_SLOT0,
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CONFIG_SCB1_MI0_SLOT1,
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CONFIG_SCB1_MI0_SLOT2,
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CONFIG_SCB1_MI0_SLOT3,
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CONFIG_SCB1_MI0_SLOT4,
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CONFIG_SCB1_MI0_SLOT5,
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CONFIG_SCB1_MI0_SLOT6,
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CONFIG_SCB1_MI0_SLOT7,
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CONFIG_SCB1_MI0_SLOT8,
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CONFIG_SCB1_MI0_SLOT9,
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CONFIG_SCB1_MI0_SLOT10,
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CONFIG_SCB1_MI0_SLOT11,
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CONFIG_SCB1_MI0_SLOT12,
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CONFIG_SCB1_MI0_SLOT13,
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CONFIG_SCB1_MI0_SLOT14,
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CONFIG_SCB1_MI0_SLOT15,
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CONFIG_SCB1_MI0_SLOT16,
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CONFIG_SCB1_MI0_SLOT17,
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CONFIG_SCB1_MI0_SLOT18,
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CONFIG_SCB1_MI0_SLOT19
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},
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},
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#endif
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#ifdef CONFIG_SCB2_MI0
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{ REG_SCB2_ARBR0, REG_SCB2_ARBW0, 10, {
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CONFIG_SCB2_MI0_SLOT0,
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CONFIG_SCB2_MI0_SLOT1,
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CONFIG_SCB2_MI0_SLOT2,
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CONFIG_SCB2_MI0_SLOT3,
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CONFIG_SCB2_MI0_SLOT4,
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CONFIG_SCB2_MI0_SLOT5,
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CONFIG_SCB2_MI0_SLOT6,
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CONFIG_SCB2_MI0_SLOT7,
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CONFIG_SCB2_MI0_SLOT8,
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CONFIG_SCB2_MI0_SLOT9
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},
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},
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#endif
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#ifdef CONFIG_SCB3_MI0
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{ REG_SCB3_ARBR0, REG_SCB3_ARBW0, 16, {
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CONFIG_SCB3_MI0_SLOT0,
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CONFIG_SCB3_MI0_SLOT1,
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CONFIG_SCB3_MI0_SLOT2,
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CONFIG_SCB3_MI0_SLOT3,
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CONFIG_SCB3_MI0_SLOT4,
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CONFIG_SCB3_MI0_SLOT5,
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CONFIG_SCB3_MI0_SLOT6,
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CONFIG_SCB3_MI0_SLOT7,
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CONFIG_SCB3_MI0_SLOT8,
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CONFIG_SCB3_MI0_SLOT9,
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CONFIG_SCB3_MI0_SLOT10,
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CONFIG_SCB3_MI0_SLOT11,
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CONFIG_SCB3_MI0_SLOT12,
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CONFIG_SCB3_MI0_SLOT13,
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CONFIG_SCB3_MI0_SLOT14,
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CONFIG_SCB3_MI0_SLOT15
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},
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},
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#endif
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#ifdef CONFIG_SCB4_MI0
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{ REG_SCB4_ARBR0, REG_SCB4_ARBW0, 16, {
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CONFIG_SCB4_MI0_SLOT0,
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CONFIG_SCB4_MI0_SLOT1,
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CONFIG_SCB4_MI0_SLOT2,
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CONFIG_SCB4_MI0_SLOT3,
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CONFIG_SCB4_MI0_SLOT4,
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CONFIG_SCB4_MI0_SLOT5,
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CONFIG_SCB4_MI0_SLOT6,
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CONFIG_SCB4_MI0_SLOT7,
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CONFIG_SCB4_MI0_SLOT8,
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CONFIG_SCB4_MI0_SLOT9,
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CONFIG_SCB4_MI0_SLOT10,
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CONFIG_SCB4_MI0_SLOT11,
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CONFIG_SCB4_MI0_SLOT12,
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CONFIG_SCB4_MI0_SLOT13,
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CONFIG_SCB4_MI0_SLOT14,
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CONFIG_SCB4_MI0_SLOT15
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},
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},
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#endif
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#ifdef CONFIG_SCB5_MI0
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{ REG_SCB5_ARBR0, REG_SCB5_ARBW0, 8, {
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CONFIG_SCB5_MI0_SLOT0,
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CONFIG_SCB5_MI0_SLOT1,
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CONFIG_SCB5_MI0_SLOT2,
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CONFIG_SCB5_MI0_SLOT3,
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CONFIG_SCB5_MI0_SLOT4,
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CONFIG_SCB5_MI0_SLOT5,
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CONFIG_SCB5_MI0_SLOT6,
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CONFIG_SCB5_MI0_SLOT7
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},
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},
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#endif
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#ifdef CONFIG_SCB6_MI0
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{ REG_SCB6_ARBR0, REG_SCB6_ARBW0, 4, {
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CONFIG_SCB6_MI0_SLOT0,
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CONFIG_SCB6_MI0_SLOT1,
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CONFIG_SCB6_MI0_SLOT2,
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CONFIG_SCB6_MI0_SLOT3
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},
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},
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#endif
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#ifdef CONFIG_SCB7_MI0
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{ REG_SCB7_ARBR0, REG_SCB7_ARBW0, 6, {
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CONFIG_SCB7_MI0_SLOT0,
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CONFIG_SCB7_MI0_SLOT1,
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CONFIG_SCB7_MI0_SLOT2,
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CONFIG_SCB7_MI0_SLOT3,
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CONFIG_SCB7_MI0_SLOT4,
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CONFIG_SCB7_MI0_SLOT5
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},
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},
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#endif
|
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#ifdef CONFIG_SCB8_MI0
|
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{ REG_SCB8_ARBR0, REG_SCB8_ARBW0, 8, {
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CONFIG_SCB8_MI0_SLOT0,
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CONFIG_SCB8_MI0_SLOT1,
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CONFIG_SCB8_MI0_SLOT2,
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CONFIG_SCB8_MI0_SLOT3,
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CONFIG_SCB8_MI0_SLOT4,
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CONFIG_SCB8_MI0_SLOT5,
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CONFIG_SCB8_MI0_SLOT6,
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CONFIG_SCB8_MI0_SLOT7
|
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},
|
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},
|
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|
#endif
|
|
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|
|
#ifdef CONFIG_SCB9_MI0
|
|
|
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|
{ REG_SCB9_ARBR0, REG_SCB9_ARBW0, 10, {
|
|
|
|
|
CONFIG_SCB9_MI0_SLOT0,
|
|
|
|
|
CONFIG_SCB9_MI0_SLOT1,
|
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|
|
|
CONFIG_SCB9_MI0_SLOT2,
|
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|
CONFIG_SCB9_MI0_SLOT3,
|
|
|
|
|
CONFIG_SCB9_MI0_SLOT4,
|
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|
|
|
CONFIG_SCB9_MI0_SLOT5,
|
|
|
|
|
CONFIG_SCB9_MI0_SLOT6,
|
|
|
|
|
CONFIG_SCB9_MI0_SLOT7,
|
|
|
|
|
CONFIG_SCB9_MI0_SLOT8,
|
|
|
|
|
CONFIG_SCB9_MI0_SLOT9
|
2013-09-12 16:36:16 +08:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
#endif
|
|
|
|
|
{ 0, }
|
|
|
|
|
};
|
