2005-04-17 06:20:36 +08:00
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/*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* Setting up the clock on the MIPS boards.
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*/
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#include <linux/types.h>
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2011-06-02 02:04:57 +08:00
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#include <linux/i8253.h>
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2005-04-17 06:20:36 +08:00
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#include <linux/init.h>
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#include <linux/kernel_stat.h>
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2017-04-19 20:26:45 +08:00
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#include <linux/libfdt.h>
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2016-04-23 01:19:15 +08:00
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#include <linux/math64.h>
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2005-04-17 06:20:36 +08:00
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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2014-10-21 03:03:53 +08:00
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#include <linux/irqchip/mips-gic.h>
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2005-04-17 06:20:36 +08:00
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#include <linux/timex.h>
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#include <linux/mc146818rtc.h>
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2013-09-17 23:58:10 +08:00
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#include <asm/cpu.h>
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2005-04-17 06:20:36 +08:00
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#include <asm/mipsregs.h>
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2006-04-05 16:45:45 +08:00
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#include <asm/mipsmtregs.h>
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2005-07-14 23:57:16 +08:00
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#include <asm/hardirq.h>
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#include <asm/irq.h>
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2005-04-17 06:20:36 +08:00
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#include <asm/div64.h>
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2012-03-29 01:30:02 +08:00
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#include <asm/setup.h>
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2005-04-17 06:20:36 +08:00
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#include <asm/time.h>
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#include <asm/mc146818-time.h>
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2005-07-14 23:57:16 +08:00
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#include <asm/msc01_ic.h>
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2005-04-17 06:20:36 +08:00
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#include <asm/mips-boards/generic.h>
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2005-07-14 23:57:16 +08:00
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#include <asm/mips-boards/maltaint.h>
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2005-04-17 06:20:36 +08:00
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2005-07-14 23:57:16 +08:00
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static int mips_cpu_timer_irq;
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2008-04-29 00:14:26 +08:00
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static int mips_cpu_perf_irq;
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2007-06-21 05:27:10 +08:00
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extern int cp0_perfcount_irq;
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2005-04-17 06:20:36 +08:00
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2014-10-21 03:04:01 +08:00
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static unsigned int gic_frequency;
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2006-10-08 02:44:33 +08:00
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static void mips_timer_dispatch(void)
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2005-04-17 06:20:36 +08:00
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{
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2006-10-08 02:44:33 +08:00
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do_IRQ(mips_cpu_timer_irq);
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2005-07-14 23:57:16 +08:00
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}
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2007-05-25 05:24:20 +08:00
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static void mips_perf_dispatch(void)
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{
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2008-04-29 00:14:26 +08:00
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do_IRQ(mips_cpu_perf_irq);
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2007-05-25 05:24:20 +08:00
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}
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2012-12-07 11:51:04 +08:00
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static unsigned int freqround(unsigned int freq, unsigned int amount)
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{
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freq += amount;
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freq -= freq % (amount*2);
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return freq;
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}
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2005-04-17 06:20:36 +08:00
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/*
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2012-12-07 11:51:04 +08:00
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* Estimate CPU and GIC frequencies.
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2005-04-17 06:20:36 +08:00
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*/
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2012-12-07 11:51:04 +08:00
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static void __init estimate_frequencies(void)
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2005-04-17 06:20:36 +08:00
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{
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2006-11-01 03:53:15 +08:00
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unsigned long flags;
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2012-12-07 11:51:04 +08:00
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unsigned int count, start;
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2016-04-23 01:19:15 +08:00
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unsigned char secs1, secs2, ctrl;
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int secs;
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2016-12-22 03:32:01 +08:00
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u64 giccount = 0, gicstart = 0;
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2005-04-17 06:20:36 +08:00
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2014-05-29 17:16:36 +08:00
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#if defined(CONFIG_KVM_GUEST) && CONFIG_KVM_GUEST_TIMER_FREQ
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mips_hpt_frequency = CONFIG_KVM_GUEST_TIMER_FREQ * 1000000;
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2012-11-22 10:34:03 +08:00
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return;
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#endif
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2005-04-17 06:20:36 +08:00
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local_irq_save(flags);
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2016-04-23 01:19:14 +08:00
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if (gic_present)
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gic_start_count();
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2016-04-23 01:19:15 +08:00
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/*
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* Read counters exactly on rising edge of update flag.
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* This helps get an accurate reading under virtualisation.
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*/
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2005-04-17 06:20:36 +08:00
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while (CMOS_READ(RTC_REG_A) & RTC_UIP);
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while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
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2006-11-01 02:33:09 +08:00
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start = read_c0_count();
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2016-04-23 01:19:14 +08:00
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if (gic_present)
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2014-10-21 03:03:48 +08:00
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gicstart = gic_read_count();
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2005-04-17 06:20:36 +08:00
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2016-04-23 01:19:15 +08:00
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/* Wait for falling edge before reading RTC. */
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2005-04-17 06:20:36 +08:00
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while (CMOS_READ(RTC_REG_A) & RTC_UIP);
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2016-04-23 01:19:15 +08:00
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secs1 = CMOS_READ(RTC_SECONDS);
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2005-04-17 06:20:36 +08:00
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2016-04-23 01:19:15 +08:00
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/* Read counters again exactly on rising edge of update flag. */
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while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
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2012-12-07 11:51:04 +08:00
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count = read_c0_count();
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if (gic_present)
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2014-10-21 03:03:48 +08:00
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giccount = gic_read_count();
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2005-04-17 06:20:36 +08:00
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2016-04-23 01:19:15 +08:00
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/* Wait for falling edge before reading RTC again. */
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while (CMOS_READ(RTC_REG_A) & RTC_UIP);
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secs2 = CMOS_READ(RTC_SECONDS);
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ctrl = CMOS_READ(RTC_CONTROL);
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2005-04-17 06:20:36 +08:00
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local_irq_restore(flags);
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2016-04-23 01:19:15 +08:00
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if (!(ctrl & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
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secs1 = bcd2bin(secs1);
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secs2 = bcd2bin(secs2);
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}
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secs = secs2 - secs1;
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if (secs < 1)
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secs += 60;
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2012-12-07 11:51:04 +08:00
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count -= start;
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2016-04-23 01:19:15 +08:00
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count /= secs;
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2012-12-07 11:51:04 +08:00
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mips_hpt_frequency = count;
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2013-04-11 05:28:36 +08:00
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if (gic_present) {
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2016-04-23 01:19:15 +08:00
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giccount = div_u64(giccount - gicstart, secs);
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2012-12-07 11:51:04 +08:00
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gic_frequency = giccount;
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2013-04-11 05:28:36 +08:00
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}
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2005-04-17 06:20:36 +08:00
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}
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2009-08-14 21:47:31 +08:00
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void read_persistent_clock(struct timespec *ts)
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2005-04-17 06:20:36 +08:00
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{
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2009-08-14 21:47:31 +08:00
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ts->tv_sec = mc146818_get_cmos_time();
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ts->tv_nsec = 0;
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2005-04-17 06:20:36 +08:00
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}
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2015-01-29 19:14:10 +08:00
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int get_c0_fdc_int(void)
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{
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2015-04-17 17:44:15 +08:00
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/*
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* Some cores claim the FDC is routable through the GIC, but it doesn't
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* actually seem to be connected for those Malta bitstreams.
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*/
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switch (current_cpu_type()) {
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case CPU_INTERAPTIV:
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case CPU_PROAPTIV:
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return -1;
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};
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2015-01-29 19:14:10 +08:00
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if (cpu_has_veic)
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2015-04-17 17:44:15 +08:00
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return -1;
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2015-01-29 19:14:10 +08:00
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else if (gic_present)
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2015-04-17 17:44:15 +08:00
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return gic_get_c0_fdc_int();
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2015-01-29 19:14:10 +08:00
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else if (cp0_fdc_irq >= 0)
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2015-04-17 17:44:15 +08:00
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return MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
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2015-01-29 19:14:10 +08:00
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else
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2015-04-17 17:44:15 +08:00
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return -1;
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2015-01-29 19:14:10 +08:00
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}
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2014-09-19 05:47:12 +08:00
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int get_c0_perfcount_int(void)
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2007-05-25 05:24:20 +08:00
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{
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2005-07-14 23:57:16 +08:00
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if (cpu_has_veic) {
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2007-10-12 06:46:15 +08:00
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set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch);
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2008-04-29 00:14:26 +08:00
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mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
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2014-09-19 05:47:27 +08:00
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} else if (gic_present) {
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mips_cpu_perf_irq = gic_get_c0_perfcount_int();
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2014-09-19 05:47:12 +08:00
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} else if (cp0_perfcount_irq >= 0) {
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2008-04-29 00:14:26 +08:00
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mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
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2014-09-19 05:47:12 +08:00
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} else {
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mips_cpu_perf_irq = -1;
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2005-07-14 23:57:16 +08:00
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}
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2014-09-19 05:47:12 +08:00
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return mips_cpu_perf_irq;
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2007-05-25 05:24:20 +08:00
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}
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2015-07-24 00:59:52 +08:00
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EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
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2005-07-14 23:57:16 +08:00
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MIPS: Delete __cpuinit/__CPUINIT usage from MIPS code
commit 3747069b25e419f6b51395f48127e9812abc3596 upstream.
The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.
After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.
Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
and are flagged as __cpuinit -- so if we remove the __cpuinit from
the arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
related content into no-ops as early as possible, since that will get
rid of these warnings. In any case, they are temporary and harmless.
Here, we remove all the MIPS __cpuinit from C code and __CPUINIT
from asm files. MIPS is interesting in this respect, because there
are also uasm users hiding behind their own renamed versions of the
__cpuinit macros.
[1] https://lkml.org/lkml/2013/5/20/589
[ralf@linux-mips.org: Folded in Paul's followup fix.]
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5494/
Patchwork: https://patchwork.linux-mips.org/patch/5495/
Patchwork: https://patchwork.linux-mips.org/patch/5509/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-06-18 21:38:59 +08:00
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unsigned int get_c0_compare_int(void)
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2007-05-25 05:24:20 +08:00
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{
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if (cpu_has_veic) {
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2007-10-12 06:46:15 +08:00
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set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
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2007-05-25 05:24:20 +08:00
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mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
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2014-09-19 05:47:27 +08:00
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} else if (gic_present) {
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mips_cpu_timer_irq = gic_get_c0_compare_int();
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} else {
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2007-06-21 05:27:10 +08:00
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mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
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2007-05-25 05:24:20 +08:00
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}
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2005-07-14 23:57:16 +08:00
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2007-10-29 22:23:43 +08:00
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return mips_cpu_timer_irq;
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}
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2013-12-03 00:48:36 +08:00
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static void __init init_rtc(void)
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{
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MIPS: Malta: Don't reinitialise RTC
On Malta, since commit a87ea88d8f6c ("MIPS: Malta: initialise the RTC at
boot"), the RTC is reinitialised and forced into binary coded decimal
(BCD) mode during init, even if the bootloader has already initialised
it, and may even have already put it into binary mode (as YAMON does).
This corrupts the current time, can result in the RTC seconds being an
invalid BCD (e.g. 0x1a..0x1f) for up to 6 seconds, as well as confusing
YAMON for a while after reset, enough for it to report timeouts when
attempting to load from TFTP (it actually uses the RTC in that code).
Therefore only initialise the RTC to the extent that is necessary so
that Linux avoids interfering with the bootloader setup, while also
allowing it to estimate the CPU frequency without hanging, without a
bootloader necessarily having done anything with the RTC (for example
when the kernel is loaded via EJTAG).
The divider control is configured for a 32KHZ reference clock if
necessary, and the SET bit of the RTC_CONTROL register is cleared if
necessary without changing any other bits (this bit will be set when
coming out of reset if the battery has been disconnected).
Fixes: a87ea88d8f6c ("MIPS: Malta: initialise the RTC at boot")
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: <stable@vger.kernel.org> # 3.14+
Patchwork: https://patchwork.linux-mips.org/patch/10739/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-07-17 22:54:41 +08:00
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unsigned char freq, ctrl;
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2013-12-03 00:48:36 +08:00
|
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MIPS: Malta: Don't reinitialise RTC
On Malta, since commit a87ea88d8f6c ("MIPS: Malta: initialise the RTC at
boot"), the RTC is reinitialised and forced into binary coded decimal
(BCD) mode during init, even if the bootloader has already initialised
it, and may even have already put it into binary mode (as YAMON does).
This corrupts the current time, can result in the RTC seconds being an
invalid BCD (e.g. 0x1a..0x1f) for up to 6 seconds, as well as confusing
YAMON for a while after reset, enough for it to report timeouts when
attempting to load from TFTP (it actually uses the RTC in that code).
Therefore only initialise the RTC to the extent that is necessary so
that Linux avoids interfering with the bootloader setup, while also
allowing it to estimate the CPU frequency without hanging, without a
bootloader necessarily having done anything with the RTC (for example
when the kernel is loaded via EJTAG).
The divider control is configured for a 32KHZ reference clock if
necessary, and the SET bit of the RTC_CONTROL register is cleared if
necessary without changing any other bits (this bit will be set when
coming out of reset if the battery has been disconnected).
Fixes: a87ea88d8f6c ("MIPS: Malta: initialise the RTC at boot")
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: <stable@vger.kernel.org> # 3.14+
Patchwork: https://patchwork.linux-mips.org/patch/10739/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-07-17 22:54:41 +08:00
|
|
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/* Set 32KHz time base if not already set */
|
|
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freq = CMOS_READ(RTC_FREQ_SELECT);
|
|
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|
if ((freq & RTC_DIV_CTL) != RTC_REF_CLCK_32KHZ)
|
|
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|
CMOS_WRITE(RTC_REF_CLCK_32KHZ, RTC_FREQ_SELECT);
|
2013-12-03 00:48:36 +08:00
|
|
|
|
MIPS: Malta: Don't reinitialise RTC
On Malta, since commit a87ea88d8f6c ("MIPS: Malta: initialise the RTC at
boot"), the RTC is reinitialised and forced into binary coded decimal
(BCD) mode during init, even if the bootloader has already initialised
it, and may even have already put it into binary mode (as YAMON does).
This corrupts the current time, can result in the RTC seconds being an
invalid BCD (e.g. 0x1a..0x1f) for up to 6 seconds, as well as confusing
YAMON for a while after reset, enough for it to report timeouts when
attempting to load from TFTP (it actually uses the RTC in that code).
Therefore only initialise the RTC to the extent that is necessary so
that Linux avoids interfering with the bootloader setup, while also
allowing it to estimate the CPU frequency without hanging, without a
bootloader necessarily having done anything with the RTC (for example
when the kernel is loaded via EJTAG).
The divider control is configured for a 32KHZ reference clock if
necessary, and the SET bit of the RTC_CONTROL register is cleared if
necessary without changing any other bits (this bit will be set when
coming out of reset if the battery has been disconnected).
Fixes: a87ea88d8f6c ("MIPS: Malta: initialise the RTC at boot")
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: <stable@vger.kernel.org> # 3.14+
Patchwork: https://patchwork.linux-mips.org/patch/10739/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-07-17 22:54:41 +08:00
|
|
|
/* Ensure SET bit is clear so RTC can run */
|
|
|
|
ctrl = CMOS_READ(RTC_CONTROL);
|
|
|
|
if (ctrl & RTC_SET)
|
|
|
|
CMOS_WRITE(ctrl & ~RTC_SET, RTC_CONTROL);
|
2013-12-03 00:48:36 +08:00
|
|
|
}
|
|
|
|
|
2017-04-19 20:26:45 +08:00
|
|
|
#ifdef CONFIG_CLKSRC_MIPS_GIC
|
|
|
|
static u32 gic_frequency_dt;
|
|
|
|
|
|
|
|
static struct property gic_frequency_prop = {
|
|
|
|
.name = "clock-frequency",
|
|
|
|
.length = sizeof(u32),
|
|
|
|
.value = &gic_frequency_dt,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void update_gic_frequency_dt(void)
|
|
|
|
{
|
|
|
|
struct device_node *node;
|
|
|
|
|
|
|
|
gic_frequency_dt = cpu_to_be32(gic_frequency);
|
|
|
|
|
|
|
|
node = of_find_compatible_node(NULL, NULL, "mti,gic-timer");
|
|
|
|
if (!node) {
|
|
|
|
pr_err("mti,gic-timer device node not found\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (of_update_property(node, &gic_frequency_prop) < 0)
|
|
|
|
pr_err("error updating gic frequency property\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
2007-10-29 22:23:43 +08:00
|
|
|
void __init plat_time_init(void)
|
|
|
|
{
|
2013-09-17 23:58:10 +08:00
|
|
|
unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK);
|
2012-12-07 11:51:04 +08:00
|
|
|
unsigned int freq;
|
2007-10-29 22:23:43 +08:00
|
|
|
|
2013-12-03 00:48:36 +08:00
|
|
|
init_rtc();
|
2012-12-07 11:51:04 +08:00
|
|
|
estimate_frequencies();
|
2007-10-29 22:23:43 +08:00
|
|
|
|
2012-12-07 11:51:04 +08:00
|
|
|
freq = mips_hpt_frequency;
|
|
|
|
if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
|
|
|
|
(prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
|
|
|
|
freq *= 2;
|
|
|
|
freq = freqround(freq, 5000);
|
2013-04-11 05:28:36 +08:00
|
|
|
printk("CPU frequency %d.%02d MHz\n", freq/1000000,
|
2012-12-07 11:51:04 +08:00
|
|
|
(freq%1000000)*100/1000000);
|
|
|
|
|
2013-04-11 05:28:36 +08:00
|
|
|
mips_scroll_message();
|
2007-10-29 22:23:43 +08:00
|
|
|
|
2012-12-07 11:51:04 +08:00
|
|
|
#ifdef CONFIG_I8253
|
|
|
|
/* Only Malta has a PIT. */
|
2007-10-29 22:23:43 +08:00
|
|
|
setup_pit_timer();
|
2005-08-18 01:44:08 +08:00
|
|
|
#endif
|
2007-05-25 05:24:20 +08:00
|
|
|
|
2014-09-19 05:47:19 +08:00
|
|
|
#ifdef CONFIG_MIPS_GIC
|
2013-04-11 05:28:36 +08:00
|
|
|
if (gic_present) {
|
|
|
|
freq = freqround(gic_frequency, 5000);
|
|
|
|
printk("GIC frequency %d.%02d MHz\n", freq/1000000,
|
|
|
|
(freq%1000000)*100/1000000);
|
2014-10-21 03:03:58 +08:00
|
|
|
#ifdef CONFIG_CLKSRC_MIPS_GIC
|
2017-04-19 20:26:45 +08:00
|
|
|
update_gic_frequency_dt();
|
2017-05-26 23:40:46 +08:00
|
|
|
timer_probe();
|
2013-04-11 05:28:36 +08:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
#endif
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|