2012-08-30 16:51:04 +08:00
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/*
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* Copyright 2012 DENX Software Engineering GmbH
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* Heiko Schocher <hs@denx.de>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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2013-06-14 17:45:53 +08:00
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#include "skeleton.dtsi"
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2013-11-22 02:15:30 +08:00
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#include <dt-bindings/interrupt-controller/irq.h>
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2012-08-30 16:51:04 +08:00
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/ {
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arm {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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intc: interrupt-controller {
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compatible = "ti,cp-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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ti,intc-size = <100>;
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reg = <0xfffee000 0x2000>;
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};
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};
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soc {
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compatible = "simple-bus";
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model = "da850";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x01c00000 0x400000>;
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2013-01-25 19:18:44 +08:00
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interrupt-parent = <&intc>;
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2012-08-30 16:51:04 +08:00
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2013-01-16 17:07:39 +08:00
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pmx_core: pinmux@1c14120 {
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compatible = "pinctrl-single";
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reg = <0x14120 0x50>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-single,bit-per-mux;
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pinctrl-single,register-width = <32>;
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2013-05-21 22:08:02 +08:00
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pinctrl-single,function-mask = <0xf>;
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2013-01-16 17:07:39 +08:00
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status = "disabled";
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2013-01-16 17:07:41 +08:00
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nand_cs3_pins: pinmux_nand_pins {
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pinctrl-single,bits = <
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/* EMA_OE, EMA_WE */
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0x1c 0x00110000 0x00ff0000
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/* EMA_CS[4],EMA_CS[3]*/
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0x1c 0x00000110 0x00000ff0
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/*
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* EMA_D[0], EMA_D[1], EMA_D[2],
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* EMA_D[3], EMA_D[4], EMA_D[5],
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* EMA_D[6], EMA_D[7]
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*/
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0x24 0x11111111 0xffffffff
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/* EMA_A[1], EMA_A[2] */
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0x30 0x01100000 0x0ff00000
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>;
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};
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2013-02-06 17:36:22 +08:00
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i2c0_pins: pinmux_i2c0_pins {
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pinctrl-single,bits = <
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/* I2C0_SDA,I2C0_SCL */
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0x10 0x00002200 0x0000ff00
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>;
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};
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2013-03-28 21:12:01 +08:00
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mmc0_pins: pinmux_mmc_pins {
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pinctrl-single,bits = <
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/* MMCSD0_DAT[3] MMCSD0_DAT[2]
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* MMCSD0_DAT[1] MMCSD0_DAT[0]
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* MMCSD0_CMD MMCSD0_CLK
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*/
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0x28 0x00222222 0x00ffffff
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>;
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};
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2013-04-10 20:12:41 +08:00
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ehrpwm0a_pins: pinmux_ehrpwm0a_pins {
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pinctrl-single,bits = <
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/* EPWM0A */
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0xc 0x00000002 0x0000000f
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>;
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};
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ehrpwm0b_pins: pinmux_ehrpwm0b_pins {
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pinctrl-single,bits = <
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/* EPWM0B */
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0xc 0x00000020 0x000000f0
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>;
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};
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ehrpwm1a_pins: pinmux_ehrpwm1a_pins {
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pinctrl-single,bits = <
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/* EPWM1A */
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0x14 0x00000002 0x0000000f
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>;
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};
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ehrpwm1b_pins: pinmux_ehrpwm1b_pins {
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pinctrl-single,bits = <
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/* EPWM1B */
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0x14 0x00000020 0x000000f0
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>;
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};
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ecap0_pins: pinmux_ecap0_pins {
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pinctrl-single,bits = <
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/* ECAP0_APWM0 */
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0x8 0x20000000 0xf0000000
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>;
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};
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ecap1_pins: pinmux_ecap1_pins {
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pinctrl-single,bits = <
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/* ECAP1_APWM1 */
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0x4 0x40000000 0xf0000000
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>;
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};
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ecap2_pins: pinmux_ecap2_pins {
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pinctrl-single,bits = <
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/* ECAP2_APWM2 */
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0x4 0x00000004 0x0000000f
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>;
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};
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2013-04-03 22:09:08 +08:00
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spi1_pins: pinmux_spi_pins {
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pinctrl-single,bits = <
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/* SIMO, SOMI, CLK */
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0x14 0x00110100 0x00ff0f00
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>;
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};
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spi1_cs0_pin: pinmux_spi1_cs0 {
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pinctrl-single,bits = <
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/* CS0 */
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0x14 0x00000010 0x000000f0
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>;
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};
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2013-08-15 14:01:34 +08:00
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mdio_pins: pinmux_mdio_pins {
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pinctrl-single,bits = <
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/* MDIO_CLK, MDIO_D */
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0x10 0x00000088 0x000000ff
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>;
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};
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2013-08-17 01:07:09 +08:00
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mii_pins: pinmux_mii_pins {
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pinctrl-single,bits = <
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/*
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* MII_TXEN, MII_TXCLK, MII_COL
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* MII_TXD_3, MII_TXD_2, MII_TXD_1
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* MII_TXD_0
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*/
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0x8 0x88888880 0xfffffff0
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/*
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* MII_RXER, MII_CRS, MII_RXCLK
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* MII_RXDV, MII_RXD_3, MII_RXD_2
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* MII_RXD_1, MII_RXD_0
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*/
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0xc 0x88888888 0xffffffff
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>;
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};
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2013-08-15 14:01:34 +08:00
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2013-01-16 17:07:39 +08:00
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};
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2014-08-01 14:13:26 +08:00
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edma0: edma@01c00000 {
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2015-12-17 21:27:48 +08:00
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compatible = "ti,edma3-tpcc";
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2015-12-17 21:27:47 +08:00
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/* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */
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reg = <0x0 0x8000>;
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2015-12-17 21:27:48 +08:00
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reg-names = "edma3_cc";
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interrupts = <11 12>;
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interrupt-names = "edma3_ccint", "edma3_ccerrint";
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#dma-cells = <2>;
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ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>;
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};
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edma0_tptc0: tptc@01c08000 {
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compatible = "ti,edma3-tptc";
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reg = <0x8000 0x400>;
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interrupts = <13>;
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interrupt-names = "edm3_tcerrint";
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};
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edma0_tptc1: tptc@01c08400 {
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compatible = "ti,edma3-tptc";
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reg = <0x8400 0x400>;
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interrupts = <32>;
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interrupt-names = "edm3_tcerrint";
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2014-08-01 14:13:26 +08:00
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};
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2015-12-17 21:27:49 +08:00
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edma1: edma@01e30000 {
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compatible = "ti,edma3-tpcc";
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/* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */
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reg = <0x230000 0x8000>;
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reg-names = "edma3_cc";
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interrupts = <93 94>;
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interrupt-names = "edma3_ccint", "edma3_ccerrint";
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#dma-cells = <2>;
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ti,tptcs = <&edma1_tptc0 7>;
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};
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edma1_tptc0: tptc@01e38000 {
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compatible = "ti,edma3-tptc";
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reg = <0x238000 0x400>;
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interrupts = <95>;
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interrupt-names = "edm3_tcerrint";
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};
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2012-08-30 16:51:04 +08:00
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serial0: serial@1c42000 {
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compatible = "ns16550a";
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reg = <0x42000 0x100>;
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reg-shift = <2>;
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interrupts = <25>;
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status = "disabled";
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};
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serial1: serial@1d0c000 {
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compatible = "ns16550a";
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reg = <0x10c000 0x100>;
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reg-shift = <2>;
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interrupts = <53>;
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status = "disabled";
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};
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serial2: serial@1d0d000 {
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compatible = "ns16550a";
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reg = <0x10d000 0x100>;
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reg-shift = <2>;
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interrupts = <61>;
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status = "disabled";
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};
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2013-01-28 15:47:48 +08:00
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rtc0: rtc@1c23000 {
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compatible = "ti,da830-rtc";
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reg = <0x23000 0x1000>;
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interrupts = <19
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19>;
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status = "disabled";
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};
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2013-02-06 17:36:22 +08:00
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i2c0: i2c@1c22000 {
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compatible = "ti,davinci-i2c";
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reg = <0x22000 0x1000>;
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interrupts = <15>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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2013-02-06 12:00:03 +08:00
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wdt: wdt@1c21000 {
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compatible = "ti,davinci-wdt";
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reg = <0x21000 0x1000>;
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status = "disabled";
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};
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2013-03-28 21:12:01 +08:00
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mmc0: mmc@1c40000 {
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compatible = "ti,da830-mmc";
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reg = <0x40000 0x1000>;
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interrupts = <16>;
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2015-12-17 21:27:50 +08:00
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dmas = <&edma0 16 0>, <&edma0 17 0>;
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dma-names = "rx", "tx";
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2013-03-28 21:12:01 +08:00
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status = "disabled";
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};
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2015-12-17 21:27:51 +08:00
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mmc1: mmc@1e1b000 {
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compatible = "ti,da830-mmc";
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reg = <0x21b000 0x1000>;
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interrupts = <72>;
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dmas = <&edma1 28 0>, <&edma1 29 0>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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2013-04-10 20:12:41 +08:00
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ehrpwm0: ehrpwm@01f00000 {
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compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
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#pwm-cells = <3>;
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reg = <0x300000 0x2000>;
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status = "disabled";
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};
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ehrpwm1: ehrpwm@01f02000 {
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compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
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#pwm-cells = <3>;
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reg = <0x302000 0x2000>;
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status = "disabled";
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};
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ecap0: ecap@01f06000 {
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compatible = "ti,da850-ecap", "ti,am33xx-ecap";
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#pwm-cells = <3>;
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reg = <0x306000 0x80>;
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status = "disabled";
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};
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ecap1: ecap@01f07000 {
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compatible = "ti,da850-ecap", "ti,am33xx-ecap";
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#pwm-cells = <3>;
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reg = <0x307000 0x80>;
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status = "disabled";
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};
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ecap2: ecap@01f08000 {
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compatible = "ti,da850-ecap", "ti,am33xx-ecap";
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#pwm-cells = <3>;
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reg = <0x308000 0x80>;
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status = "disabled";
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};
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2013-04-03 22:09:08 +08:00
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spi1: spi@1f0e000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "ti,da830-spi";
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reg = <0x30e000 0x1000>;
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num-cs = <4>;
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ti,davinci-spi-intr-line = <1>;
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interrupts = <56>;
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2015-12-17 21:27:52 +08:00
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dmas = <&edma0 18 0>, <&edma0 19 0>;
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dma-names = "rx", "tx";
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2013-04-03 22:09:08 +08:00
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status = "disabled";
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};
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2013-08-15 14:01:34 +08:00
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mdio: mdio@1e24000 {
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compatible = "ti,davinci_mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x224000 0x1000>;
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};
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2013-08-17 01:07:09 +08:00
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eth0: ethernet@1e20000 {
|
|
|
|
|
compatible = "ti,davinci-dm6467-emac";
|
|
|
|
|
reg = <0x220000 0x4000>;
|
|
|
|
|
ti,davinci-ctrl-reg-offset = <0x3000>;
|
|
|
|
|
ti,davinci-ctrl-mod-reg-offset = <0x2000>;
|
|
|
|
|
ti,davinci-ctrl-ram-offset = <0>;
|
|
|
|
|
ti,davinci-ctrl-ram-size = <0x2000>;
|
|
|
|
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
|
|
|
|
interrupts = <33
|
|
|
|
|
34
|
|
|
|
|
35
|
|
|
|
|
36
|
|
|
|
|
>;
|
|
|
|
|
};
|
2013-11-22 02:15:30 +08:00
|
|
|
gpio: gpio@1e26000 {
|
|
|
|
|
compatible = "ti,dm6441-gpio";
|
|
|
|
|
gpio-controller;
|
2016-04-05 17:31:37 +08:00
|
|
|
#gpio-cells = <2>;
|
2013-11-22 02:15:30 +08:00
|
|
|
reg = <0x226000 0x1000>;
|
|
|
|
|
interrupts = <42 IRQ_TYPE_EDGE_BOTH
|
|
|
|
|
43 IRQ_TYPE_EDGE_BOTH 44 IRQ_TYPE_EDGE_BOTH
|
|
|
|
|
45 IRQ_TYPE_EDGE_BOTH 46 IRQ_TYPE_EDGE_BOTH
|
|
|
|
|
47 IRQ_TYPE_EDGE_BOTH 48 IRQ_TYPE_EDGE_BOTH
|
|
|
|
|
49 IRQ_TYPE_EDGE_BOTH 50 IRQ_TYPE_EDGE_BOTH>;
|
|
|
|
|
ti,ngpio = <144>;
|
|
|
|
|
ti,davinci-gpio-unbanked = <0>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2014-08-01 14:13:27 +08:00
|
|
|
|
|
|
|
|
mcasp0: mcasp@01d00000 {
|
|
|
|
|
compatible = "ti,da830-mcasp-audio";
|
|
|
|
|
reg = <0x100000 0x2000>,
|
|
|
|
|
<0x102000 0x400000>;
|
|
|
|
|
reg-names = "mpu", "dat";
|
|
|
|
|
interrupts = <54>;
|
|
|
|
|
interrupt-names = "common";
|
|
|
|
|
status = "disabled";
|
2015-12-17 21:27:48 +08:00
|
|
|
dmas = <&edma0 1 1>,
|
|
|
|
|
<&edma0 0 1>;
|
2014-08-01 14:13:27 +08:00
|
|
|
dma-names = "tx", "rx";
|
|
|
|
|
};
|
2012-08-30 16:51:04 +08:00
|
|
|
};
|
2013-01-16 17:07:41 +08:00
|
|
|
nand_cs3@62000000 {
|
|
|
|
|
compatible = "ti,davinci-nand";
|
|
|
|
|
reg = <0x62000000 0x807ff
|
|
|
|
|
0x68000000 0x8000>;
|
|
|
|
|
ti,davinci-chipselect = <1>;
|
|
|
|
|
ti,davinci-mask-ale = <0>;
|
|
|
|
|
ti,davinci-mask-cle = <0>;
|
|
|
|
|
ti,davinci-mask-chipsel = <0>;
|
|
|
|
|
ti,davinci-ecc-mode = "hw";
|
|
|
|
|
ti,davinci-ecc-bits = <4>;
|
|
|
|
|
ti,davinci-nand-use-bbt;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2012-08-30 16:51:04 +08:00
|
|
|
};
|
