2010-08-24 11:24:12 +08:00
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/*
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* Linux network driver for Brocade Converged Network Adapter.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License (GPL) Version 2 as
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* published by the Free Software Foundation
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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/*
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* Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
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* All rights reserved
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* www.brocade.com
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*/
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#ifndef __BFA_IOC_H__
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#define __BFA_IOC_H__
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2011-07-22 16:07:49 +08:00
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#include "bfa_cs.h"
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2010-08-24 11:24:12 +08:00
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#include "bfi.h"
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#include "cna.h"
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#define BFA_IOC_TOV 3000 /* msecs */
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#define BFA_IOC_HWSEM_TOV 500 /* msecs */
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#define BFA_IOC_HB_TOV 500 /* msecs */
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bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
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#define BFA_IOC_POLL_TOV 200 /* msecs */
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2010-08-24 11:24:12 +08:00
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/**
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* PCI device information required by IOC
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*/
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struct bfa_pcidev {
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int pci_slot;
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u8 pci_func;
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u16 device_id;
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2011-09-27 18:39:08 +08:00
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u16 ssid;
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2010-08-24 11:24:12 +08:00
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void __iomem *pci_bar_kva;
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};
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/**
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* Structure used to remember the DMA-able memory block's KVA and Physical
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* Address
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*/
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struct bfa_dma {
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void *kva; /* ! Kernel virtual address */
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u64 pa; /* ! Physical address */
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};
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#define BFA_DMA_ALIGN_SZ 256
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/**
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* smem size for Crossbow and Catapult
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*/
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#define BFI_SMEM_CB_SIZE 0x200000U /* ! 2MB for crossbow */
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#define BFI_SMEM_CT_SIZE 0x280000U /* ! 2.5MB for catapult */
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/**
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* @brief BFA dma address assignment macro. (big endian format)
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*/
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#define bfa_dma_be_addr_set(dma_addr, pa) \
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__bfa_dma_be_addr_set(&dma_addr, (u64)pa)
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static inline void
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__bfa_dma_be_addr_set(union bfi_addr_u *dma_addr, u64 pa)
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{
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dma_addr->a32.addr_lo = (u32) htonl(pa);
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dma_addr->a32.addr_hi = (u32) htonl(upper_32_bits(pa));
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}
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struct bfa_ioc_regs {
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void __iomem *hfn_mbox_cmd;
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void __iomem *hfn_mbox;
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void __iomem *lpu_mbox_cmd;
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void __iomem *lpu_mbox;
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2011-09-27 18:39:05 +08:00
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void __iomem *lpu_read_stat;
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2010-08-24 11:24:12 +08:00
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void __iomem *pss_ctl_reg;
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void __iomem *pss_err_status_reg;
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void __iomem *app_pll_fast_ctl_reg;
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void __iomem *app_pll_slow_ctl_reg;
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void __iomem *ioc_sem_reg;
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void __iomem *ioc_usage_sem_reg;
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void __iomem *ioc_init_sem_reg;
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void __iomem *ioc_usage_reg;
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void __iomem *host_page_num_fn;
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void __iomem *heartbeat;
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void __iomem *ioc_fwstate;
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2010-12-24 05:45:09 +08:00
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void __iomem *alt_ioc_fwstate;
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2010-08-24 11:24:12 +08:00
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void __iomem *ll_halt;
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2010-12-24 05:45:09 +08:00
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void __iomem *alt_ll_halt;
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2010-08-24 11:24:12 +08:00
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void __iomem *err_set;
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2010-12-24 05:45:09 +08:00
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void __iomem *ioc_fail_sync;
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2010-08-24 11:24:12 +08:00
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void __iomem *shirq_isr_next;
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void __iomem *shirq_msk_next;
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void __iomem *smem_page_start;
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u32 smem_pg0;
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};
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/**
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* IOC Mailbox structures
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*/
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2011-07-22 16:07:42 +08:00
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typedef void (*bfa_mbox_cmd_cbfn_t)(void *cbarg);
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2010-08-24 11:24:12 +08:00
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struct bfa_mbox_cmd {
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struct list_head qe;
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2011-07-22 16:07:42 +08:00
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bfa_mbox_cmd_cbfn_t cbfn;
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void *cbarg;
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u32 msg[BFI_IOC_MSGSZ];
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2010-08-24 11:24:12 +08:00
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};
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/**
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* IOC mailbox module
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*/
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typedef void (*bfa_ioc_mbox_mcfunc_t)(void *cbarg, struct bfi_mbmsg *m);
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struct bfa_ioc_mbox_mod {
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struct list_head cmd_q; /*!< pending mbox queue */
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int nmclass; /*!< number of handlers */
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struct {
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bfa_ioc_mbox_mcfunc_t cbfn; /*!< message handlers */
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void *cbarg;
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} mbhdlr[BFI_MC_MAX];
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};
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/**
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* IOC callback function interfaces
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*/
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typedef void (*bfa_ioc_enable_cbfn_t)(void *bfa, enum bfa_status status);
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typedef void (*bfa_ioc_disable_cbfn_t)(void *bfa);
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typedef void (*bfa_ioc_hbfail_cbfn_t)(void *bfa);
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typedef void (*bfa_ioc_reset_cbfn_t)(void *bfa);
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struct bfa_ioc_cbfn {
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bfa_ioc_enable_cbfn_t enable_cbfn;
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bfa_ioc_disable_cbfn_t disable_cbfn;
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bfa_ioc_hbfail_cbfn_t hbfail_cbfn;
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bfa_ioc_reset_cbfn_t reset_cbfn;
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};
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2011-07-22 16:07:42 +08:00
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/**
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* IOC event notification mechanism.
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*/
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enum bfa_ioc_event {
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BFA_IOC_E_ENABLED = 1,
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BFA_IOC_E_DISABLED = 2,
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BFA_IOC_E_FAILED = 3,
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};
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typedef void (*bfa_ioc_notify_cbfn_t)(void *, enum bfa_ioc_event);
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struct bfa_ioc_notify {
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struct list_head qe;
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bfa_ioc_notify_cbfn_t cbfn;
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void *cbarg;
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};
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2010-08-24 11:24:12 +08:00
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/**
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* Heartbeat failure notification queue element.
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*/
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struct bfa_ioc_hbfail_notify {
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struct list_head qe;
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bfa_ioc_hbfail_cbfn_t cbfn;
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void *cbarg;
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};
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/**
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* Initialize a heartbeat failure notification structure
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*/
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2011-07-22 16:07:42 +08:00
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#define bfa_ioc_notify_init(__notify, __cbfn, __cbarg) do { \
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2010-08-24 11:24:12 +08:00
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(__notify)->cbfn = (__cbfn); \
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(__notify)->cbarg = (__cbarg); \
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} while (0)
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2010-12-24 05:45:09 +08:00
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struct bfa_iocpf {
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bfa_fsm_t fsm;
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struct bfa_ioc *ioc;
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bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
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bool fw_mismatch_notified;
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2010-12-24 05:45:09 +08:00
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bool auto_recover;
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bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
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u32 poll_time;
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2010-12-24 05:45:09 +08:00
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};
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2010-08-24 11:24:12 +08:00
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struct bfa_ioc {
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bfa_fsm_t fsm;
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2011-07-22 16:07:41 +08:00
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struct bfa *bfa;
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struct bfa_pcidev pcidev;
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struct timer_list ioc_timer;
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struct timer_list iocpf_timer;
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struct timer_list sem_timer;
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2010-08-24 11:24:12 +08:00
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struct timer_list hb_timer;
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u32 hb_count;
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2011-07-22 16:07:42 +08:00
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struct list_head notify_q;
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2010-08-24 11:24:12 +08:00
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void *dbg_fwsave;
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int dbg_fwsave_len;
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bool dbg_fwsave_once;
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
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|
|
enum bfi_pcifn_class clscode;
|
2011-07-22 16:07:41 +08:00
|
|
|
struct bfa_ioc_regs ioc_regs;
|
2010-08-24 11:24:12 +08:00
|
|
|
struct bfa_ioc_drv_stats stats;
|
|
|
|
|
bool fcmode;
|
|
|
|
|
bool pllinit;
|
2011-07-22 16:07:41 +08:00
|
|
|
bool stats_busy; /*!< outstanding stats */
|
2010-08-24 11:24:12 +08:00
|
|
|
u8 port_id;
|
|
|
|
|
|
|
|
|
|
struct bfa_dma attr_dma;
|
|
|
|
|
struct bfi_ioc_attr *attr;
|
|
|
|
|
struct bfa_ioc_cbfn *cbfn;
|
|
|
|
|
struct bfa_ioc_mbox_mod mbox_mod;
|
2011-09-16 19:09:51 +08:00
|
|
|
const struct bfa_ioc_hwif *ioc_hwif;
|
2010-12-24 05:45:09 +08:00
|
|
|
struct bfa_iocpf iocpf;
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
|
|
|
enum bfi_asic_gen asic_gen;
|
|
|
|
|
enum bfi_asic_mode asic_mode;
|
|
|
|
|
enum bfi_port_mode port0_mode;
|
|
|
|
|
enum bfi_port_mode port1_mode;
|
|
|
|
|
enum bfa_mode port_mode;
|
|
|
|
|
u8 ad_cap_bm; /*!< adapter cap bit mask */
|
|
|
|
|
u8 port_mode_cfg; /*!< config port mode */
|
2010-08-24 11:24:12 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct bfa_ioc_hwif {
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
|
|
|
enum bfa_status (*ioc_pll_init) (void __iomem *rb,
|
|
|
|
|
enum bfi_asic_mode m);
|
2010-08-24 11:24:12 +08:00
|
|
|
bool (*ioc_firmware_lock) (struct bfa_ioc *ioc);
|
|
|
|
|
void (*ioc_firmware_unlock) (struct bfa_ioc *ioc);
|
|
|
|
|
void (*ioc_reg_init) (struct bfa_ioc *ioc);
|
|
|
|
|
void (*ioc_map_port) (struct bfa_ioc *ioc);
|
|
|
|
|
void (*ioc_isr_mode_set) (struct bfa_ioc *ioc,
|
|
|
|
|
bool msix);
|
2010-12-24 05:45:09 +08:00
|
|
|
void (*ioc_notify_fail) (struct bfa_ioc *ioc);
|
2010-08-24 11:24:12 +08:00
|
|
|
void (*ioc_ownership_reset) (struct bfa_ioc *ioc);
|
2011-04-14 16:05:18 +08:00
|
|
|
bool (*ioc_sync_start) (struct bfa_ioc *ioc);
|
2010-12-24 05:45:09 +08:00
|
|
|
void (*ioc_sync_join) (struct bfa_ioc *ioc);
|
|
|
|
|
void (*ioc_sync_leave) (struct bfa_ioc *ioc);
|
|
|
|
|
void (*ioc_sync_ack) (struct bfa_ioc *ioc);
|
|
|
|
|
bool (*ioc_sync_complete) (struct bfa_ioc *ioc);
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
|
|
|
bool (*ioc_lpu_read_stat) (struct bfa_ioc *ioc);
|
2010-08-24 11:24:12 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
#define bfa_ioc_pcifn(__ioc) ((__ioc)->pcidev.pci_func)
|
|
|
|
|
#define bfa_ioc_devid(__ioc) ((__ioc)->pcidev.device_id)
|
|
|
|
|
#define bfa_ioc_bar0(__ioc) ((__ioc)->pcidev.pci_bar_kva)
|
|
|
|
|
#define bfa_ioc_portid(__ioc) ((__ioc)->port_id)
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
|
|
|
#define bfa_ioc_asic_gen(__ioc) ((__ioc)->asic_gen)
|
2010-08-24 11:24:12 +08:00
|
|
|
#define bfa_ioc_fetch_stats(__ioc, __stats) \
|
|
|
|
|
(((__stats)->drv_stats) = (__ioc)->stats)
|
|
|
|
|
#define bfa_ioc_clr_stats(__ioc) \
|
|
|
|
|
memset(&(__ioc)->stats, 0, sizeof((__ioc)->stats))
|
|
|
|
|
#define bfa_ioc_maxfrsize(__ioc) ((__ioc)->attr->maxfrsize)
|
|
|
|
|
#define bfa_ioc_rx_bbcredit(__ioc) ((__ioc)->attr->rx_bbcredit)
|
|
|
|
|
#define bfa_ioc_speed_sup(__ioc) \
|
|
|
|
|
BFI_ADAPTER_GETP(SPEED, (__ioc)->attr->adapter_prop)
|
|
|
|
|
#define bfa_ioc_get_nports(__ioc) \
|
|
|
|
|
BFI_ADAPTER_GETP(NPORTS, (__ioc)->attr->adapter_prop)
|
|
|
|
|
|
|
|
|
|
#define bfa_ioc_stats(_ioc, _stats) ((_ioc)->stats._stats++)
|
2011-07-22 16:07:48 +08:00
|
|
|
#define bfa_ioc_stats_hb_count(_ioc, _hb_count) \
|
|
|
|
|
((_ioc)->stats.hb_count = (_hb_count))
|
2010-08-24 11:24:12 +08:00
|
|
|
#define BFA_IOC_FWIMG_MINSZ (16 * 1024)
|
|
|
|
|
#define BFA_IOC_FW_SMEM_SIZE(__ioc) \
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
|
|
|
((bfa_ioc_asic_gen(__ioc) == BFI_ASIC_GEN_CB) \
|
|
|
|
|
? BFI_SMEM_CB_SIZE : BFI_SMEM_CT_SIZE)
|
2010-08-24 11:24:12 +08:00
|
|
|
#define BFA_IOC_FLASH_CHUNK_NO(off) (off / BFI_FLASH_CHUNK_SZ_WORDS)
|
|
|
|
|
#define BFA_IOC_FLASH_OFFSET_IN_CHUNK(off) (off % BFI_FLASH_CHUNK_SZ_WORDS)
|
|
|
|
|
#define BFA_IOC_FLASH_CHUNK_ADDR(chunkno) (chunkno * BFI_FLASH_CHUNK_SZ_WORDS)
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* IOC mailbox interface
|
|
|
|
|
*/
|
2011-08-09 00:21:35 +08:00
|
|
|
bool bfa_nw_ioc_mbox_queue(struct bfa_ioc *ioc,
|
|
|
|
|
struct bfa_mbox_cmd *cmd,
|
|
|
|
|
bfa_mbox_cmd_cbfn_t cbfn, void *cbarg);
|
2010-08-26 14:00:27 +08:00
|
|
|
void bfa_nw_ioc_mbox_isr(struct bfa_ioc *ioc);
|
|
|
|
|
void bfa_nw_ioc_mbox_regisr(struct bfa_ioc *ioc, enum bfi_mclass mc,
|
2010-08-24 11:24:12 +08:00
|
|
|
bfa_ioc_mbox_mcfunc_t cbfn, void *cbarg);
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* IOC interfaces
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#define bfa_ioc_pll_init_asic(__ioc) \
|
|
|
|
|
((__ioc)->ioc_hwif->ioc_pll_init((__ioc)->pcidev.pci_bar_kva, \
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
|
|
|
(__ioc)->asic_mode))
|
2010-08-24 11:24:12 +08:00
|
|
|
|
2011-08-30 23:27:37 +08:00
|
|
|
#define bfa_ioc_isr_mode_set(__ioc, __msix) do { \
|
|
|
|
|
if ((__ioc)->ioc_hwif->ioc_isr_mode_set) \
|
|
|
|
|
((__ioc)->ioc_hwif->ioc_isr_mode_set(__ioc, __msix)); \
|
|
|
|
|
} while (0)
|
2010-08-24 11:24:12 +08:00
|
|
|
#define bfa_ioc_ownership_reset(__ioc) \
|
|
|
|
|
((__ioc)->ioc_hwif->ioc_ownership_reset(__ioc))
|
|
|
|
|
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
|
|
|
#define bfa_ioc_lpu_read_stat(__ioc) do { \
|
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if ((__ioc)->ioc_hwif->ioc_lpu_read_stat) \
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((__ioc)->ioc_hwif->ioc_lpu_read_stat(__ioc)); \
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|
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} while (0)
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|
|
|
|
2010-08-26 14:00:27 +08:00
|
|
|
void bfa_nw_ioc_set_ct_hwif(struct bfa_ioc *ioc);
|
2011-09-27 18:39:05 +08:00
|
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|
void bfa_nw_ioc_set_ct2_hwif(struct bfa_ioc *ioc);
|
2010-08-24 11:24:12 +08:00
|
|
|
|
2010-08-26 14:00:27 +08:00
|
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void bfa_nw_ioc_attach(struct bfa_ioc *ioc, void *bfa,
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2010-08-24 11:24:12 +08:00
|
|
|
struct bfa_ioc_cbfn *cbfn);
|
2010-08-26 14:00:27 +08:00
|
|
|
void bfa_nw_ioc_auto_recover(bool auto_recover);
|
|
|
|
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void bfa_nw_ioc_detach(struct bfa_ioc *ioc);
|
|
|
|
|
void bfa_nw_ioc_pci_init(struct bfa_ioc *ioc, struct bfa_pcidev *pcidev,
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
|
|
|
enum bfi_pcifn_class clscode);
|
2010-08-26 14:00:27 +08:00
|
|
|
u32 bfa_nw_ioc_meminfo(void);
|
|
|
|
|
void bfa_nw_ioc_mem_claim(struct bfa_ioc *ioc, u8 *dm_kva, u64 dm_pa);
|
|
|
|
|
void bfa_nw_ioc_enable(struct bfa_ioc *ioc);
|
|
|
|
|
void bfa_nw_ioc_disable(struct bfa_ioc *ioc);
|
|
|
|
|
|
|
|
|
|
void bfa_nw_ioc_error_isr(struct bfa_ioc *ioc);
|
2011-07-22 16:07:42 +08:00
|
|
|
bool bfa_nw_ioc_is_disabled(struct bfa_ioc *ioc);
|
2010-08-26 14:00:27 +08:00
|
|
|
void bfa_nw_ioc_get_attr(struct bfa_ioc *ioc, struct bfa_ioc_attr *ioc_attr);
|
2011-07-22 16:07:42 +08:00
|
|
|
void bfa_nw_ioc_notify_register(struct bfa_ioc *ioc,
|
|
|
|
|
struct bfa_ioc_notify *notify);
|
2010-08-26 14:00:27 +08:00
|
|
|
bool bfa_nw_ioc_sem_get(void __iomem *sem_reg);
|
|
|
|
|
void bfa_nw_ioc_sem_release(void __iomem *sem_reg);
|
|
|
|
|
void bfa_nw_ioc_hw_sem_release(struct bfa_ioc *ioc);
|
|
|
|
|
void bfa_nw_ioc_fwver_get(struct bfa_ioc *ioc,
|
2010-08-24 11:24:12 +08:00
|
|
|
struct bfi_ioc_image_hdr *fwhdr);
|
2010-08-26 14:00:27 +08:00
|
|
|
bool bfa_nw_ioc_fwver_cmp(struct bfa_ioc *ioc,
|
2010-08-24 11:24:12 +08:00
|
|
|
struct bfi_ioc_image_hdr *fwhdr);
|
2010-08-26 14:00:27 +08:00
|
|
|
mac_t bfa_nw_ioc_get_mac(struct bfa_ioc *ioc);
|
2010-08-24 11:24:12 +08:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Timeout APIs
|
|
|
|
|
*/
|
2010-08-26 14:00:27 +08:00
|
|
|
void bfa_nw_ioc_timeout(void *ioc);
|
|
|
|
|
void bfa_nw_ioc_hb_check(void *ioc);
|
2010-12-24 05:45:09 +08:00
|
|
|
void bfa_nw_iocpf_timeout(void *ioc);
|
|
|
|
|
void bfa_nw_iocpf_sem_timeout(void *ioc);
|
2010-08-24 11:24:12 +08:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* F/W Image Size & Chunk
|
|
|
|
|
*/
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
|
|
|
u32 *bfa_cb_image_get_chunk(enum bfi_asic_gen asic_gen, u32 off);
|
|
|
|
|
u32 bfa_cb_image_get_size(enum bfi_asic_gen asic_gen);
|
2010-08-24 11:24:12 +08:00
|
|
|
|
|
|
|
|
#endif /* __BFA_IOC_H__ */
|