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linux/drivers/clk/zte/clk.h

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clk: zx: add clock support to zx296702 It adds a clock driver for zx296702 SoC to register the clock tree to Common Clock Framework. All the clocks of bus topology and some the peripheral clocks are ready with this commit. Some missing leaf clocks for peripherals will be added later when needed. Signed-off-by: Jun Nie <jun.nie@linaro.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@linaro.org>
2015-06-04 11:21:01 +08:00
/*
* Copyright 2015 Linaro Ltd.
* Copyright (C) 2014 ZTE Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ZTE_CLK_H
#define __ZTE_CLK_H
#include <linux/clk-provider.h>
#include <linux/spinlock.h>
struct zx_pll_config {
unsigned long rate;
u32 cfg0;
u32 cfg1;
};
struct clk_zx_pll {
struct clk_hw hw;
void __iomem *reg_base;
const struct zx_pll_config *lookup_table; /* order by rate asc */
int count;
spinlock_t *lock;
clk: zx: reform pll config info to ease code extension Add power down bit and pll lock bit in pll config structure to ease new SoC support. Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-06 14:02:41 +08:00
u8 pd_bit; /* power down bit */
u8 lock_bit; /* pll lock flag bit */
clk: zx: add clock support to zx296702 It adds a clock driver for zx296702 SoC to register the clock tree to Common Clock Framework. All the clocks of bus topology and some the peripheral clocks are ready with this commit. Some missing leaf clocks for peripherals will be added later when needed. Signed-off-by: Jun Nie <jun.nie@linaro.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@linaro.org>
2015-06-04 11:21:01 +08:00
};
struct clk *clk_register_zx_pll(const char *name, const char *parent_name,
unsigned long flags, void __iomem *reg_base,
const struct zx_pll_config *lookup_table, int count, spinlock_t *lock);
clk: zx: Add audio div clock method for zx296702 Add SPDIF/I2S divider clock method for zx296702 Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-23 15:02:51 +08:00
struct clk_zx_audio {
struct clk_hw hw;
void __iomem *reg_base;
};
struct clk *clk_register_zx_audio(const char *name,
const char * const parent_name,
unsigned long flags, void __iomem *reg_base);
clk: zx: reform pll config info to ease code extension Add power down bit and pll lock bit in pll config structure to ease new SoC support. Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-06 14:02:41 +08:00
extern const struct clk_ops zx_pll_ops;
clk: zx: add clock support to zx296702 It adds a clock driver for zx296702 SoC to register the clock tree to Common Clock Framework. All the clocks of bus topology and some the peripheral clocks are ready with this commit. Some missing leaf clocks for peripherals will be added later when needed. Signed-off-by: Jun Nie <jun.nie@linaro.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@linaro.org>
2015-06-04 11:21:01 +08:00
#endif