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linux/arch/arm/boot/dts/tegra124-venice2.dts

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ARM: tegra: add Venice2 board support Add support for the Tegra124 based Venice2 reference board. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-08 12:50:06 +08:00
/dts-v1/;
ARM: tegra: Enable Venice2 keyboard The keyboard on Venice2 is attached to the ChromeOS embedded controller. Add the corresponding device tree nodes and use the MATRIX_KEY define to encode keycodes. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-20 00:06:19 +08:00
#include <dt-bindings/input/input.h>
ARM: tegra: add Venice2 board support Add support for the Tegra124 based Venice2 reference board. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-08 12:50:06 +08:00
#include "tegra124.dtsi"
/ {
model = "NVIDIA Tegra124 Venice2";
compatible = "nvidia,venice2", "nvidia,tegra124";
ARM: tegra: set up /aliases for RTCs on Venice2 This ensures that the PMIC RTC provides the system time, rather than the on-SoC RTC, which is not battery-backed. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-20 02:32:15 +08:00
aliases {
ARM: tegra: use 2 address cells for Tegra124 DT Tegra124 can support 4GB of RAM. With that much RAM (plus some memory- mapped IO peripherals), more than 32-bits of physical address space is required. Hence, convert all Tegra124 DTs to use 2 DT cells for address space. (I think this was suggested by Olof Johansson, but I'm not 100% sure) Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-04 05:51:15 +08:00
rtc0 = "/i2c@0,7000d000/pmic@40";
rtc1 = "/rtc@0,7000e000";
ARM: tegra: set up /aliases for RTCs on Venice2 This ensures that the PMIC RTC provides the system time, rather than the on-SoC RTC, which is not battery-backed. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-20 02:32:15 +08:00
};
ARM: tegra: add Venice2 board support Add support for the Tegra124 based Venice2 reference board. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-08 12:50:06 +08:00
memory {
ARM: tegra: use 2 address cells for Tegra124 DT Tegra124 can support 4GB of RAM. With that much RAM (plus some memory- mapped IO peripherals), more than 32-bits of physical address space is required. Hence, convert all Tegra124 DTs to use 2 DT cells for address space. (I think this was suggested by Olof Johansson, but I'm not 100% sure) Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-04 05:51:15 +08:00
reg = <0x0 0x80000000 0x0 0x80000000>;
ARM: tegra: add Venice2 board support Add support for the Tegra124 based Venice2 reference board. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-08 12:50:06 +08:00
};
ARM: tegra: use 2 address cells for Tegra124 DT Tegra124 can support 4GB of RAM. With that much RAM (plus some memory- mapped IO peripherals), more than 32-bits of physical address space is required. Hence, convert all Tegra124 DTs to use 2 DT cells for address space. (I think this was suggested by Olof Johansson, but I'm not 100% sure) Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-04 05:51:15 +08:00
host1x@0,50000000 {
ARM: tegra: venice2 - Enable HDMI Add HDMI +5V, VDD and PLL regulators and enable the DDC I2C controller. Enable the HDMI device, provide the power supplies as well as the DDC adapter and use the standard pin (PN7) for hotplug detection. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-04-25 23:44:46 +08:00
hdmi@0,54280000 {
status = "okay";
vdd-supply = <&vdd_3v3_hdmi>;
pll-supply = <&vdd_hdmi_pll>;
hdmi-supply = <&vdd_5v0_hdmi>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
nvidia,hpd-gpio =
<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
};
ARM: tegra: use 2 address cells for Tegra124 DT Tegra124 can support 4GB of RAM. With that much RAM (plus some memory- mapped IO peripherals), more than 32-bits of physical address space is required. Hence, convert all Tegra124 DTs to use 2 DT cells for address space. (I think this was suggested by Olof Johansson, but I'm not 100% sure) Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-04 05:51:15 +08:00
sor@0,54540000 {
ARM: tegra: Enable eDP for Venice2 Venice2 has a 12.9" (2560x1700) panel connected to the eDP output of the Tegra124. The panel has an EDID to describe the video timings but needs a few extra nodes to get the backlight to come up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:24 +08:00
status = "okay";
nvidia,dpaux = <&dpaux>;
nvidia,panel = <&panel>;
};
ARM: tegra: Move pwm and dpaux labels to tegra124.dtsi These labels will be used by other boards in addition to Venice2, move them to tegra124.dtsi so they are defined in a common place. Signed-off-by: Dylan Reid <dgreid@chromium.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-09-05 06:20:34 +08:00
dpaux@0,545c0000 {
ARM: tegra: Enable eDP for Venice2 Venice2 has a 12.9" (2560x1700) panel connected to the eDP output of the Tegra124. The panel has an EDID to describe the video timings but needs a few extra nodes to get the backlight to come up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:24 +08:00
vdd-supply = <&vdd_3v3_panel>;
status = "okay";
};
};
ARM: tegra: use 2 address cells for Tegra124 DT Tegra124 can support 4GB of RAM. With that much RAM (plus some memory- mapped IO peripherals), more than 32-bits of physical address space is required. Hence, convert all Tegra124 DTs to use 2 DT cells for address space. (I think this was suggested by Olof Johansson, but I'm not 100% sure) Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-04 05:51:15 +08:00
pinmux: pinmux@0,70000868 {
ARM: tegra: rely on bootloader pinmux programming on Tegra124 The defined mechanism for programming the Tegra pinmux is to perform all of the following at once in order, before using any I/O controller that is affected by the pinmux: - Set the CLAMP_INPUTS_WHEN_TRISTATED PMC register bit. - Set up any GPIO pins to their "initial" state. - Program all pinmux settings in one go. Other methods such as: - Not setting CLAMP_INPUTS_WHEN_TRISTATED. - Not setting GPIOs to their "initial" state before programming the pinmux settings of the related pin, in particular the mux function. - Not programming the entire pinmux at once, in order to avoid possible conflicting settings. ... are not qualified or supported by NVIDIA ASIC/syseng. They could cause glitches or undesired output levels on some pins, or controller malfunction. While we've been getting away with doing something different on many Tegra boards without issue, I believe we've just been getting lucky. I'd like to switch all Tegra124 systems to the correct scheme now so they provide the right example to follow, and require that any new boards we support upstream work in the same fashion. While it would be nice to update boards containing older SoCs for consistency, I don't anticipate doing so. It's too much churn to change at this time. At least with all Tegra124 boards converted, the most recent boards provide the correct example. Since the bootloader needs to reprogram the pinmux to access certain peripherals, it must program the entire pinmux due to the supported rules above. As such, there is no need to program any part of the pinmux from the kernel, unless dynamic pinmuxing is used. Given this, we couuld simply remove the pinmux "default" state from the DT entirely. However, some bootloaders parse the DT to perform their initial pinmux setup, so it's useful to keep the pinmux data in DT. To allow this while avoiding redundant work in the kernel, rename the "default" state to "boot". The kernel won't apply this, but bootloaders can still look for this state name and apply it. Note however that the DT provides zero information about the required initial GPIO setup, so bootloaders using this approach are not likely to operate correctly without an additional GPIO initialization table somewhere. Previous discussions on the DT mailing list have rejected adding such a table to DT... The following U-Boot commits fully initialize the pinmux: Jetson TK1: 4ff213b8e478 ARM: tegra: clamp inputs on Jetson TK1 Venice2: 3365479ce78a ARM: tegra: Venice2 pinmux spreadsheet updates Both are part of U-Boot v2014.07 and later. Without those commits, the only fallout I see from this change is that HDMI on Venice2 no longer works. Given the very small user-base of this platform, I feel that requiring a bootloader update is reasonable. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-09-03 23:42:06 +08:00
pinctrl-names = "boot";
pinctrl-0 = <&pinmux_boot>;
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
ARM: tegra: rely on bootloader pinmux programming on Tegra124 The defined mechanism for programming the Tegra pinmux is to perform all of the following at once in order, before using any I/O controller that is affected by the pinmux: - Set the CLAMP_INPUTS_WHEN_TRISTATED PMC register bit. - Set up any GPIO pins to their "initial" state. - Program all pinmux settings in one go. Other methods such as: - Not setting CLAMP_INPUTS_WHEN_TRISTATED. - Not setting GPIOs to their "initial" state before programming the pinmux settings of the related pin, in particular the mux function. - Not programming the entire pinmux at once, in order to avoid possible conflicting settings. ... are not qualified or supported by NVIDIA ASIC/syseng. They could cause glitches or undesired output levels on some pins, or controller malfunction. While we've been getting away with doing something different on many Tegra boards without issue, I believe we've just been getting lucky. I'd like to switch all Tegra124 systems to the correct scheme now so they provide the right example to follow, and require that any new boards we support upstream work in the same fashion. While it would be nice to update boards containing older SoCs for consistency, I don't anticipate doing so. It's too much churn to change at this time. At least with all Tegra124 boards converted, the most recent boards provide the correct example. Since the bootloader needs to reprogram the pinmux to access certain peripherals, it must program the entire pinmux due to the supported rules above. As such, there is no need to program any part of the pinmux from the kernel, unless dynamic pinmuxing is used. Given this, we couuld simply remove the pinmux "default" state from the DT entirely. However, some bootloaders parse the DT to perform their initial pinmux setup, so it's useful to keep the pinmux data in DT. To allow this while avoiding redundant work in the kernel, rename the "default" state to "boot". The kernel won't apply this, but bootloaders can still look for this state name and apply it. Note however that the DT provides zero information about the required initial GPIO setup, so bootloaders using this approach are not likely to operate correctly without an additional GPIO initialization table somewhere. Previous discussions on the DT mailing list have rejected adding such a table to DT... The following U-Boot commits fully initialize the pinmux: Jetson TK1: 4ff213b8e478 ARM: tegra: clamp inputs on Jetson TK1 Venice2: 3365479ce78a ARM: tegra: Venice2 pinmux spreadsheet updates Both are part of U-Boot v2014.07 and later. Without those commits, the only fallout I see from this change is that HDMI on Venice2 no longer works. Given the very small user-base of this platform, I feel that requiring a bootloader update is reasonable. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-09-03 23:42:06 +08:00
pinmux_boot: common {
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
dap_mclk1_pw4 {
nvidia,pins = "dap_mclk1_pw4";
nvidia,function = "extperiph1";
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
dap1_din_pn1 {
ARM: tegra: fix missing pincontrol configuration for Venice2 Compare the initial population of default pinmux configuration of Venice2 with the chrome branch and add/fix the missing configurations. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:58 +08:00
nvidia,pins = "dap1_din_pn1";
nvidia,function = "i2s0";
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
dap1_dout_pn2 {
nvidia,pins = "dap1_dout_pn2",
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
"dap1_fs_pn0",
"dap1_sclk_pn3";
nvidia,function = "i2s0";
ARM: tegra: fix missing pincontrol configuration for Venice2 Compare the initial population of default pinmux configuration of Venice2 with the chrome branch and add/fix the missing configurations. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:58 +08:00
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
dap2_din_pa4 {
ARM: tegra: fix missing pincontrol configuration for Venice2 Compare the initial population of default pinmux configuration of Venice2 with the chrome branch and add/fix the missing configurations. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:58 +08:00
nvidia,pins = "dap2_din_pa4";
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
nvidia,function = "i2s1";
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
ARM: tegra: fix pinctrl misconfiguration on Venice2 Other boards use PULL_NONE for their debug UART pins, and without this change, the board doesn't accept any serial input. Don't set the I2S port pins to tristate mode, or no audio signal will be sent out. Fixes: 605ae5804385 ("ARM: tegra: add default pinctrl nodes for Venice2") Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-13 05:40:30 +08:00
nvidia,tristate = <TEGRA_PIN_DISABLE>;
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
};
ARM: tegra: fix missing pincontrol configuration for Venice2 Compare the initial population of default pinmux configuration of Venice2 with the chrome branch and add/fix the missing configurations. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:58 +08:00
dap2_dout_pa5 {
nvidia,pins = "dap2_dout_pa5",
"dap2_fs_pa2",
"dap2_sclk_pa3";
nvidia,function = "i2s1";
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
ARM: tegra: fix missing pincontrol configuration for Venice2 Compare the initial population of default pinmux configuration of Venice2 with the chrome branch and add/fix the missing configurations. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:58 +08:00
nvidia,tristate = <TEGRA_PIN_DISABLE>;
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
};
ARM: tegra: fix missing pincontrol configuration for Venice2 Compare the initial population of default pinmux configuration of Venice2 with the chrome branch and add/fix the missing configurations. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:58 +08:00
dvfs_pwm_px0 {
nvidia,pins = "dvfs_pwm_px0",
"dvfs_clk_px2";
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
nvidia,function = "cldvfs";
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
ulpi_clk_py0 {
nvidia,pins = "ulpi_clk_py0",
"ulpi_nxt_py2",
"ulpi_stp_py3";
nvidia,function = "spi1";
ARM: tegra: fix missing pincontrol configuration for Venice2 Compare the initial population of default pinmux configuration of Venice2 with the chrome branch and add/fix the missing configurations. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:58 +08:00
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
ulpi_dir_py1 {
nvidia,pins = "ulpi_dir_py1";
nvidia,function = "spi1";
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
ARM: tegra: fix missing pincontrol configuration for Venice2 Compare the initial population of default pinmux configuration of Venice2 with the chrome branch and add/fix the missing configurations. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:58 +08:00
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
cam_i2c_scl_pbb1 {
nvidia,pins = "cam_i2c_scl_pbb1",
"cam_i2c_sda_pbb2";
nvidia,function = "i2c3";
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
};
gen2_i2c_scl_pt5 {
nvidia,pins = "gen2_i2c_scl_pt5",
"gen2_i2c_sda_pt6";
nvidia,function = "i2c2";
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
};
pg4 {
nvidia,pins = "pg4",
"pg5",
"pg6",
"pi3";
nvidia,function = "spi4";
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
ARM: tegra: fix missing pincontrol configuration for Venice2 Compare the initial population of default pinmux configuration of Venice2 with the chrome branch and add/fix the missing configurations. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:58 +08:00
pg7 {
nvidia,pins = "pg7";
nvidia,function = "spi4";
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
ARM: tegra: fix missing pincontrol configuration for Venice2 Compare the initial population of default pinmux configuration of Venice2 with the chrome branch and add/fix the missing configurations. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:58 +08:00
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
};
ph1 {
nvidia,pins = "ph1";
nvidia,function = "pwm1";
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
ARM: tegra: fix missing pincontrol configuration for Venice2 Compare the initial population of default pinmux configuration of Venice2 with the chrome branch and add/fix the missing configurations. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:58 +08:00
pk0 {
nvidia,pins = "pk0",
"kb_row15_ps7",
"clk_32k_out_pa0";
nvidia,function = "soc";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
ARM: tegra: Fix misconfiguration of pin PH2 on Venice2 This pin needs to be configured in pull-down, non-tristate mode in order for the backlight to work correctly. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-14 00:25:04 +08:00
nvidia,tristate = <TEGRA_PIN_DISABLE>;
ARM: tegra: fix missing pincontrol configuration for Venice2 Compare the initial population of default pinmux configuration of Venice2 with the chrome branch and add/fix the missing configurations. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:58 +08:00
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
ARM: tegra: Fix misconfiguration of pin PH2 on Venice2 This pin needs to be configured in pull-down, non-tristate mode in order for the backlight to work correctly. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-14 00:25:04 +08:00
};
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
sdmmc1_clk_pz0 {
ARM: tegra: fix board DT pinmux setup Neither Tegra114 nor Tegra124 allow "low power mode" to be configured on SDIO1 or SDIO3 drive groups. Remove the attempt to configure that option from the Dalmore and Venice2 DTs. The Venice2 DT contained duplicate configurations for most sdmmc1_* pins. Remove the duplicate pins from one of the nodes, and fix the configuration since the remaining clk pin is output-only. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-21 08:06:01 +08:00
nvidia,pins = "sdmmc1_clk_pz0";
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
nvidia,function = "sdmmc1";
ARM: tegra: fix board DT pinmux setup Neither Tegra114 nor Tegra124 allow "low power mode" to be configured on SDIO1 or SDIO3 drive groups. Remove the attempt to configure that option from the Dalmore and Venice2 DTs. The Venice2 DT contained duplicate configurations for most sdmmc1_* pins. Remove the duplicate pins from one of the nodes, and fix the configuration since the remaining clk pin is output-only. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-21 08:06:01 +08:00
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
ARM: tegra: fix missing pincontrol configuration for Venice2 Compare the initial population of default pinmux configuration of Venice2 with the chrome branch and add/fix the missing configurations. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:58 +08:00
sdmmc1_cmd_pz1 {
nvidia,pins = "sdmmc1_cmd_pz1",
"sdmmc1_dat0_py7",
"sdmmc1_dat1_py6",
"sdmmc1_dat2_py5",
"sdmmc1_dat3_py4";
nvidia,function = "sdmmc1";
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
sdmmc3_clk_pa6 {
nvidia,pins = "sdmmc3_clk_pa6";
nvidia,function = "sdmmc3";
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
sdmmc3_cmd_pa7 {
nvidia,pins = "sdmmc3_cmd_pa7",
"sdmmc3_dat0_pb7",
"sdmmc3_dat1_pb6",
"sdmmc3_dat2_pb5",
"sdmmc3_dat3_pb4",
"sdmmc3_clk_lb_out_pee4",
"sdmmc3_clk_lb_in_pee5";
nvidia,function = "sdmmc3";
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
sdmmc4_clk_pcc4 {
nvidia,pins = "sdmmc4_clk_pcc4";
nvidia,function = "sdmmc4";
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
sdmmc4_cmd_pt7 {
nvidia,pins = "sdmmc4_cmd_pt7",
"sdmmc4_dat0_paa0",
"sdmmc4_dat1_paa1",
"sdmmc4_dat2_paa2",
"sdmmc4_dat3_paa3",
"sdmmc4_dat4_paa4",
"sdmmc4_dat5_paa5",
"sdmmc4_dat6_paa6",
"sdmmc4_dat7_paa7";
nvidia,function = "sdmmc4";
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
pwr_i2c_scl_pz6 {
nvidia,pins = "pwr_i2c_scl_pz6",
"pwr_i2c_sda_pz7";
nvidia,function = "i2cpwr";
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
ARM: tegra: fix missing pincontrol configuration for Venice2 Compare the initial population of default pinmux configuration of Venice2 with the chrome branch and add/fix the missing configurations. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:58 +08:00
nvidia,lock = <TEGRA_PIN_DISABLE>;
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
};
jtag_rtck {
nvidia,pins = "jtag_rtck";
nvidia,function = "rtck";
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
clk_32k_in {
nvidia,pins = "clk_32k_in";
nvidia,function = "clk";
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
core_pwr_req {
nvidia,pins = "core_pwr_req";
nvidia,function = "pwron";
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
cpu_pwr_req {
nvidia,pins = "cpu_pwr_req";
nvidia,function = "cpu";
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
pwr_int_n {
nvidia,pins = "pwr_int_n";
nvidia,function = "pmi";
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
reset_out_n {
nvidia,pins = "reset_out_n";
nvidia,function = "reset_out_n";
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
clk3_out_pee0 {
nvidia,pins = "clk3_out_pee0";
nvidia,function = "extperiph3";
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
dap4_din_pp5 {
ARM: tegra: fix missing pincontrol configuration for Venice2 Compare the initial population of default pinmux configuration of Venice2 with the chrome branch and add/fix the missing configurations. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:58 +08:00
nvidia,pins = "dap4_din_pp5";
nvidia,function = "i2s3";
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
dap4_dout_pp6 {
nvidia,pins = "dap4_dout_pp6",
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
"dap4_fs_pp4",
"dap4_sclk_pp7";
nvidia,function = "i2s3";
ARM: tegra: fix missing pincontrol configuration for Venice2 Compare the initial population of default pinmux configuration of Venice2 with the chrome branch and add/fix the missing configurations. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:58 +08:00
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
gen1_i2c_sda_pc5 {
nvidia,pins = "gen1_i2c_sda_pc5",
"gen1_i2c_scl_pc4";
nvidia,function = "i2c1";
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
ARM: tegra: fix missing pincontrol configuration for Venice2 Compare the initial population of default pinmux configuration of Venice2 with the chrome branch and add/fix the missing configurations. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:58 +08:00
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
};
ARM: tegra: fix missing pincontrol configuration for Venice2 Compare the initial population of default pinmux configuration of Venice2 with the chrome branch and add/fix the missing configurations. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:58 +08:00
uart2_cts_n_pj5 {
nvidia,pins = "uart2_cts_n_pj5";
nvidia,function = "uartb";
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
ARM: tegra: fix pinctrl misconfiguration on Venice2 Other boards use PULL_NONE for their debug UART pins, and without this change, the board doesn't accept any serial input. Don't set the I2S port pins to tristate mode, or no audio signal will be sent out. Fixes: 605ae5804385 ("ARM: tegra: add default pinctrl nodes for Venice2") Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-13 05:40:30 +08:00
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
ARM: tegra: fix missing pincontrol configuration for Venice2 Compare the initial population of default pinmux configuration of Venice2 with the chrome branch and add/fix the missing configurations. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:58 +08:00
uart2_rts_n_pj6 {
nvidia,pins = "uart2_rts_n_pj6";
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
nvidia,function = "uartb";
ARM: tegra: fix missing pincontrol configuration for Venice2 Compare the initial population of default pinmux configuration of Venice2 with the chrome branch and add/fix the missing configurations. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:58 +08:00
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
uart2_rxd_pc3 {
ARM: tegra: fix missing pincontrol configuration for Venice2 Compare the initial population of default pinmux configuration of Venice2 with the chrome branch and add/fix the missing configurations. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:58 +08:00
nvidia,pins = "uart2_rxd_pc3";
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
nvidia,function = "irda";
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
ARM: tegra: fix missing pincontrol configuration for Venice2 Compare the initial population of default pinmux configuration of Venice2 with the chrome branch and add/fix the missing configurations. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:58 +08:00
uart2_txd_pc2 {
nvidia,pins = "uart2_txd_pc2";
nvidia,function = "irda";
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
uart3_cts_n_pa1 {
nvidia,pins = "uart3_cts_n_pa1",
ARM: tegra: fix missing pincontrol configuration for Venice2 Compare the initial population of default pinmux configuration of Venice2 with the chrome branch and add/fix the missing configurations. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:58 +08:00
"uart3_rxd_pw7";
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
nvidia,function = "uartc";
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
ARM: tegra: fix missing pincontrol configuration for Venice2 Compare the initial population of default pinmux configuration of Venice2 with the chrome branch and add/fix the missing configurations. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:58 +08:00
uart3_rts_n_pc0 {
nvidia,pins = "uart3_rts_n_pc0",
"uart3_txd_pw6";
nvidia,function = "uartc";
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
hdmi_cec_pee3 {
nvidia,pins = "hdmi_cec_pee3";
nvidia,function = "cec";
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
ARM: tegra: fix missing pincontrol configuration for Venice2 Compare the initial population of default pinmux configuration of Venice2 with the chrome branch and add/fix the missing configurations. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:58 +08:00
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
hdmi_int_pn7 {
nvidia,pins = "hdmi_int_pn7";
nvidia,function = "rsvd1";
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
};
ddc_scl_pv4 {
nvidia,pins = "ddc_scl_pv4",
"ddc_sda_pv5";
nvidia,function = "i2c4";
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
ARM: tegra: fix missing pincontrol configuration for Venice2 Compare the initial population of default pinmux configuration of Venice2 with the chrome branch and add/fix the missing configurations. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:58 +08:00
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
};
pj7 {
nvidia,pins = "pj7",
"pk7";
nvidia,function = "uartd";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
pb0 {
nvidia,pins = "pb0",
"pb1";
nvidia,function = "uartd";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
ph0 {
nvidia,pins = "ph0";
nvidia,function = "pwm0";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
kb_row10_ps2 {
nvidia,pins = "kb_row10_ps2";
nvidia,function = "uarta";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
kb_row9_ps1 {
nvidia,pins = "kb_row9_ps1";
nvidia,function = "uarta";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
kb_row6_pr6 {
nvidia,pins = "kb_row6_pr6";
nvidia,function = "displaya_alt";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
};
usb_vbus_en0_pn4 {
ARM: tegra: Combine VBUS enable pins into one node Both USB_VBUS_EN0 and USB_VBUS_EN1 are configured the same way, so they can be combined into a single node. While at it, don't configure them as pull-up since they already have external pull-ups. Also U-Boot doesn't configure them as pull-up either. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-02-25 23:45:04 +08:00
nvidia,pins = "usb_vbus_en0_pn4",
"usb_vbus_en1_pn5";
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
nvidia,function = "usb";
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
ARM: tegra: Combine VBUS enable pins into one node Both USB_VBUS_EN0 and USB_VBUS_EN1 are configured the same way, so they can be combined into a single node. While at it, don't configure them as pull-up since they already have external pull-ups. Also U-Boot doesn't configure them as pull-up either. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-02-25 23:45:04 +08:00
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
ARM: tegra: fix missing pincontrol configuration for Venice2 Compare the initial population of default pinmux configuration of Venice2 with the chrome branch and add/fix the missing configurations. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:58 +08:00
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
};
drive_sdio1 {
nvidia,pins = "drive_sdio1";
nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
nvidia,pull-down-strength = <32>;
nvidia,pull-up-strength = <42>;
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
};
drive_sdio3 {
nvidia,pins = "drive_sdio3";
nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
nvidia,pull-down-strength = <20>;
nvidia,pull-up-strength = <36>;
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
};
drive_gma {
nvidia,pins = "drive_gma";
nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
nvidia,pull-down-strength = <1>;
nvidia,pull-up-strength = <2>;
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
nvidia,drive-type = <1>;
};
ARM: tegra: fix missing pincontrol configuration for Venice2 Compare the initial population of default pinmux configuration of Venice2 with the chrome branch and add/fix the missing configurations. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:58 +08:00
als_irq_l {
nvidia,pins = "gpio_x3_aud_px3";
nvidia,function = "gmi";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
codec_irq_l {
nvidia,pins = "ph4";
nvidia,function = "gmi";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
lcd_bl_en {
nvidia,pins = "ph2";
nvidia,function = "gmi";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
touch_irq_l {
nvidia,pins = "gpio_w3_aud_pw3";
nvidia,function = "spi6";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
tpm_davint_l {
nvidia,pins = "ph6";
nvidia,function = "gmi";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
ts_irq_l {
nvidia,pins = "pk2";
nvidia,function = "gmi";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
ts_reset_l {
nvidia,pins = "pk4";
nvidia,function = "gmi";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
ts_shdn_l {
nvidia,pins = "pk1";
nvidia,function = "gmi";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
ph7 {
nvidia,pins = "ph7";
nvidia,function = "gmi";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
kb_col0_ap {
nvidia,pins = "kb_col0_pq0";
nvidia,function = "rsvd4";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
lid_open {
nvidia,pins = "kb_row4_pr4";
nvidia,function = "rsvd3";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
en_vdd_sd {
nvidia,pins = "kb_row0_pr0";
nvidia,function = "rsvd4";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
ac_ok {
nvidia,pins = "pj0";
nvidia,function = "gmi";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
sensor_irq_l {
nvidia,pins = "pi6";
nvidia,function = "gmi";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
wifi_en {
nvidia,pins = "gpio_x7_aud_px7";
nvidia,function = "rsvd4";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
wifi_rst_l {
nvidia,pins = "clk2_req_pcc5";
nvidia,function = "dap";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
hp_det_l {
nvidia,pins = "ulpi_data1_po2";
nvidia,function = "spi3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
};
};
ARM: tegra: use 2 address cells for Tegra124 DT Tegra124 can support 4GB of RAM. With that much RAM (plus some memory- mapped IO peripherals), more than 32-bits of physical address space is required. Hence, convert all Tegra124 DTs to use 2 DT cells for address space. (I think this was suggested by Olof Johansson, but I'm not 100% sure) Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-04 05:51:15 +08:00
serial@0,70006000 {
ARM: tegra: add Venice2 board support Add support for the Tegra124 based Venice2 reference board. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-08 12:50:06 +08:00
status = "okay";
};
ARM: tegra: Move pwm and dpaux labels to tegra124.dtsi These labels will be used by other boards in addition to Venice2, move them to tegra124.dtsi so they are defined in a common place. Signed-off-by: Dylan Reid <dgreid@chromium.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-09-05 06:20:34 +08:00
pwm@0,7000a000 {
ARM: tegra: Enable PWM on Venice2 Subsequent patches will need to reference a PWM channel for backlight support, so enable the PWM device and assign a label to it. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-11-19 00:00:35 +08:00
status = "okay";
};
ARM: tegra: use 2 address cells for Tegra124 DT Tegra124 can support 4GB of RAM. With that much RAM (plus some memory- mapped IO peripherals), more than 32-bits of physical address space is required. Hence, convert all Tegra124 DTs to use 2 DT cells for address space. (I think this was suggested by Olof Johansson, but I'm not 100% sure) Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-04 05:51:15 +08:00
i2c@0,7000c000 {
ARM: tegra: enable I2C controllers on Venice2 Enable all the I2C controllers that are wired up on Venice2. I don't know the correct I2C bus clock rates, so set them all to a conservative 100KHz for now. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-04 07:44:35 +08:00
status = "okay";
clock-frequency = <100000>;
ARM: tegra: add sound card to Venice2 DT Venice2 uses the MAX98090 audio CODEC, and supports built-in speakers, and a combo headphones/microphone jack. Add a top-level sound card node to represent this. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-04 08:26:12 +08:00
acodec: audio-codec@10 {
compatible = "maxim,max98090";
reg = <0x10>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
};
ARM: tegra: enable I2C controllers on Venice2 Enable all the I2C controllers that are wired up on Venice2. I don't know the correct I2C bus clock rates, so set them all to a conservative 100KHz for now. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-04 07:44:35 +08:00
};
ARM: tegra: use 2 address cells for Tegra124 DT Tegra124 can support 4GB of RAM. With that much RAM (plus some memory- mapped IO peripherals), more than 32-bits of physical address space is required. Hence, convert all Tegra124 DTs to use 2 DT cells for address space. (I think this was suggested by Olof Johansson, but I'm not 100% sure) Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-04 05:51:15 +08:00
i2c@0,7000c400 {
ARM: tegra: enable I2C controllers on Venice2 Enable all the I2C controllers that are wired up on Venice2. I don't know the correct I2C bus clock rates, so set them all to a conservative 100KHz for now. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-04 07:44:35 +08:00
status = "okay";
clock-frequency = <100000>;
ARM: tegra: add touchpad to Venice2 DT Venice2 contains an Atmel MXT touchpad. Add an I2C node for it to DT. The Linux driver doesn't quite work on this platform yet, but adding the DT node causes no issues, and will allow the device to work once the driver is fixed. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-09-02 23:57:09 +08:00
trackpad@4b {
compatible = "atmel,maxtouch";
reg = <0x4b>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_LOW>;
linux,gpio-keymap = <0 0 0 BTN_LEFT>;
};
ARM: tegra: enable I2C controllers on Venice2 Enable all the I2C controllers that are wired up on Venice2. I don't know the correct I2C bus clock rates, so set them all to a conservative 100KHz for now. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-04 07:44:35 +08:00
};
ARM: tegra: use 2 address cells for Tegra124 DT Tegra124 can support 4GB of RAM. With that much RAM (plus some memory- mapped IO peripherals), more than 32-bits of physical address space is required. Hence, convert all Tegra124 DTs to use 2 DT cells for address space. (I think this was suggested by Olof Johansson, but I'm not 100% sure) Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-04 05:51:15 +08:00
i2c@0,7000c500 {
ARM: tegra: enable I2C controllers on Venice2 Enable all the I2C controllers that are wired up on Venice2. I don't know the correct I2C bus clock rates, so set them all to a conservative 100KHz for now. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-04 07:44:35 +08:00
status = "okay";
clock-frequency = <100000>;
};
ARM: tegra: venice2 - Enable HDMI Add HDMI +5V, VDD and PLL regulators and enable the DDC I2C controller. Enable the HDMI device, provide the power supplies as well as the DDC adapter and use the standard pin (PN7) for hotplug detection. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-04-25 23:44:46 +08:00
hdmi_ddc: i2c@0,7000c700 {
ARM: tegra: enable I2C controllers on Venice2 Enable all the I2C controllers that are wired up on Venice2. I don't know the correct I2C bus clock rates, so set them all to a conservative 100KHz for now. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-04 07:44:35 +08:00
status = "okay";
clock-frequency = <100000>;
};
ARM: tegra: use 2 address cells for Tegra124 DT Tegra124 can support 4GB of RAM. With that much RAM (plus some memory- mapped IO peripherals), more than 32-bits of physical address space is required. Hence, convert all Tegra124 DTs to use 2 DT cells for address space. (I think this was suggested by Olof Johansson, but I'm not 100% sure) Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-04 05:51:15 +08:00
i2c@0,7000d000 {
ARM: tegra: enable I2C controllers on Venice2 Enable all the I2C controllers that are wired up on Venice2. I don't know the correct I2C bus clock rates, so set them all to a conservative 100KHz for now. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-04 07:44:35 +08:00
status = "okay";
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
clock-frequency = <400000>;
ARM: tegra: Rename as3722 node to pmic Device tree node name should reflect the kind of device rather than the specific name of the device. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:28 +08:00
pmic: pmic@40 {
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
compatible = "ams,as3722";
reg = <0x40>;
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
ARM: tegra: add system-power-controller property for PMIC node Add system-power-controller property to system PMIC, ams AS3722, node to enable power off functionality through PMIC. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-01-09 19:01:48 +08:00
ams,system-power-controller;
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
#interrupt-cells = <2>;
interrupt-controller;
gpio-controller;
#gpio-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&as3722_default>;
as3722_default: pinmux {
gpio0 {
pins = "gpio0";
function = "gpio";
bias-pull-down;
};
gpio1_2_4_7 {
pins = "gpio1", "gpio2", "gpio4", "gpio7";
function = "gpio";
bias-pull-up;
};
gpio3_6 {
pins = "gpio3", "gpio6";
bias-high-impedance;
};
gpio5 {
pins = "gpio5";
function = "clk32k-out";
};
};
regulators {
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
vsup-sd2-supply = <&vdd_5v0_sys>;
vsup-sd3-supply = <&vdd_5v0_sys>;
vsup-sd4-supply = <&vdd_5v0_sys>;
vsup-sd5-supply = <&vdd_5v0_sys>;
vin-ldo0-supply = <&vdd_1v35_lp0>;
vin-ldo1-6-supply = <&vdd_3v3_run>;
vin-ldo2-5-7-supply = <&vddio_1v8>;
vin-ldo3-4-supply = <&vdd_3v3_sys>;
vin-ldo9-10-supply = <&vdd_5v0_sys>;
vin-ldo11-supply = <&vdd_3v3_run>;
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
sd0 {
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
regulator-name = "+VDD_CPU_AP";
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1400000>;
regulator-min-microamp = <3500000>;
regulator-max-microamp = <3500000>;
regulator-always-on;
regulator-boot-on;
ARM: tegra: Fix typoed ams,ext-control properties The property for enabling external rail control on the AS3722 is ams,ext-control, not ams,external-control. Since the external rail control property was previously being ignored, LP1 suspend on these boards wasn't actually turning the CPU rail off at all. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-10 02:53:17 +08:00
ams,ext-control = <2>;
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
};
sd1 {
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
regulator-name = "+VDD_CORE";
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1350000>;
regulator-min-microamp = <2500000>;
regulator-max-microamp = <2500000>;
regulator-always-on;
regulator-boot-on;
ARM: tegra: Fix typoed ams,ext-control properties The property for enabling external rail control on the AS3722 is ams,ext-control, not ams,external-control. Since the external rail control property was previously being ignored, LP1 suspend on these boards wasn't actually turning the CPU rail off at all. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-10 02:53:17 +08:00
ams,ext-control = <1>;
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
};
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
vdd_1v35_lp0: sd2 {
regulator-name = "+1.35V_LP0(sd2)";
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-boot-on;
};
sd3 {
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
regulator-name = "+1.35V_LP0(sd3)";
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-boot-on;
};
ARM: tegra: venice2 - Enable HDMI Add HDMI +5V, VDD and PLL regulators and enable the DDC I2C controller. Enable the HDMI device, provide the power supplies as well as the DDC adapter and use the standard pin (PN7) for hotplug detection. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-04-25 23:44:46 +08:00
vdd_1v05_run: sd4 {
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
regulator-name = "+1.05V_RUN";
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
};
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
vddio_1v8: sd5 {
regulator-name = "+1.8V_VDDIO";
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
sd6 {
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
regulator-name = "+VDD_GPU_AP";
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
regulator-min-microvolt = <650000>;
regulator-max-microvolt = <1200000>;
regulator-min-microamp = <3500000>;
regulator-max-microamp = <3500000>;
regulator-boot-on;
regulator-always-on;
};
ldo0 {
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
regulator-name = "+1.05V_RUN_AVDD";
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
regulator-boot-on;
regulator-always-on;
ARM: tegra: Fix typoed ams,ext-control properties The property for enabling external rail control on the AS3722 is ams,ext-control, not ams,external-control. Since the external rail control property was previously being ignored, LP1 suspend on these boards wasn't actually turning the CPU rail off at all. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-10 02:53:17 +08:00
ams,ext-control = <1>;
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
};
ldo1 {
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
regulator-name = "+1.8V_RUN_CAM";
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo2 {
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
regulator-name = "+1.2V_GEN_AVDD";
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
regulator-always-on;
};
ldo3 {
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
regulator-name = "+1.00V_LP0_VDD_RTC";
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
regulator-always-on;
ams,enable-tracking;
};
ARM: tegra: Enable USB on Venice2 USB1 and USB3 are routed to two external connectors, while USB2 is used for the integrated webcam. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:26 +08:00
vdd_run_cam: ldo4 {
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
regulator-name = "+3.3V_RUN_CAM";
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
ldo5 {
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
regulator-name = "+1.2V_RUN_CAM_FRONT";
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
ARM: tegra: Hook up SDMMC3 power-supply on Venice2 The SDMMC3 interface is supplied with 1.8V by the PMICs LDO6. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:21 +08:00
vddio_sdmmc3: ldo6 {
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
regulator-name = "+VDDIO_SDMMC3";
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
ldo7 {
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
regulator-name = "+1.05V_RUN_CAM_REAR";
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
};
ldo9 {
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
regulator-name = "+2.8V_RUN_TOUCH";
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
ldo10 {
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
regulator-name = "+2.8V_RUN_CAM_AF";
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
ldo11 {
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
regulator-name = "+1.8V_RUN_VPP_FUSE";
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
};
ARM: tegra: enable I2C controllers on Venice2 Enable all the I2C controllers that are wired up on Venice2. I don't know the correct I2C bus clock rates, so set them all to a conservative 100KHz for now. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-04 07:44:35 +08:00
};
ARM: tegra: use 2 address cells for Tegra124 DT Tegra124 can support 4GB of RAM. With that much RAM (plus some memory- mapped IO peripherals), more than 32-bits of physical address space is required. Hence, convert all Tegra124 DTs to use 2 DT cells for address space. (I think this was suggested by Olof Johansson, but I'm not 100% sure) Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-04 05:51:15 +08:00
spi@0,7000d400 {
ARM: tegra: Enable Venice2 keyboard The keyboard on Venice2 is attached to the ChromeOS embedded controller. Add the corresponding device tree nodes and use the MATRIX_KEY define to encode keycodes. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-20 00:06:19 +08:00
status = "okay";
ARM: tegra: Use the cros-ec-keyboard fragment in venice2 Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-06-05 06:20:19 +08:00
cros_ec: cros-ec@0 {
ARM: tegra: Enable Venice2 keyboard The keyboard on Venice2 is attached to the ChromeOS embedded controller. Add the corresponding device tree nodes and use the MATRIX_KEY define to encode keycodes. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-20 00:06:19 +08:00
compatible = "google,cros-ec-spi";
spi-max-frequency = <4000000>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
reg = <0>;
google,cros-ec-spi-msg-delay = <2000>;
ARM: tegra: Add the EC i2c tunnel to tegra124-venice2 This adds the EC i2c tunnel (and devices under it) to the tegra124-venice2 device tree. Signed-off-by: Doug Anderson <dianders@chromium.org> Tested-by: Andrew Bresticker <abrestic@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-05-01 01:44:10 +08:00
i2c-tunnel {
compatible = "google,cros-ec-i2c-tunnel";
#address-cells = <1>;
#size-cells = <0>;
google,remote-bus = <0>;
charger: bq24735@9 {
compatible = "ti,bq24735";
reg = <0x9>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(J, 0)
GPIO_ACTIVE_HIGH>;
ti,ac-detect-gpios = <&gpio
TEGRA_GPIO(J, 0)
GPIO_ACTIVE_HIGH>;
};
battery: sbs-battery@b {
compatible = "sbs,sbs-battery";
reg = <0xb>;
sbs,i2c-retry-count = <2>;
sbs,poll-retry-count = <1>;
};
};
ARM: tegra: Enable Venice2 keyboard The keyboard on Venice2 is attached to the ChromeOS embedded controller. Add the corresponding device tree nodes and use the MATRIX_KEY define to encode keycodes. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-20 00:06:19 +08:00
};
};
ARM: tegra: use 2 address cells for Tegra124 DT Tegra124 can support 4GB of RAM. With that much RAM (plus some memory- mapped IO peripherals), more than 32-bits of physical address space is required. Hence, convert all Tegra124 DTs to use 2 DT cells for address space. (I think this was suggested by Olof Johansson, but I'm not 100% sure) Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-04 05:51:15 +08:00
spi@0,7000da00 {
ARM: tegra: add SPI flash to Venice2 DT Venice2 contains an SPI Flash chip, which contains the bootloader. Add this to the DT, so the kernel can access it. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-02-19 06:03:21 +08:00
status = "okay";
spi-max-frequency = <25000000>;
spi-flash@0 {
compatible = "winbond,w25q32dw";
reg = <0>;
spi-max-frequency = <20000000>;
};
};
ARM: tegra: use 2 address cells for Tegra124 DT Tegra124 can support 4GB of RAM. With that much RAM (plus some memory- mapped IO peripherals), more than 32-bits of physical address space is required. Hence, convert all Tegra124 DTs to use 2 DT cells for address space. (I think this was suggested by Olof Johansson, but I'm not 100% sure) Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-04 05:51:15 +08:00
pmc@0,7000e400 {
ARM: tegra: add Venice2 board support Add support for the Tegra124 based Venice2 reference board. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-08 12:50:06 +08:00
nvidia,invert-interrupt;
ARM: tegra: enable LP1 suspend mode for Venice2 Enable LP1 suspend mode for Tegra124 Venice2 board. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-11 17:58:39 +08:00
nvidia,suspend-mode = <1>;
nvidia,cpu-pwr-good-time = <500>;
nvidia,cpu-pwr-off-time = <300>;
nvidia,core-pwr-good-time = <641 3845>;
nvidia,core-pwr-off-time = <61036>;
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
ARM: tegra: add Venice2 board support Add support for the Tegra124 based Venice2 reference board. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-08 12:50:06 +08:00
};
ARM: tegra: add clock properties for devices of Tegra124 This patch adds clock properties for devices in the DT for basic support of Tegra124 SoC. Signed-off-by: Joseph Lo <josephl@nvidia.com> [swarren, added missing unit address to "clock" node] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-08 15:47:40 +08:00
ARM: tegra: venice2 - Enable HDA Turn on the HDA controller in Venice2, it is used for HDMI audio. Signed-off-by: Dylan Reid <dgreid@chromium.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-05-20 10:35:46 +08:00
hda@0,70030000 {
status = "okay";
};
ARM: tegra: use 2 address cells for Tegra124 DT Tegra124 can support 4GB of RAM. With that much RAM (plus some memory- mapped IO peripherals), more than 32-bits of physical address space is required. Hence, convert all Tegra124 DTs to use 2 DT cells for address space. (I think this was suggested by Olof Johansson, but I'm not 100% sure) Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-04 05:51:15 +08:00
sdhci@0,700b0400 {
ARM: tegra: add MMC controllers to Tegra124 DT Tegra124 has 4 MMC controllers just like previous versions of the SoC. Note that there are some non-backwards-compatible HW differences, and hence a new DT compatible value must be used to describe the HW. Also enable the relevant controllers in the Venice2 board DT. power-gpios property suggested by Thierry Reding. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com>
2013-11-01 07:23:05 +08:00
cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
ARM: tegra: add SD wp-gpios to Venice2 DT Venice2 can detect write-protect on the SD card. Add the required DT entries to allow this. Signed-off-by: Stephen Warren <swarren@nvidia.com> [swarren: fixed GPIO polarity per Thierry's testing] Tested-by: Thierry Reding <treding@nvidia.com>
2014-04-29 02:10:26 +08:00
wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
ARM: tegra: add MMC controllers to Tegra124 DT Tegra124 has 4 MMC controllers just like previous versions of the SoC. Note that there are some non-backwards-compatible HW differences, and hence a new DT compatible value must be used to describe the HW. Also enable the relevant controllers in the Venice2 board DT. power-gpios property suggested by Thierry Reding. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com>
2013-11-01 07:23:05 +08:00
status = "okay";
bus-width = <4>;
ARM: tegra: fix Venice2 SD card VQMMC supply VDDIO_SDMMC3 is the VQMMC (I/O) supply, not the VMMC (core) supply, for the SD slot on Venice2. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-04-17 07:08:39 +08:00
vqmmc-supply = <&vddio_sdmmc3>;
ARM: tegra: add MMC controllers to Tegra124 DT Tegra124 has 4 MMC controllers just like previous versions of the SoC. Note that there are some non-backwards-compatible HW differences, and hence a new DT compatible value must be used to describe the HW. Also enable the relevant controllers in the Venice2 board DT. power-gpios property suggested by Thierry Reding. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com>
2013-11-01 07:23:05 +08:00
};
ARM: tegra: use 2 address cells for Tegra124 DT Tegra124 can support 4GB of RAM. With that much RAM (plus some memory- mapped IO peripherals), more than 32-bits of physical address space is required. Hence, convert all Tegra124 DTs to use 2 DT cells for address space. (I think this was suggested by Olof Johansson, but I'm not 100% sure) Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-04 05:51:15 +08:00
sdhci@0,700b0600 {
ARM: tegra: add MMC controllers to Tegra124 DT Tegra124 has 4 MMC controllers just like previous versions of the SoC. Note that there are some non-backwards-compatible HW differences, and hence a new DT compatible value must be used to describe the HW. Also enable the relevant controllers in the Venice2 board DT. power-gpios property suggested by Thierry Reding. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com>
2013-11-01 07:23:05 +08:00
status = "okay";
bus-width = <8>;
};
ARM: tegra: use 2 address cells for Tegra124 DT Tegra124 can support 4GB of RAM. With that much RAM (plus some memory- mapped IO peripherals), more than 32-bits of physical address space is required. Hence, convert all Tegra124 DTs to use 2 DT cells for address space. (I think this was suggested by Olof Johansson, but I'm not 100% sure) Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-04 05:51:15 +08:00
ahub@0,70300000 {
i2s@0,70301100 {
ARM: tegra: add sound card to Venice2 DT Venice2 uses the MAX98090 audio CODEC, and supports built-in speakers, and a combo headphones/microphone jack. Add a top-level sound card node to represent this. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-04 08:26:12 +08:00
status = "okay";
};
};
ARM: tegra: use 2 address cells for Tegra124 DT Tegra124 can support 4GB of RAM. With that much RAM (plus some memory- mapped IO peripherals), more than 32-bits of physical address space is required. Hence, convert all Tegra124 DTs to use 2 DT cells for address space. (I think this was suggested by Olof Johansson, but I'm not 100% sure) Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-04 05:51:15 +08:00
usb@0,7d000000 {
ARM: tegra: Enable USB on Venice2 USB1 and USB3 are routed to two external connectors, while USB2 is used for the integrated webcam. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:26 +08:00
status = "okay";
};
ARM: tegra: use 2 address cells for Tegra124 DT Tegra124 can support 4GB of RAM. With that much RAM (plus some memory- mapped IO peripherals), more than 32-bits of physical address space is required. Hence, convert all Tegra124 DTs to use 2 DT cells for address space. (I think this was suggested by Olof Johansson, but I'm not 100% sure) Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-04 05:51:15 +08:00
usb-phy@0,7d000000 {
ARM: tegra: Enable USB on Venice2 USB1 and USB3 are routed to two external connectors, while USB2 is used for the integrated webcam. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:26 +08:00
status = "okay";
vbus-supply = <&vdd_usb1_vbus>;
};
ARM: tegra: use 2 address cells for Tegra124 DT Tegra124 can support 4GB of RAM. With that much RAM (plus some memory- mapped IO peripherals), more than 32-bits of physical address space is required. Hence, convert all Tegra124 DTs to use 2 DT cells for address space. (I think this was suggested by Olof Johansson, but I'm not 100% sure) Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-04 05:51:15 +08:00
usb@0,7d004000 {
ARM: tegra: Enable USB on Venice2 USB1 and USB3 are routed to two external connectors, while USB2 is used for the integrated webcam. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:26 +08:00
status = "okay";
};
ARM: tegra: use 2 address cells for Tegra124 DT Tegra124 can support 4GB of RAM. With that much RAM (plus some memory- mapped IO peripherals), more than 32-bits of physical address space is required. Hence, convert all Tegra124 DTs to use 2 DT cells for address space. (I think this was suggested by Olof Johansson, but I'm not 100% sure) Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-04 05:51:15 +08:00
usb-phy@0,7d004000 {
ARM: tegra: Enable USB on Venice2 USB1 and USB3 are routed to two external connectors, while USB2 is used for the integrated webcam. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:26 +08:00
status = "okay";
vbus-supply = <&vdd_run_cam>;
};
ARM: tegra: use 2 address cells for Tegra124 DT Tegra124 can support 4GB of RAM. With that much RAM (plus some memory- mapped IO peripherals), more than 32-bits of physical address space is required. Hence, convert all Tegra124 DTs to use 2 DT cells for address space. (I think this was suggested by Olof Johansson, but I'm not 100% sure) Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-04 05:51:15 +08:00
usb@0,7d008000 {
ARM: tegra: Enable USB on Venice2 USB1 and USB3 are routed to two external connectors, while USB2 is used for the integrated webcam. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:26 +08:00
status = "okay";
};
ARM: tegra: use 2 address cells for Tegra124 DT Tegra124 can support 4GB of RAM. With that much RAM (plus some memory- mapped IO peripherals), more than 32-bits of physical address space is required. Hence, convert all Tegra124 DTs to use 2 DT cells for address space. (I think this was suggested by Olof Johansson, but I'm not 100% sure) Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-04 05:51:15 +08:00
usb-phy@0,7d008000 {
ARM: tegra: Enable USB on Venice2 USB1 and USB3 are routed to two external connectors, while USB2 is used for the integrated webcam. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:26 +08:00
status = "okay";
vbus-supply = <&vdd_usb3_vbus>;
};
ARM: tegra: Enable eDP for Venice2 Venice2 has a 12.9" (2560x1700) panel connected to the eDP output of the Tegra124. The panel has an EDID to describe the video timings but needs a few extra nodes to get the backlight to come up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:24 +08:00
backlight: backlight {
compatible = "pwm-backlight";
enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
power-supply = <&vdd_led>;
pwms = <&pwm 1 1000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
};
ARM: tegra: add clock properties for devices of Tegra124 This patch adds clock properties for devices in the DT for basic support of Tegra124 SoC. Signed-off-by: Joseph Lo <josephl@nvidia.com> [swarren, added missing unit address to "clock" node] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-08 15:47:40 +08:00
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clock@0 {
compatible = "fixed-clock";
ARM: tegra: Fix whitespace around '=' Equal signs should always be preceded and followed by a single space in device tree files. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:27 +08:00
reg = <0>;
ARM: tegra: add clock properties for devices of Tegra124 This patch adds clock properties for devices in the DT for basic support of Tegra124 SoC. Signed-off-by: Joseph Lo <josephl@nvidia.com> [swarren, added missing unit address to "clock" node] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-08 15:47:40 +08:00
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
ARM: tegra: add sound card to Venice2 DT Venice2 uses the MAX98090 audio CODEC, and supports built-in speakers, and a combo headphones/microphone jack. Add a top-level sound card node to represent this. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-04 08:26:12 +08:00
ARM: tegra: Enable power key on Venice2 Contrary to the rest of the keyboard, which is connected to the ChromeOS embedded controller, the power key is hooked up to a GPIO. Add a device tree node to handle it. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-20 00:06:20 +08:00
gpio-keys {
compatible = "gpio-keys";
power {
label = "Power";
gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
debounce-interval = <10>;
gpio-key,wakeup;
};
};
ARM: tegra: Enable eDP for Venice2 Venice2 has a 12.9" (2560x1700) panel connected to the eDP output of the Tegra124. The panel has an EDID to describe the video timings but needs a few extra nodes to get the backlight to come up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:24 +08:00
panel: panel {
compatible = "lg,lp129qe", "simple-panel";
backlight = <&backlight>;
ddc-i2c-bus = <&dpaux>;
};
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
vdd_mux: regulator@0 {
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
compatible = "regulator-fixed";
reg = <0>;
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
regulator-name = "+VDD_MUX";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
regulator-always-on;
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
regulator-boot-on;
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
};
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
vdd_5v0_sys: regulator@1 {
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
compatible = "regulator-fixed";
reg = <1>;
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
regulator-name = "+5V_SYS";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
regulator-always-on;
regulator-boot-on;
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
vin-supply = <&vdd_mux>;
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
};
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
vdd_3v3_sys: regulator@2 {
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
compatible = "regulator-fixed";
reg = <2>;
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
regulator-name = "+3.3V_SYS";
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
regulator-always-on;
regulator-boot-on;
vin-supply = <&vdd_mux>;
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
};
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
vdd_3v3_run: regulator@3 {
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
compatible = "regulator-fixed";
reg = <3>;
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
regulator-name = "+3.3V_RUN";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
ARM: tegra: make Venice's +3.3V_RUN regulator always on This regulator supplies power to pretty much everything on the board, so it doesn't make sense to allow it to turn off. Mark it boot-on and always-on so it doesn't get turned off. Without this, I see issues with the eMMC device; it can't be correctly detected during boot. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-04-16 06:27:01 +08:00
regulator-always-on;
regulator-boot-on;
ARM: tegra: Rename as3722 node to pmic Device tree node name should reflect the kind of device rather than the specific name of the device. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:28 +08:00
gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
enable-active-high;
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
vin-supply = <&vdd_3v3_sys>;
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
};
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
vdd_3v3_hdmi: regulator@4 {
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
compatible = "regulator-fixed";
reg = <4>;
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
vin-supply = <&vdd_3v3_run>;
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
};
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
vdd_led: regulator@5 {
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
compatible = "regulator-fixed";
reg = <5>;
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
regulator-name = "+VDD_LED";
gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
enable-active-high;
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
vin-supply = <&vdd_mux>;
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
};
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
vdd_5v0_ts: regulator@6 {
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
compatible = "regulator-fixed";
reg = <6>;
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
regulator-name = "+5V_VDD_TS_SW";
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
enable-active-high;
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
vin-supply = <&vdd_5v0_sys>;
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
};
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
vdd_usb1_vbus: regulator@7 {
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
compatible = "regulator-fixed";
reg = <7>;
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
regulator-name = "+5V_USB_HS";
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
enable-active-high;
gpio-open-drain;
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
vin-supply = <&vdd_5v0_sys>;
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
};
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
vdd_usb3_vbus: regulator@8 {
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
compatible = "regulator-fixed";
reg = <8>;
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
regulator-name = "+5V_USB_SS";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
enable-active-high;
gpio-open-drain;
vin-supply = <&vdd_5v0_sys>;
};
vdd_3v3_panel: regulator@9 {
compatible = "regulator-fixed";
reg = <9>;
regulator-name = "+3.3V_PANEL";
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
ARM: tegra: Rename as3722 node to pmic Device tree node name should reflect the kind of device rather than the specific name of the device. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:28 +08:00
gpio = <&pmic 4 GPIO_ACTIVE_HIGH>;
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
enable-active-high;
vin-supply = <&vdd_3v3_run>;
};
vdd_3v3_lp0: regulator@10 {
compatible = "regulator-fixed";
reg = <10>;
regulator-name = "+3.3V_LP0";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
/*
* TODO: find a way to wire this up with the USB EHCI
* controllers so that it can be enabled on demand.
*/
regulator-always-on;
ARM: tegra: Rename as3722 node to pmic Device tree node name should reflect the kind of device rather than the specific name of the device. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:28 +08:00
gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
enable-active-high;
ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-03-01 00:40:20 +08:00
vin-supply = <&vdd_3v3_sys>;
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
};
ARM: tegra: venice2 - Enable HDMI Add HDMI +5V, VDD and PLL regulators and enable the DDC I2C controller. Enable the HDMI device, provide the power supplies as well as the DDC adapter and use the standard pin (PN7) for hotplug detection. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-04-25 23:44:46 +08:00
vdd_hdmi_pll: regulator@11 {
compatible = "regulator-fixed";
reg = <11>;
regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
vin-supply = <&vdd_1v05_run>;
};
vdd_5v0_hdmi: regulator@12 {
compatible = "regulator-fixed";
reg = <12>;
regulator-name = "+5V_HDMI_CON";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vdd_5v0_sys>;
};
ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-18 20:52:59 +08:00
};
ARM: tegra: add sound card to Venice2 DT Venice2 uses the MAX98090 audio CODEC, and supports built-in speakers, and a combo headphones/microphone jack. Add a top-level sound card node to represent this. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-04 08:26:12 +08:00
sound {
compatible = "nvidia,tegra-audio-max98090-venice2",
"nvidia,tegra-audio-max98090";
nvidia,model = "NVIDIA Tegra Venice2";
nvidia,audio-routing =
"Headphones", "HPR",
"Headphones", "HPL",
"Speakers", "SPKR",
"Speakers", "SPKL",
"Mic Jack", "MICBIAS",
"IN34", "Mic Jack";
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&acodec>;
clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
<&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA124_CLK_EXTERN1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
ARM: tegra: add Venice2 board support Add support for the Tegra124 based Venice2 reference board. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-08 12:50:06 +08:00
};
ARM: tegra: Use the cros-ec-keyboard fragment in venice2 Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-06-05 06:20:19 +08:00
#include "cros-ec-keyboard.dtsi"