2012-07-19 06:07:18 +08:00
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/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/dts-v1/;
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/include/ "socfpga.dtsi"
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/ {
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model = "Altera SOCFPGA Cyclone V";
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2013-02-12 07:30:30 +08:00
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compatible = "altr,socfpga-cyclone5", "altr,socfpga";
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2012-07-19 06:07:18 +08:00
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chosen {
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bootargs = "console=ttyS0,57600";
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};
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memory {
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name = "memory";
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device_type = "memory";
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2013-02-12 07:30:30 +08:00
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reg = <0x0 0x40000000>; /* 1GB */
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};
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2013-06-05 23:02:53 +08:00
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aliases {
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/* this allow the ethaddr uboot environmnet variable contents
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* to be added to the gmac1 device tree blob.
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*/
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ethernet0 = &gmac1;
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};
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2013-02-12 07:30:30 +08:00
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soc {
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2013-04-11 23:55:25 +08:00
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clkmgr@ffd04000 {
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clocks {
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osc1 {
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clock-frequency = <25000000>;
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};
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};
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};
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2013-06-05 23:02:53 +08:00
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ethernet@ff702000 {
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phy-mode = "rgmii";
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phy-addr = <0xffffffff>; /* probe for phy addr */
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status = "okay";
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};
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2013-02-12 07:30:30 +08:00
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timer0@ffc08000 {
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clock-frequency = <100000000>;
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};
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timer1@ffc09000 {
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clock-frequency = <100000000>;
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};
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timer2@ffd00000 {
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clock-frequency = <25000000>;
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};
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timer3@ffd01000 {
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clock-frequency = <25000000>;
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};
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serial0@ffc02000 {
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clock-frequency = <100000000>;
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};
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serial1@ffc03000 {
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clock-frequency = <100000000>;
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};
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2013-02-12 07:30:33 +08:00
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sysmgr@ffd08000 {
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cpu1-start-addr = <0xffd080c4>;
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};
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2012-07-19 06:07:18 +08:00
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};
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};
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