2012-06-14 01:01:28 +08:00
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/*
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* Device Tree file for Marvell Armada XP evaluation board
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* (DB-78460-BP)
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*
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2014-03-05 00:37:00 +08:00
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* Copyright (C) 2012-2014 Marvell
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2012-06-14 01:01:28 +08:00
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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2014-03-05 00:37:00 +08:00
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*
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* Note: this Device Tree assumes that the bootloader has remapped the
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* internal registers to 0xf1000000 (instead of the default
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* 0xd0000000). The 0xf1000000 is the default used by the recent,
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* DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
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* boards were delivered with an older version of the bootloader that
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* left internal registers mapped at 0xd0000000. If you are in this
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* situation, you should either update your bootloader (preferred
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* solution) or the below Device Tree should be adjusted.
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2012-06-14 01:01:28 +08:00
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*/
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/dts-v1/;
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2013-07-26 21:17:56 +08:00
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#include "armada-xp-mv78460.dtsi"
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2012-06-14 01:01:28 +08:00
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/ {
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model = "Marvell Armada XP Evaluation Board";
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2012-09-13 23:41:50 +08:00
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compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
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2012-06-14 01:01:28 +08:00
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chosen {
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bootargs = "console=ttyS0,115200 earlyprintk";
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};
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memory {
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device_type = "memory";
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2013-04-12 22:29:10 +08:00
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reg = <0 0x00000000 0 0x80000000>; /* 2 GB */
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2012-06-14 01:01:28 +08:00
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};
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soc {
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2014-03-05 00:37:00 +08:00
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ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
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2013-07-26 21:17:59 +08:00
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MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
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MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
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devbus-bootcs {
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status = "okay";
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/* Device Bus parameters are required */
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/* Read parameters */
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2014-04-14 23:29:20 +08:00
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devbus,bus-width = <16>;
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2013-07-26 21:17:59 +08:00
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devbus,turn-off-ps = <60000>;
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devbus,badr-skew-ps = <0>;
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devbus,acc-first-ps = <124000>;
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devbus,acc-next-ps = <248000>;
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devbus,rd-setup-ps = <0>;
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devbus,rd-hold-ps = <0>;
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/* Write parameters */
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devbus,sync-enable = <0>;
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devbus,wr-high-ps = <60000>;
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devbus,wr-low-ps = <60000>;
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devbus,ale-wr-ps = <60000>;
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/* NOR 16 MiB */
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nor@0 {
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compatible = "cfi-flash";
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reg = <0 0x1000000>;
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bank-width = <2>;
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};
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};
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2013-05-17 19:09:58 +08:00
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2013-07-26 21:18:00 +08:00
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pcie-controller {
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status = "okay";
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/*
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* All 6 slots are physically present as
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* standard PCIe slots on the board.
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*/
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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pcie@2,0 {
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/* Port 0, Lane 1 */
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status = "okay";
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};
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pcie@3,0 {
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/* Port 0, Lane 2 */
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status = "okay";
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};
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pcie@4,0 {
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/* Port 0, Lane 3 */
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status = "okay";
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};
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pcie@9,0 {
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/* Port 2, Lane 0 */
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status = "okay";
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};
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pcie@10,0 {
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/* Port 3, Lane 0 */
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status = "okay";
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};
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};
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2013-04-12 22:29:09 +08:00
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internal-regs {
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serial@12000 {
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status = "okay";
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2012-09-04 21:06:44 +08:00
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};
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2013-04-12 22:29:09 +08:00
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serial@12100 {
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status = "okay";
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2012-09-04 21:06:44 +08:00
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};
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2013-04-12 22:29:09 +08:00
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serial@12200 {
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status = "okay";
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2012-09-04 21:06:44 +08:00
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};
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2013-04-12 22:29:09 +08:00
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serial@12300 {
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status = "okay";
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2012-09-04 21:06:44 +08:00
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};
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2013-01-23 23:26:31 +08:00
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2013-04-12 22:29:09 +08:00
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sata@a0000 {
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nr-ports = <2>;
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status = "okay";
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};
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2013-01-23 23:26:31 +08:00
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2013-04-12 22:29:09 +08:00
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mdio {
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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2013-01-23 23:26:31 +08:00
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2013-04-12 22:29:09 +08:00
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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2013-02-06 04:54:54 +08:00
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2013-04-12 22:29:09 +08:00
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phy2: ethernet-phy@2 {
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reg = <25>;
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};
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2013-02-06 04:54:54 +08:00
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2013-04-12 22:29:09 +08:00
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phy3: ethernet-phy@3 {
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reg = <27>;
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};
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2013-02-06 04:54:54 +08:00
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};
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2013-04-10 05:06:36 +08:00
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2013-04-12 22:29:09 +08:00
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ethernet@70000 {
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status = "okay";
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phy = <&phy0>;
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phy-mode = "rgmii-id";
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};
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ethernet@74000 {
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status = "okay";
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phy = <&phy1>;
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phy-mode = "rgmii-id";
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};
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ethernet@30000 {
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status = "okay";
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phy = <&phy2>;
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phy-mode = "sgmii";
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};
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ethernet@34000 {
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status = "okay";
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phy = <&phy3>;
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phy-mode = "sgmii";
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};
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2013-04-10 05:06:36 +08:00
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2013-04-12 22:29:09 +08:00
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mvsdio@d4000 {
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pinctrl-0 = <&sdio_pins>;
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pinctrl-names = "default";
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2013-04-10 05:06:36 +08:00
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status = "okay";
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2013-04-12 22:29:09 +08:00
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/* No CD or WP GPIOs */
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2013-05-14 05:18:58 +08:00
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broken-cd;
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2013-04-10 05:06:36 +08:00
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};
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2013-04-12 22:29:09 +08:00
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usb@50000 {
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2013-04-10 05:06:36 +08:00
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status = "okay";
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};
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2013-04-12 22:29:09 +08:00
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usb@51000 {
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2013-04-10 05:06:36 +08:00
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status = "okay";
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};
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2013-04-12 22:29:09 +08:00
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usb@52000 {
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2013-04-10 05:06:36 +08:00
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status = "okay";
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};
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2013-04-12 22:29:09 +08:00
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spi0: spi@10600 {
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2013-04-10 05:06:36 +08:00
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status = "okay";
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2013-04-12 22:29:09 +08:00
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "m25p64";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <20000000>;
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};
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2013-04-10 05:06:36 +08:00
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};
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};
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2012-06-14 01:01:28 +08:00
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};
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};
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