2005-04-17 06:20:36 +08:00
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/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
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*/
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2006-01-02 17:14:23 +08:00
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/*
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2005-06-23 20:46:46 +08:00
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*
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2005-04-17 06:20:36 +08:00
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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2005-06-23 20:46:46 +08:00
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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2006-01-02 17:14:23 +08:00
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*/
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2005-04-17 06:20:36 +08:00
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2009-02-18 07:13:31 +08:00
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#include <linux/device.h>
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2014-06-12 23:35:47 +08:00
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#include <linux/acpi.h>
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2012-10-03 01:01:07 +08:00
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#include <drm/drmP.h>
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#include <drm/i915_drm.h>
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2005-04-17 06:20:36 +08:00
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#include "i915_drv.h"
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2012-07-02 22:51:02 +08:00
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#include "i915_trace.h"
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2010-09-11 16:19:14 +08:00
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#include "intel_drv.h"
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2005-04-17 06:20:36 +08:00
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DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 06:24:08 +08:00
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#include <linux/console.h>
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2011-08-30 23:04:30 +08:00
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#include <linux/module.h>
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2014-05-08 00:57:49 +08:00
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#include <linux/pm_runtime.h>
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2012-10-03 01:01:07 +08:00
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#include <drm/drm_crtc_helper.h>
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DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 06:24:08 +08:00
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2009-01-05 05:55:33 +08:00
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static struct drm_driver driver;
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drm/i915: Reorganize display pipe register accesses
RFCv2: Reorganize array indexing so that full offsets can be used as
is. It makes grepping for registers in i915_reg.h much easier. Also
move offset arrays to intel_device_info.
v1: Fixed offsets for VLV, proper eDP handling
v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros.
v3: Added EDP pipe comment, removed redundant offset arrays for
MSA_MISC and DDI_FUNC_CTL.
v4: Rename patch and report object size increase.
v5: Change location of commas, add PIPE_EDP into enum pipe
v6: Insert PIPE_EDP_OFFSET into pipe offset array
v7: Set I915_MAX_PIPES back to 3, change more registers accessors
to use the new macros, get rid of _PIPE_INC and add dev_priv
as a parameter where required by the new macros.
Upcoming hardware will not have the various display pipe register
ranges evenly spaced in memory. Change register address calculations
into array lookups.
Tested on SNB, VLV, IVB, Gen2 and HSW w/eDP.
I left the UMS cruft untouched.
Size differences:
text data bss dec hex filename
596431 4634 56 601121 92c21 i915.ko (new)
593199 4634 56 597889 91f81 i915.ko (old)
Signed-off-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-02-04 20:22:24 +08:00
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#define GEN_DEFAULT_PIPEOFFSETS \
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.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
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PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
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.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
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TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
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.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
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2014-04-28 19:00:42 +08:00
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#define GEN_CHV_PIPEOFFSETS \
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.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
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CHV_PIPE_C_OFFSET }, \
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.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
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CHV_TRANSCODER_C_OFFSET, }, \
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.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
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CHV_PALETTE_C_OFFSET }
|
drm/i915: Reorganize display pipe register accesses
RFCv2: Reorganize array indexing so that full offsets can be used as
is. It makes grepping for registers in i915_reg.h much easier. Also
move offset arrays to intel_device_info.
v1: Fixed offsets for VLV, proper eDP handling
v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros.
v3: Added EDP pipe comment, removed redundant offset arrays for
MSA_MISC and DDI_FUNC_CTL.
v4: Rename patch and report object size increase.
v5: Change location of commas, add PIPE_EDP into enum pipe
v6: Insert PIPE_EDP_OFFSET into pipe offset array
v7: Set I915_MAX_PIPES back to 3, change more registers accessors
to use the new macros, get rid of _PIPE_INC and add dev_priv
as a parameter where required by the new macros.
Upcoming hardware will not have the various display pipe register
ranges evenly spaced in memory. Change register address calculations
into array lookups.
Tested on SNB, VLV, IVB, Gen2 and HSW w/eDP.
I left the UMS cruft untouched.
Size differences:
text data bss dec hex filename
596431 4634 56 601121 92c21 i915.ko (new)
593199 4634 56 597889 91f81 i915.ko (old)
Signed-off-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-02-04 20:22:24 +08:00
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2014-04-09 18:28:53 +08:00
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#define CURSOR_OFFSETS \
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.cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
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#define IVB_CURSOR_OFFSETS \
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.cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
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2010-05-20 16:33:46 +08:00
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static const struct intel_device_info intel_i830_info = {
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2013-03-14 05:05:41 +08:00
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.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
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2010-08-12 16:42:51 +08:00
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.has_overlay = 1, .overlay_needs_physical = 1,
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2013-10-16 01:02:57 +08:00
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.ring_mask = RENDER_RING,
|
drm/i915: Reorganize display pipe register accesses
RFCv2: Reorganize array indexing so that full offsets can be used as
is. It makes grepping for registers in i915_reg.h much easier. Also
move offset arrays to intel_device_info.
v1: Fixed offsets for VLV, proper eDP handling
v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros.
v3: Added EDP pipe comment, removed redundant offset arrays for
MSA_MISC and DDI_FUNC_CTL.
v4: Rename patch and report object size increase.
v5: Change location of commas, add PIPE_EDP into enum pipe
v6: Insert PIPE_EDP_OFFSET into pipe offset array
v7: Set I915_MAX_PIPES back to 3, change more registers accessors
to use the new macros, get rid of _PIPE_INC and add dev_priv
as a parameter where required by the new macros.
Upcoming hardware will not have the various display pipe register
ranges evenly spaced in memory. Change register address calculations
into array lookups.
Tested on SNB, VLV, IVB, Gen2 and HSW w/eDP.
I left the UMS cruft untouched.
Size differences:
text data bss dec hex filename
596431 4634 56 601121 92c21 i915.ko (new)
593199 4634 56 597889 91f81 i915.ko (old)
Signed-off-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-02-04 20:22:24 +08:00
|
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GEN_DEFAULT_PIPEOFFSETS,
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2014-04-09 18:28:53 +08:00
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CURSOR_OFFSETS,
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2009-12-17 04:16:16 +08:00
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};
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2010-05-20 16:33:46 +08:00
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static const struct intel_device_info intel_845g_info = {
|
2013-03-14 05:05:41 +08:00
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.gen = 2, .num_pipes = 1,
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2010-08-12 16:42:51 +08:00
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.has_overlay = 1, .overlay_needs_physical = 1,
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2013-10-16 01:02:57 +08:00
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.ring_mask = RENDER_RING,
|
drm/i915: Reorganize display pipe register accesses
RFCv2: Reorganize array indexing so that full offsets can be used as
is. It makes grepping for registers in i915_reg.h much easier. Also
move offset arrays to intel_device_info.
v1: Fixed offsets for VLV, proper eDP handling
v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros.
v3: Added EDP pipe comment, removed redundant offset arrays for
MSA_MISC and DDI_FUNC_CTL.
v4: Rename patch and report object size increase.
v5: Change location of commas, add PIPE_EDP into enum pipe
v6: Insert PIPE_EDP_OFFSET into pipe offset array
v7: Set I915_MAX_PIPES back to 3, change more registers accessors
to use the new macros, get rid of _PIPE_INC and add dev_priv
as a parameter where required by the new macros.
Upcoming hardware will not have the various display pipe register
ranges evenly spaced in memory. Change register address calculations
into array lookups.
Tested on SNB, VLV, IVB, Gen2 and HSW w/eDP.
I left the UMS cruft untouched.
Size differences:
text data bss dec hex filename
596431 4634 56 601121 92c21 i915.ko (new)
593199 4634 56 597889 91f81 i915.ko (old)
Signed-off-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-02-04 20:22:24 +08:00
|
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GEN_DEFAULT_PIPEOFFSETS,
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2014-04-09 18:28:53 +08:00
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CURSOR_OFFSETS,
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2009-12-17 04:16:16 +08:00
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};
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2010-05-20 16:33:46 +08:00
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static const struct intel_device_info intel_i85x_info = {
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2013-03-14 05:05:41 +08:00
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.gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
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2010-04-16 02:03:30 +08:00
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.cursor_needs_physical = 1,
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2010-08-12 16:42:51 +08:00
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.has_overlay = 1, .overlay_needs_physical = 1,
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2013-11-28 23:30:02 +08:00
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.has_fbc = 1,
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2013-10-16 01:02:57 +08:00
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.ring_mask = RENDER_RING,
|
drm/i915: Reorganize display pipe register accesses
RFCv2: Reorganize array indexing so that full offsets can be used as
is. It makes grepping for registers in i915_reg.h much easier. Also
move offset arrays to intel_device_info.
v1: Fixed offsets for VLV, proper eDP handling
v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros.
v3: Added EDP pipe comment, removed redundant offset arrays for
MSA_MISC and DDI_FUNC_CTL.
v4: Rename patch and report object size increase.
v5: Change location of commas, add PIPE_EDP into enum pipe
v6: Insert PIPE_EDP_OFFSET into pipe offset array
v7: Set I915_MAX_PIPES back to 3, change more registers accessors
to use the new macros, get rid of _PIPE_INC and add dev_priv
as a parameter where required by the new macros.
Upcoming hardware will not have the various display pipe register
ranges evenly spaced in memory. Change register address calculations
into array lookups.
Tested on SNB, VLV, IVB, Gen2 and HSW w/eDP.
I left the UMS cruft untouched.
Size differences:
text data bss dec hex filename
596431 4634 56 601121 92c21 i915.ko (new)
593199 4634 56 597889 91f81 i915.ko (old)
Signed-off-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-02-04 20:22:24 +08:00
|
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GEN_DEFAULT_PIPEOFFSETS,
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2014-04-09 18:28:53 +08:00
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CURSOR_OFFSETS,
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2009-12-17 04:16:16 +08:00
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};
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2010-05-20 16:33:46 +08:00
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static const struct intel_device_info intel_i865g_info = {
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2013-03-14 05:05:41 +08:00
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.gen = 2, .num_pipes = 1,
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2010-08-12 16:42:51 +08:00
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.has_overlay = 1, .overlay_needs_physical = 1,
|
2013-10-16 01:02:57 +08:00
|
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.ring_mask = RENDER_RING,
|
drm/i915: Reorganize display pipe register accesses
RFCv2: Reorganize array indexing so that full offsets can be used as
is. It makes grepping for registers in i915_reg.h much easier. Also
move offset arrays to intel_device_info.
v1: Fixed offsets for VLV, proper eDP handling
v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros.
v3: Added EDP pipe comment, removed redundant offset arrays for
MSA_MISC and DDI_FUNC_CTL.
v4: Rename patch and report object size increase.
v5: Change location of commas, add PIPE_EDP into enum pipe
v6: Insert PIPE_EDP_OFFSET into pipe offset array
v7: Set I915_MAX_PIPES back to 3, change more registers accessors
to use the new macros, get rid of _PIPE_INC and add dev_priv
as a parameter where required by the new macros.
Upcoming hardware will not have the various display pipe register
ranges evenly spaced in memory. Change register address calculations
into array lookups.
Tested on SNB, VLV, IVB, Gen2 and HSW w/eDP.
I left the UMS cruft untouched.
Size differences:
text data bss dec hex filename
596431 4634 56 601121 92c21 i915.ko (new)
593199 4634 56 597889 91f81 i915.ko (old)
Signed-off-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-02-04 20:22:24 +08:00
|
|
|
GEN_DEFAULT_PIPEOFFSETS,
|
2014-04-09 18:28:53 +08:00
|
|
|
CURSOR_OFFSETS,
|
2009-12-17 04:16:16 +08:00
|
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};
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|
|
2010-05-20 16:33:46 +08:00
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static const struct intel_device_info intel_i915g_info = {
|
2013-03-14 05:05:41 +08:00
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.gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
|
2010-08-12 16:42:51 +08:00
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.has_overlay = 1, .overlay_needs_physical = 1,
|
2013-10-16 01:02:57 +08:00
|
|
|
.ring_mask = RENDER_RING,
|
drm/i915: Reorganize display pipe register accesses
RFCv2: Reorganize array indexing so that full offsets can be used as
is. It makes grepping for registers in i915_reg.h much easier. Also
move offset arrays to intel_device_info.
v1: Fixed offsets for VLV, proper eDP handling
v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros.
v3: Added EDP pipe comment, removed redundant offset arrays for
MSA_MISC and DDI_FUNC_CTL.
v4: Rename patch and report object size increase.
v5: Change location of commas, add PIPE_EDP into enum pipe
v6: Insert PIPE_EDP_OFFSET into pipe offset array
v7: Set I915_MAX_PIPES back to 3, change more registers accessors
to use the new macros, get rid of _PIPE_INC and add dev_priv
as a parameter where required by the new macros.
Upcoming hardware will not have the various display pipe register
ranges evenly spaced in memory. Change register address calculations
into array lookups.
Tested on SNB, VLV, IVB, Gen2 and HSW w/eDP.
I left the UMS cruft untouched.
Size differences:
text data bss dec hex filename
596431 4634 56 601121 92c21 i915.ko (new)
593199 4634 56 597889 91f81 i915.ko (old)
Signed-off-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-02-04 20:22:24 +08:00
|
|
|
GEN_DEFAULT_PIPEOFFSETS,
|
2014-04-09 18:28:53 +08:00
|
|
|
CURSOR_OFFSETS,
|
2009-12-17 04:16:16 +08:00
|
|
|
};
|
2010-05-20 16:33:46 +08:00
|
|
|
static const struct intel_device_info intel_i915gm_info = {
|
2013-03-14 05:05:41 +08:00
|
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.gen = 3, .is_mobile = 1, .num_pipes = 2,
|
2009-12-17 04:16:17 +08:00
|
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.cursor_needs_physical = 1,
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2010-08-12 16:42:51 +08:00
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.has_overlay = 1, .overlay_needs_physical = 1,
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2010-09-17 07:32:17 +08:00
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.supports_tv = 1,
|
2013-11-28 23:30:02 +08:00
|
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.has_fbc = 1,
|
2013-10-16 01:02:57 +08:00
|
|
|
.ring_mask = RENDER_RING,
|
drm/i915: Reorganize display pipe register accesses
RFCv2: Reorganize array indexing so that full offsets can be used as
is. It makes grepping for registers in i915_reg.h much easier. Also
move offset arrays to intel_device_info.
v1: Fixed offsets for VLV, proper eDP handling
v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros.
v3: Added EDP pipe comment, removed redundant offset arrays for
MSA_MISC and DDI_FUNC_CTL.
v4: Rename patch and report object size increase.
v5: Change location of commas, add PIPE_EDP into enum pipe
v6: Insert PIPE_EDP_OFFSET into pipe offset array
v7: Set I915_MAX_PIPES back to 3, change more registers accessors
to use the new macros, get rid of _PIPE_INC and add dev_priv
as a parameter where required by the new macros.
Upcoming hardware will not have the various display pipe register
ranges evenly spaced in memory. Change register address calculations
into array lookups.
Tested on SNB, VLV, IVB, Gen2 and HSW w/eDP.
I left the UMS cruft untouched.
Size differences:
text data bss dec hex filename
596431 4634 56 601121 92c21 i915.ko (new)
593199 4634 56 597889 91f81 i915.ko (old)
Signed-off-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-02-04 20:22:24 +08:00
|
|
|
GEN_DEFAULT_PIPEOFFSETS,
|
2014-04-09 18:28:53 +08:00
|
|
|
CURSOR_OFFSETS,
|
2009-12-17 04:16:16 +08:00
|
|
|
};
|
2010-05-20 16:33:46 +08:00
|
|
|
static const struct intel_device_info intel_i945g_info = {
|
2013-03-14 05:05:41 +08:00
|
|
|
.gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
|
2010-08-12 16:42:51 +08:00
|
|
|
.has_overlay = 1, .overlay_needs_physical = 1,
|
2013-10-16 01:02:57 +08:00
|
|
|
.ring_mask = RENDER_RING,
|
drm/i915: Reorganize display pipe register accesses
RFCv2: Reorganize array indexing so that full offsets can be used as
is. It makes grepping for registers in i915_reg.h much easier. Also
move offset arrays to intel_device_info.
v1: Fixed offsets for VLV, proper eDP handling
v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros.
v3: Added EDP pipe comment, removed redundant offset arrays for
MSA_MISC and DDI_FUNC_CTL.
v4: Rename patch and report object size increase.
v5: Change location of commas, add PIPE_EDP into enum pipe
v6: Insert PIPE_EDP_OFFSET into pipe offset array
v7: Set I915_MAX_PIPES back to 3, change more registers accessors
to use the new macros, get rid of _PIPE_INC and add dev_priv
as a parameter where required by the new macros.
Upcoming hardware will not have the various display pipe register
ranges evenly spaced in memory. Change register address calculations
into array lookups.
Tested on SNB, VLV, IVB, Gen2 and HSW w/eDP.
I left the UMS cruft untouched.
Size differences:
text data bss dec hex filename
596431 4634 56 601121 92c21 i915.ko (new)
593199 4634 56 597889 91f81 i915.ko (old)
Signed-off-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-02-04 20:22:24 +08:00
|
|
|
GEN_DEFAULT_PIPEOFFSETS,
|
2014-04-09 18:28:53 +08:00
|
|
|
CURSOR_OFFSETS,
|
2009-12-17 04:16:16 +08:00
|
|
|
};
|
2010-05-20 16:33:46 +08:00
|
|
|
static const struct intel_device_info intel_i945gm_info = {
|
2013-03-14 05:05:41 +08:00
|
|
|
.gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
|
2009-12-17 04:16:17 +08:00
|
|
|
.has_hotplug = 1, .cursor_needs_physical = 1,
|
2010-08-12 16:42:51 +08:00
|
|
|
.has_overlay = 1, .overlay_needs_physical = 1,
|
2010-09-17 07:32:17 +08:00
|
|
|
.supports_tv = 1,
|
2013-11-28 23:30:02 +08:00
|
|
|
.has_fbc = 1,
|
2013-10-16 01:02:57 +08:00
|
|
|
.ring_mask = RENDER_RING,
|
drm/i915: Reorganize display pipe register accesses
RFCv2: Reorganize array indexing so that full offsets can be used as
is. It makes grepping for registers in i915_reg.h much easier. Also
move offset arrays to intel_device_info.
v1: Fixed offsets for VLV, proper eDP handling
v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros.
v3: Added EDP pipe comment, removed redundant offset arrays for
MSA_MISC and DDI_FUNC_CTL.
v4: Rename patch and report object size increase.
v5: Change location of commas, add PIPE_EDP into enum pipe
v6: Insert PIPE_EDP_OFFSET into pipe offset array
v7: Set I915_MAX_PIPES back to 3, change more registers accessors
to use the new macros, get rid of _PIPE_INC and add dev_priv
as a parameter where required by the new macros.
Upcoming hardware will not have the various display pipe register
ranges evenly spaced in memory. Change register address calculations
into array lookups.
Tested on SNB, VLV, IVB, Gen2 and HSW w/eDP.
I left the UMS cruft untouched.
Size differences:
text data bss dec hex filename
596431 4634 56 601121 92c21 i915.ko (new)
593199 4634 56 597889 91f81 i915.ko (old)
Signed-off-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-02-04 20:22:24 +08:00
|
|
|
GEN_DEFAULT_PIPEOFFSETS,
|
2014-04-09 18:28:53 +08:00
|
|
|
CURSOR_OFFSETS,
|
2009-12-17 04:16:16 +08:00
|
|
|
};
|
|
|
|
|
2010-05-20 16:33:46 +08:00
|
|
|
static const struct intel_device_info intel_i965g_info = {
|
2013-03-14 05:05:41 +08:00
|
|
|
.gen = 4, .is_broadwater = 1, .num_pipes = 2,
|
2010-08-11 16:59:24 +08:00
|
|
|
.has_hotplug = 1,
|
2010-08-12 16:42:51 +08:00
|
|
|
.has_overlay = 1,
|
2013-10-16 01:02:57 +08:00
|
|
|
.ring_mask = RENDER_RING,
|
drm/i915: Reorganize display pipe register accesses
RFCv2: Reorganize array indexing so that full offsets can be used as
is. It makes grepping for registers in i915_reg.h much easier. Also
move offset arrays to intel_device_info.
v1: Fixed offsets for VLV, proper eDP handling
v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros.
v3: Added EDP pipe comment, removed redundant offset arrays for
MSA_MISC and DDI_FUNC_CTL.
v4: Rename patch and report object size increase.
v5: Change location of commas, add PIPE_EDP into enum pipe
v6: Insert PIPE_EDP_OFFSET into pipe offset array
v7: Set I915_MAX_PIPES back to 3, change more registers accessors
to use the new macros, get rid of _PIPE_INC and add dev_priv
as a parameter where required by the new macros.
Upcoming hardware will not have the various display pipe register
ranges evenly spaced in memory. Change register address calculations
into array lookups.
Tested on SNB, VLV, IVB, Gen2 and HSW w/eDP.
I left the UMS cruft untouched.
Size differences:
text data bss dec hex filename
596431 4634 56 601121 92c21 i915.ko (new)
593199 4634 56 597889 91f81 i915.ko (old)
Signed-off-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-02-04 20:22:24 +08:00
|
|
|
GEN_DEFAULT_PIPEOFFSETS,
|
2014-04-09 18:28:53 +08:00
|
|
|
CURSOR_OFFSETS,
|
2009-12-17 04:16:16 +08:00
|
|
|
};
|
|
|
|
|
2010-05-20 16:33:46 +08:00
|
|
|
static const struct intel_device_info intel_i965gm_info = {
|
2013-03-14 05:05:41 +08:00
|
|
|
.gen = 4, .is_crestline = 1, .num_pipes = 2,
|
2010-12-06 00:49:51 +08:00
|
|
|
.is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
|
2010-08-12 16:42:51 +08:00
|
|
|
.has_overlay = 1,
|
2010-09-17 07:32:17 +08:00
|
|
|
.supports_tv = 1,
|
2013-10-16 01:02:57 +08:00
|
|
|
.ring_mask = RENDER_RING,
|
drm/i915: Reorganize display pipe register accesses
RFCv2: Reorganize array indexing so that full offsets can be used as
is. It makes grepping for registers in i915_reg.h much easier. Also
move offset arrays to intel_device_info.
v1: Fixed offsets for VLV, proper eDP handling
v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros.
v3: Added EDP pipe comment, removed redundant offset arrays for
MSA_MISC and DDI_FUNC_CTL.
v4: Rename patch and report object size increase.
v5: Change location of commas, add PIPE_EDP into enum pipe
v6: Insert PIPE_EDP_OFFSET into pipe offset array
v7: Set I915_MAX_PIPES back to 3, change more registers accessors
to use the new macros, get rid of _PIPE_INC and add dev_priv
as a parameter where required by the new macros.
Upcoming hardware will not have the various display pipe register
ranges evenly spaced in memory. Change register address calculations
into array lookups.
Tested on SNB, VLV, IVB, Gen2 and HSW w/eDP.
I left the UMS cruft untouched.
Size differences:
text data bss dec hex filename
596431 4634 56 601121 92c21 i915.ko (new)
593199 4634 56 597889 91f81 i915.ko (old)
Signed-off-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-02-04 20:22:24 +08:00
|
|
|
GEN_DEFAULT_PIPEOFFSETS,
|
2014-04-09 18:28:53 +08:00
|
|
|
CURSOR_OFFSETS,
|
2009-12-17 04:16:16 +08:00
|
|
|
};
|
|
|
|
|
2010-05-20 16:33:46 +08:00
|
|
|
static const struct intel_device_info intel_g33_info = {
|
2013-03-14 05:05:41 +08:00
|
|
|
.gen = 3, .is_g33 = 1, .num_pipes = 2,
|
2010-08-11 16:59:24 +08:00
|
|
|
.need_gfx_hws = 1, .has_hotplug = 1,
|
2010-08-12 16:42:51 +08:00
|
|
|
.has_overlay = 1,
|
2013-10-16 01:02:57 +08:00
|
|
|
.ring_mask = RENDER_RING,
|
drm/i915: Reorganize display pipe register accesses
RFCv2: Reorganize array indexing so that full offsets can be used as
is. It makes grepping for registers in i915_reg.h much easier. Also
move offset arrays to intel_device_info.
v1: Fixed offsets for VLV, proper eDP handling
v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros.
v3: Added EDP pipe comment, removed redundant offset arrays for
MSA_MISC and DDI_FUNC_CTL.
v4: Rename patch and report object size increase.
v5: Change location of commas, add PIPE_EDP into enum pipe
v6: Insert PIPE_EDP_OFFSET into pipe offset array
v7: Set I915_MAX_PIPES back to 3, change more registers accessors
to use the new macros, get rid of _PIPE_INC and add dev_priv
as a parameter where required by the new macros.
Upcoming hardware will not have the various display pipe register
ranges evenly spaced in memory. Change register address calculations
into array lookups.
Tested on SNB, VLV, IVB, Gen2 and HSW w/eDP.
I left the UMS cruft untouched.
Size differences:
text data bss dec hex filename
596431 4634 56 601121 92c21 i915.ko (new)
593199 4634 56 597889 91f81 i915.ko (old)
Signed-off-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-02-04 20:22:24 +08:00
|
|
|
GEN_DEFAULT_PIPEOFFSETS,
|
2014-04-09 18:28:53 +08:00
|
|
|
CURSOR_OFFSETS,
|
2009-12-17 04:16:16 +08:00
|
|
|
};
|
|
|
|
|
2010-05-20 16:33:46 +08:00
|
|
|
static const struct intel_device_info intel_g45_info = {
|
2013-03-14 05:05:41 +08:00
|
|
|
.gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
|
2010-08-11 16:59:24 +08:00
|
|
|
.has_pipe_cxsr = 1, .has_hotplug = 1,
|
2013-10-16 01:02:57 +08:00
|
|
|
.ring_mask = RENDER_RING | BSD_RING,
|
drm/i915: Reorganize display pipe register accesses
RFCv2: Reorganize array indexing so that full offsets can be used as
is. It makes grepping for registers in i915_reg.h much easier. Also
move offset arrays to intel_device_info.
v1: Fixed offsets for VLV, proper eDP handling
v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros.
v3: Added EDP pipe comment, removed redundant offset arrays for
MSA_MISC and DDI_FUNC_CTL.
v4: Rename patch and report object size increase.
v5: Change location of commas, add PIPE_EDP into enum pipe
v6: Insert PIPE_EDP_OFFSET into pipe offset array
v7: Set I915_MAX_PIPES back to 3, change more registers accessors
to use the new macros, get rid of _PIPE_INC and add dev_priv
as a parameter where required by the new macros.
Upcoming hardware will not have the various display pipe register
ranges evenly spaced in memory. Change register address calculations
into array lookups.
Tested on SNB, VLV, IVB, Gen2 and HSW w/eDP.
I left the UMS cruft untouched.
Size differences:
text data bss dec hex filename
596431 4634 56 601121 92c21 i915.ko (new)
593199 4634 56 597889 91f81 i915.ko (old)
Signed-off-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-02-04 20:22:24 +08:00
|
|
|
GEN_DEFAULT_PIPEOFFSETS,
|
2014-04-09 18:28:53 +08:00
|
|
|
CURSOR_OFFSETS,
|
2009-12-17 04:16:16 +08:00
|
|
|
};
|
|
|
|
|
2010-05-20 16:33:46 +08:00
|
|
|
static const struct intel_device_info intel_gm45_info = {
|
2013-03-14 05:05:41 +08:00
|
|
|
.gen = 4, .is_g4x = 1, .num_pipes = 2,
|
2010-12-06 00:49:51 +08:00
|
|
|
.is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
|
2010-08-11 16:59:24 +08:00
|
|
|
.has_pipe_cxsr = 1, .has_hotplug = 1,
|
2010-09-17 07:32:17 +08:00
|
|
|
.supports_tv = 1,
|
2013-10-16 01:02:57 +08:00
|
|
|
.ring_mask = RENDER_RING | BSD_RING,
|
drm/i915: Reorganize display pipe register accesses
RFCv2: Reorganize array indexing so that full offsets can be used as
is. It makes grepping for registers in i915_reg.h much easier. Also
move offset arrays to intel_device_info.
v1: Fixed offsets for VLV, proper eDP handling
v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros.
v3: Added EDP pipe comment, removed redundant offset arrays for
MSA_MISC and DDI_FUNC_CTL.
v4: Rename patch and report object size increase.
v5: Change location of commas, add PIPE_EDP into enum pipe
v6: Insert PIPE_EDP_OFFSET into pipe offset array
v7: Set I915_MAX_PIPES back to 3, change more registers accessors
to use the new macros, get rid of _PIPE_INC and add dev_priv
as a parameter where required by the new macros.
Upcoming hardware will not have the various display pipe register
ranges evenly spaced in memory. Change register address calculations
into array lookups.
Tested on SNB, VLV, IVB, Gen2 and HSW w/eDP.
I left the UMS cruft untouched.
Size differences:
text data bss dec hex filename
596431 4634 56 601121 92c21 i915.ko (new)
593199 4634 56 597889 91f81 i915.ko (old)
Signed-off-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-02-04 20:22:24 +08:00
|
|
|
GEN_DEFAULT_PIPEOFFSETS,
|
2014-04-09 18:28:53 +08:00
|
|
|
CURSOR_OFFSETS,
|
2009-12-17 04:16:16 +08:00
|
|
|
};
|
|
|
|
|
2010-05-20 16:33:46 +08:00
|
|
|
static const struct intel_device_info intel_pineview_info = {
|
2013-03-14 05:05:41 +08:00
|
|
|
.gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
|
2010-08-11 16:59:24 +08:00
|
|
|
.need_gfx_hws = 1, .has_hotplug = 1,
|
2010-08-12 16:42:51 +08:00
|
|
|
.has_overlay = 1,
|
drm/i915: Reorganize display pipe register accesses
RFCv2: Reorganize array indexing so that full offsets can be used as
is. It makes grepping for registers in i915_reg.h much easier. Also
move offset arrays to intel_device_info.
v1: Fixed offsets for VLV, proper eDP handling
v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros.
v3: Added EDP pipe comment, removed redundant offset arrays for
MSA_MISC and DDI_FUNC_CTL.
v4: Rename patch and report object size increase.
v5: Change location of commas, add PIPE_EDP into enum pipe
v6: Insert PIPE_EDP_OFFSET into pipe offset array
v7: Set I915_MAX_PIPES back to 3, change more registers accessors
to use the new macros, get rid of _PIPE_INC and add dev_priv
as a parameter where required by the new macros.
Upcoming hardware will not have the various display pipe register
ranges evenly spaced in memory. Change register address calculations
into array lookups.
Tested on SNB, VLV, IVB, Gen2 and HSW w/eDP.
I left the UMS cruft untouched.
Size differences:
text data bss dec hex filename
596431 4634 56 601121 92c21 i915.ko (new)
593199 4634 56 597889 91f81 i915.ko (old)
Signed-off-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-02-04 20:22:24 +08:00
|
|
|
GEN_DEFAULT_PIPEOFFSETS,
|
2014-04-09 18:28:53 +08:00
|
|
|
CURSOR_OFFSETS,
|
2009-12-17 04:16:16 +08:00
|
|
|
};
|
|
|
|
|
2010-05-20 16:33:46 +08:00
|
|
|
static const struct intel_device_info intel_ironlake_d_info = {
|
2013-03-14 05:05:41 +08:00
|
|
|
.gen = 5, .num_pipes = 2,
|
2012-01-05 19:34:29 +08:00
|
|
|
.need_gfx_hws = 1, .has_hotplug = 1,
|
2013-10-16 01:02:57 +08:00
|
|
|
.ring_mask = RENDER_RING | BSD_RING,
|
drm/i915: Reorganize display pipe register accesses
RFCv2: Reorganize array indexing so that full offsets can be used as
is. It makes grepping for registers in i915_reg.h much easier. Also
move offset arrays to intel_device_info.
v1: Fixed offsets for VLV, proper eDP handling
v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros.
v3: Added EDP pipe comment, removed redundant offset arrays for
MSA_MISC and DDI_FUNC_CTL.
v4: Rename patch and report object size increase.
v5: Change location of commas, add PIPE_EDP into enum pipe
v6: Insert PIPE_EDP_OFFSET into pipe offset array
v7: Set I915_MAX_PIPES back to 3, change more registers accessors
to use the new macros, get rid of _PIPE_INC and add dev_priv
as a parameter where required by the new macros.
Upcoming hardware will not have the various display pipe register
ranges evenly spaced in memory. Change register address calculations
into array lookups.
Tested on SNB, VLV, IVB, Gen2 and HSW w/eDP.
I left the UMS cruft untouched.
Size differences:
text data bss dec hex filename
596431 4634 56 601121 92c21 i915.ko (new)
593199 4634 56 597889 91f81 i915.ko (old)
Signed-off-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-02-04 20:22:24 +08:00
|
|
|
GEN_DEFAULT_PIPEOFFSETS,
|
2014-04-09 18:28:53 +08:00
|
|
|
CURSOR_OFFSETS,
|
2009-12-17 04:16:16 +08:00
|
|
|
};
|
|
|
|
|
2010-05-20 16:33:46 +08:00
|
|
|
static const struct intel_device_info intel_ironlake_m_info = {
|
2013-03-14 05:05:41 +08:00
|
|
|
.gen = 5, .is_mobile = 1, .num_pipes = 2,
|
2010-12-06 00:49:51 +08:00
|
|
|
.need_gfx_hws = 1, .has_hotplug = 1,
|
2011-05-06 06:24:21 +08:00
|
|
|
.has_fbc = 1,
|
2013-10-16 01:02:57 +08:00
|
|
|
.ring_mask = RENDER_RING | BSD_RING,
|
drm/i915: Reorganize display pipe register accesses
RFCv2: Reorganize array indexing so that full offsets can be used as
is. It makes grepping for registers in i915_reg.h much easier. Also
move offset arrays to intel_device_info.
v1: Fixed offsets for VLV, proper eDP handling
v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros.
v3: Added EDP pipe comment, removed redundant offset arrays for
MSA_MISC and DDI_FUNC_CTL.
v4: Rename patch and report object size increase.
v5: Change location of commas, add PIPE_EDP into enum pipe
v6: Insert PIPE_EDP_OFFSET into pipe offset array
v7: Set I915_MAX_PIPES back to 3, change more registers accessors
to use the new macros, get rid of _PIPE_INC and add dev_priv
as a parameter where required by the new macros.
Upcoming hardware will not have the various display pipe register
ranges evenly spaced in memory. Change register address calculations
into array lookups.
Tested on SNB, VLV, IVB, Gen2 and HSW w/eDP.
I left the UMS cruft untouched.
Size differences:
text data bss dec hex filename
596431 4634 56 601121 92c21 i915.ko (new)
593199 4634 56 597889 91f81 i915.ko (old)
Signed-off-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-02-04 20:22:24 +08:00
|
|
|
GEN_DEFAULT_PIPEOFFSETS,
|
2014-04-09 18:28:53 +08:00
|
|
|
CURSOR_OFFSETS,
|
2009-12-17 04:16:16 +08:00
|
|
|
};
|
|
|
|
|
2010-05-20 16:33:46 +08:00
|
|
|
static const struct intel_device_info intel_sandybridge_d_info = {
|
2013-03-14 05:05:41 +08:00
|
|
|
.gen = 6, .num_pipes = 2,
|
2010-08-11 16:59:24 +08:00
|
|
|
.need_gfx_hws = 1, .has_hotplug = 1,
|
2013-11-07 05:02:24 +08:00
|
|
|
.has_fbc = 1,
|
2013-10-16 01:02:57 +08:00
|
|
|
.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
|
2012-01-18 00:43:53 +08:00
|
|
|
.has_llc = 1,
|
drm/i915: Reorganize display pipe register accesses
RFCv2: Reorganize array indexing so that full offsets can be used as
is. It makes grepping for registers in i915_reg.h much easier. Also
move offset arrays to intel_device_info.
v1: Fixed offsets for VLV, proper eDP handling
v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros.
v3: Added EDP pipe comment, removed redundant offset arrays for
MSA_MISC and DDI_FUNC_CTL.
v4: Rename patch and report object size increase.
v5: Change location of commas, add PIPE_EDP into enum pipe
v6: Insert PIPE_EDP_OFFSET into pipe offset array
v7: Set I915_MAX_PIPES back to 3, change more registers accessors
to use the new macros, get rid of _PIPE_INC and add dev_priv
as a parameter where required by the new macros.
Upcoming hardware will not have the various display pipe register
ranges evenly spaced in memory. Change register address calculations
into array lookups.
Tested on SNB, VLV, IVB, Gen2 and HSW w/eDP.
I left the UMS cruft untouched.
Size differences:
text data bss dec hex filename
596431 4634 56 601121 92c21 i915.ko (new)
593199 4634 56 597889 91f81 i915.ko (old)
Signed-off-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-02-04 20:22:24 +08:00
|
|
|
GEN_DEFAULT_PIPEOFFSETS,
|
2014-04-09 18:28:53 +08:00
|
|
|
CURSOR_OFFSETS,
|
2009-11-03 04:08:22 +08:00
|
|
|
};
|
|
|
|
|
2010-05-20 16:33:46 +08:00
|
|
|
static const struct intel_device_info intel_sandybridge_m_info = {
|
2013-03-14 05:05:41 +08:00
|
|
|
.gen = 6, .is_mobile = 1, .num_pipes = 2,
|
2010-08-11 16:59:24 +08:00
|
|
|
.need_gfx_hws = 1, .has_hotplug = 1,
|
2010-12-15 15:42:32 +08:00
|
|
|
.has_fbc = 1,
|
2013-10-16 01:02:57 +08:00
|
|
|
.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
|
2012-01-18 00:43:53 +08:00
|
|
|
.has_llc = 1,
|
drm/i915: Reorganize display pipe register accesses
RFCv2: Reorganize array indexing so that full offsets can be used as
is. It makes grepping for registers in i915_reg.h much easier. Also
move offset arrays to intel_device_info.
v1: Fixed offsets for VLV, proper eDP handling
v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros.
v3: Added EDP pipe comment, removed redundant offset arrays for
MSA_MISC and DDI_FUNC_CTL.
v4: Rename patch and report object size increase.
v5: Change location of commas, add PIPE_EDP into enum pipe
v6: Insert PIPE_EDP_OFFSET into pipe offset array
v7: Set I915_MAX_PIPES back to 3, change more registers accessors
to use the new macros, get rid of _PIPE_INC and add dev_priv
as a parameter where required by the new macros.
Upcoming hardware will not have the various display pipe register
ranges evenly spaced in memory. Change register address calculations
into array lookups.
Tested on SNB, VLV, IVB, Gen2 and HSW w/eDP.
I left the UMS cruft untouched.
Size differences:
text data bss dec hex filename
596431 4634 56 601121 92c21 i915.ko (new)
593199 4634 56 597889 91f81 i915.ko (old)
Signed-off-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-02-04 20:22:24 +08:00
|
|
|
GEN_DEFAULT_PIPEOFFSETS,
|
2014-04-09 18:28:53 +08:00
|
|
|
CURSOR_OFFSETS,
|
2010-01-08 07:08:18 +08:00
|
|
|
};
|
|
|
|
|
2013-03-16 02:17:54 +08:00
|
|
|
#define GEN7_FEATURES \
|
|
|
|
.gen = 7, .num_pipes = 3, \
|
|
|
|
.need_gfx_hws = 1, .has_hotplug = 1, \
|
2013-11-07 05:02:24 +08:00
|
|
|
.has_fbc = 1, \
|
2013-10-16 01:02:57 +08:00
|
|
|
.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
|
2013-10-06 08:57:11 +08:00
|
|
|
.has_llc = 1
|
2013-03-16 02:17:54 +08:00
|
|
|
|
2011-04-29 05:32:07 +08:00
|
|
|
static const struct intel_device_info intel_ivybridge_d_info = {
|
2013-03-16 02:17:54 +08:00
|
|
|
GEN7_FEATURES,
|
|
|
|
.is_ivybridge = 1,
|
drm/i915: Reorganize display pipe register accesses
RFCv2: Reorganize array indexing so that full offsets can be used as
is. It makes grepping for registers in i915_reg.h much easier. Also
move offset arrays to intel_device_info.
v1: Fixed offsets for VLV, proper eDP handling
v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros.
v3: Added EDP pipe comment, removed redundant offset arrays for
MSA_MISC and DDI_FUNC_CTL.
v4: Rename patch and report object size increase.
v5: Change location of commas, add PIPE_EDP into enum pipe
v6: Insert PIPE_EDP_OFFSET into pipe offset array
v7: Set I915_MAX_PIPES back to 3, change more registers accessors
to use the new macros, get rid of _PIPE_INC and add dev_priv
as a parameter where required by the new macros.
Upcoming hardware will not have the various display pipe register
ranges evenly spaced in memory. Change register address calculations
into array lookups.
Tested on SNB, VLV, IVB, Gen2 and HSW w/eDP.
I left the UMS cruft untouched.
Size differences:
text data bss dec hex filename
596431 4634 56 601121 92c21 i915.ko (new)
593199 4634 56 597889 91f81 i915.ko (old)
Signed-off-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-02-04 20:22:24 +08:00
|
|
|
GEN_DEFAULT_PIPEOFFSETS,
|
2014-04-09 18:28:53 +08:00
|
|
|
IVB_CURSOR_OFFSETS,
|
2011-04-29 05:32:07 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct intel_device_info intel_ivybridge_m_info = {
|
2013-03-16 02:17:54 +08:00
|
|
|
GEN7_FEATURES,
|
|
|
|
.is_ivybridge = 1,
|
|
|
|
.is_mobile = 1,
|
drm/i915: Reorganize display pipe register accesses
RFCv2: Reorganize array indexing so that full offsets can be used as
is. It makes grepping for registers in i915_reg.h much easier. Also
move offset arrays to intel_device_info.
v1: Fixed offsets for VLV, proper eDP handling
v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros.
v3: Added EDP pipe comment, removed redundant offset arrays for
MSA_MISC and DDI_FUNC_CTL.
v4: Rename patch and report object size increase.
v5: Change location of commas, add PIPE_EDP into enum pipe
v6: Insert PIPE_EDP_OFFSET into pipe offset array
v7: Set I915_MAX_PIPES back to 3, change more registers accessors
to use the new macros, get rid of _PIPE_INC and add dev_priv
as a parameter where required by the new macros.
Upcoming hardware will not have the various display pipe register
ranges evenly spaced in memory. Change register address calculations
into array lookups.
Tested on SNB, VLV, IVB, Gen2 and HSW w/eDP.
I left the UMS cruft untouched.
Size differences:
text data bss dec hex filename
596431 4634 56 601121 92c21 i915.ko (new)
593199 4634 56 597889 91f81 i915.ko (old)
Signed-off-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-02-04 20:22:24 +08:00
|
|
|
GEN_DEFAULT_PIPEOFFSETS,
|
2014-04-09 18:28:53 +08:00
|
|
|
IVB_CURSOR_OFFSETS,
|
2011-04-29 05:32:07 +08:00
|
|
|
};
|
|
|
|
|
2013-04-06 04:12:45 +08:00
|
|
|
static const struct intel_device_info intel_ivybridge_q_info = {
|
|
|
|
GEN7_FEATURES,
|
|
|
|
.is_ivybridge = 1,
|
|
|
|
.num_pipes = 0, /* legal, last one wins */
|
drm/i915: Reorganize display pipe register accesses
RFCv2: Reorganize array indexing so that full offsets can be used as
is. It makes grepping for registers in i915_reg.h much easier. Also
move offset arrays to intel_device_info.
v1: Fixed offsets for VLV, proper eDP handling
v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros.
v3: Added EDP pipe comment, removed redundant offset arrays for
MSA_MISC and DDI_FUNC_CTL.
v4: Rename patch and report object size increase.
v5: Change location of commas, add PIPE_EDP into enum pipe
v6: Insert PIPE_EDP_OFFSET into pipe offset array
v7: Set I915_MAX_PIPES back to 3, change more registers accessors
to use the new macros, get rid of _PIPE_INC and add dev_priv
as a parameter where required by the new macros.
Upcoming hardware will not have the various display pipe register
ranges evenly spaced in memory. Change register address calculations
into array lookups.
Tested on SNB, VLV, IVB, Gen2 and HSW w/eDP.
I left the UMS cruft untouched.
Size differences:
text data bss dec hex filename
596431 4634 56 601121 92c21 i915.ko (new)
593199 4634 56 597889 91f81 i915.ko (old)
Signed-off-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-02-04 20:22:24 +08:00
|
|
|
GEN_DEFAULT_PIPEOFFSETS,
|
2014-04-09 18:28:53 +08:00
|
|
|
IVB_CURSOR_OFFSETS,
|
2013-04-06 04:12:45 +08:00
|
|
|
};
|
|
|
|
|
2012-03-29 04:39:21 +08:00
|
|
|
static const struct intel_device_info intel_valleyview_m_info = {
|
2013-03-16 02:17:54 +08:00
|
|
|
GEN7_FEATURES,
|
|
|
|
.is_mobile = 1,
|
|
|
|
.num_pipes = 2,
|
2012-03-29 04:39:21 +08:00
|
|
|
.is_valleyview = 1,
|
2013-01-24 21:29:56 +08:00
|
|
|
.display_mmio_offset = VLV_DISPLAY_BASE,
|
2013-11-07 05:02:24 +08:00
|
|
|
.has_fbc = 0, /* legal, last one wins */
|
2013-04-16 12:48:03 +08:00
|
|
|
.has_llc = 0, /* legal, last one wins */
|
drm/i915: Reorganize display pipe register accesses
RFCv2: Reorganize array indexing so that full offsets can be used as
is. It makes grepping for registers in i915_reg.h much easier. Also
move offset arrays to intel_device_info.
v1: Fixed offsets for VLV, proper eDP handling
v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros.
v3: Added EDP pipe comment, removed redundant offset arrays for
MSA_MISC and DDI_FUNC_CTL.
v4: Rename patch and report object size increase.
v5: Change location of commas, add PIPE_EDP into enum pipe
v6: Insert PIPE_EDP_OFFSET into pipe offset array
v7: Set I915_MAX_PIPES back to 3, change more registers accessors
to use the new macros, get rid of _PIPE_INC and add dev_priv
as a parameter where required by the new macros.
Upcoming hardware will not have the various display pipe register
ranges evenly spaced in memory. Change register address calculations
into array lookups.
Tested on SNB, VLV, IVB, Gen2 and HSW w/eDP.
I left the UMS cruft untouched.
Size differences:
text data bss dec hex filename
596431 4634 56 601121 92c21 i915.ko (new)
593199 4634 56 597889 91f81 i915.ko (old)
Signed-off-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-02-04 20:22:24 +08:00
|
|
|
GEN_DEFAULT_PIPEOFFSETS,
|
2014-04-09 18:28:53 +08:00
|
|
|
CURSOR_OFFSETS,
|
2012-03-29 04:39:21 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct intel_device_info intel_valleyview_d_info = {
|
2013-03-16 02:17:54 +08:00
|
|
|
GEN7_FEATURES,
|
|
|
|
.num_pipes = 2,
|
2012-03-29 04:39:21 +08:00
|
|
|
.is_valleyview = 1,
|
2013-01-24 21:29:56 +08:00
|
|
|
.display_mmio_offset = VLV_DISPLAY_BASE,
|
2013-11-07 05:02:24 +08:00
|
|
|
.has_fbc = 0, /* legal, last one wins */
|
2013-04-16 12:48:03 +08:00
|
|
|
.has_llc = 0, /* legal, last one wins */
|
drm/i915: Reorganize display pipe register accesses
RFCv2: Reorganize array indexing so that full offsets can be used as
is. It makes grepping for registers in i915_reg.h much easier. Also
move offset arrays to intel_device_info.
v1: Fixed offsets for VLV, proper eDP handling
v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros.
v3: Added EDP pipe comment, removed redundant offset arrays for
MSA_MISC and DDI_FUNC_CTL.
v4: Rename patch and report object size increase.
v5: Change location of commas, add PIPE_EDP into enum pipe
v6: Insert PIPE_EDP_OFFSET into pipe offset array
v7: Set I915_MAX_PIPES back to 3, change more registers accessors
to use the new macros, get rid of _PIPE_INC and add dev_priv
as a parameter where required by the new macros.
Upcoming hardware will not have the various display pipe register
ranges evenly spaced in memory. Change register address calculations
into array lookups.
Tested on SNB, VLV, IVB, Gen2 and HSW w/eDP.
I left the UMS cruft untouched.
Size differences:
text data bss dec hex filename
596431 4634 56 601121 92c21 i915.ko (new)
593199 4634 56 597889 91f81 i915.ko (old)
Signed-off-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-02-04 20:22:24 +08:00
|
|
|
GEN_DEFAULT_PIPEOFFSETS,
|
2014-04-09 18:28:53 +08:00
|
|
|
CURSOR_OFFSETS,
|
2012-03-29 04:39:21 +08:00
|
|
|
};
|
|
|
|
|
2012-03-29 23:32:18 +08:00
|
|
|
static const struct intel_device_info intel_haswell_d_info = {
|
2013-03-16 02:17:54 +08:00
|
|
|
GEN7_FEATURES,
|
|
|
|
.is_haswell = 1,
|
2013-04-23 01:40:39 +08:00
|
|
|
.has_ddi = 1,
|
2013-04-23 01:40:41 +08:00
|
|
|
.has_fpga_dbg = 1,
|
2013-10-16 01:02:57 +08:00
|
|
|
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
|
drm/i915: Reorganize display pipe register accesses
RFCv2: Reorganize array indexing so that full offsets can be used as
is. It makes grepping for registers in i915_reg.h much easier. Also
move offset arrays to intel_device_info.
v1: Fixed offsets for VLV, proper eDP handling
v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros.
v3: Added EDP pipe comment, removed redundant offset arrays for
MSA_MISC and DDI_FUNC_CTL.
v4: Rename patch and report object size increase.
v5: Change location of commas, add PIPE_EDP into enum pipe
v6: Insert PIPE_EDP_OFFSET into pipe offset array
v7: Set I915_MAX_PIPES back to 3, change more registers accessors
to use the new macros, get rid of _PIPE_INC and add dev_priv
as a parameter where required by the new macros.
Upcoming hardware will not have the various display pipe register
ranges evenly spaced in memory. Change register address calculations
into array lookups.
Tested on SNB, VLV, IVB, Gen2 and HSW w/eDP.
I left the UMS cruft untouched.
Size differences:
text data bss dec hex filename
596431 4634 56 601121 92c21 i915.ko (new)
593199 4634 56 597889 91f81 i915.ko (old)
Signed-off-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-02-04 20:22:24 +08:00
|
|
|
GEN_DEFAULT_PIPEOFFSETS,
|
2014-04-09 18:28:53 +08:00
|
|
|
IVB_CURSOR_OFFSETS,
|
2012-03-29 23:32:18 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct intel_device_info intel_haswell_m_info = {
|
2013-03-16 02:17:54 +08:00
|
|
|
GEN7_FEATURES,
|
|
|
|
.is_haswell = 1,
|
|
|
|
.is_mobile = 1,
|
2013-04-23 01:40:39 +08:00
|
|
|
.has_ddi = 1,
|
2013-04-23 01:40:41 +08:00
|
|
|
.has_fpga_dbg = 1,
|
2013-10-16 01:02:57 +08:00
|
|
|
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
|
drm/i915: Reorganize display pipe register accesses
RFCv2: Reorganize array indexing so that full offsets can be used as
is. It makes grepping for registers in i915_reg.h much easier. Also
move offset arrays to intel_device_info.
v1: Fixed offsets for VLV, proper eDP handling
v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros.
v3: Added EDP pipe comment, removed redundant offset arrays for
MSA_MISC and DDI_FUNC_CTL.
v4: Rename patch and report object size increase.
v5: Change location of commas, add PIPE_EDP into enum pipe
v6: Insert PIPE_EDP_OFFSET into pipe offset array
v7: Set I915_MAX_PIPES back to 3, change more registers accessors
to use the new macros, get rid of _PIPE_INC and add dev_priv
as a parameter where required by the new macros.
Upcoming hardware will not have the various display pipe register
ranges evenly spaced in memory. Change register address calculations
into array lookups.
Tested on SNB, VLV, IVB, Gen2 and HSW w/eDP.
I left the UMS cruft untouched.
Size differences:
text data bss dec hex filename
596431 4634 56 601121 92c21 i915.ko (new)
593199 4634 56 597889 91f81 i915.ko (old)
Signed-off-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-02-04 20:22:24 +08:00
|
|
|
GEN_DEFAULT_PIPEOFFSETS,
|
2014-04-09 18:28:53 +08:00
|
|
|
IVB_CURSOR_OFFSETS,
|
2011-04-29 05:32:07 +08:00
|
|
|
};
|
|
|
|
|
2013-11-04 08:47:33 +08:00
|
|
|
static const struct intel_device_info intel_broadwell_d_info = {
|
2013-11-03 12:07:32 +08:00
|
|
|
.gen = 8, .num_pipes = 3,
|
2013-11-04 08:47:33 +08:00
|
|
|
.need_gfx_hws = 1, .has_hotplug = 1,
|
|
|
|
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
|
|
|
|
.has_llc = 1,
|
|
|
|
.has_ddi = 1,
|
2014-07-17 04:49:30 +08:00
|
|
|
.has_fpga_dbg = 1,
|
2014-02-21 08:01:20 +08:00
|
|
|
.has_fbc = 1,
|
drm/i915: Reorganize display pipe register accesses
RFCv2: Reorganize array indexing so that full offsets can be used as
is. It makes grepping for registers in i915_reg.h much easier. Also
move offset arrays to intel_device_info.
v1: Fixed offsets for VLV, proper eDP handling
v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros.
v3: Added EDP pipe comment, removed redundant offset arrays for
MSA_MISC and DDI_FUNC_CTL.
v4: Rename patch and report object size increase.
v5: Change location of commas, add PIPE_EDP into enum pipe
v6: Insert PIPE_EDP_OFFSET into pipe offset array
v7: Set I915_MAX_PIPES back to 3, change more registers accessors
to use the new macros, get rid of _PIPE_INC and add dev_priv
as a parameter where required by the new macros.
Upcoming hardware will not have the various display pipe register
ranges evenly spaced in memory. Change register address calculations
into array lookups.
Tested on SNB, VLV, IVB, Gen2 and HSW w/eDP.
I left the UMS cruft untouched.
Size differences:
text data bss dec hex filename
596431 4634 56 601121 92c21 i915.ko (new)
593199 4634 56 597889 91f81 i915.ko (old)
Signed-off-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-02-04 20:22:24 +08:00
|
|
|
GEN_DEFAULT_PIPEOFFSETS,
|
2014-04-09 18:28:53 +08:00
|
|
|
IVB_CURSOR_OFFSETS,
|
2013-11-04 08:47:33 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct intel_device_info intel_broadwell_m_info = {
|
2013-11-03 12:07:32 +08:00
|
|
|
.gen = 8, .is_mobile = 1, .num_pipes = 3,
|
2013-11-04 08:47:33 +08:00
|
|
|
.need_gfx_hws = 1, .has_hotplug = 1,
|
|
|
|
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
|
|
|
|
.has_llc = 1,
|
|
|
|
.has_ddi = 1,
|
2014-07-17 04:49:30 +08:00
|
|
|
.has_fpga_dbg = 1,
|
2014-02-21 08:01:20 +08:00
|
|
|
.has_fbc = 1,
|
drm/i915: Reorganize display pipe register accesses
RFCv2: Reorganize array indexing so that full offsets can be used as
is. It makes grepping for registers in i915_reg.h much easier. Also
move offset arrays to intel_device_info.
v1: Fixed offsets for VLV, proper eDP handling
v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros.
v3: Added EDP pipe comment, removed redundant offset arrays for
MSA_MISC and DDI_FUNC_CTL.
v4: Rename patch and report object size increase.
v5: Change location of commas, add PIPE_EDP into enum pipe
v6: Insert PIPE_EDP_OFFSET into pipe offset array
v7: Set I915_MAX_PIPES back to 3, change more registers accessors
to use the new macros, get rid of _PIPE_INC and add dev_priv
as a parameter where required by the new macros.
Upcoming hardware will not have the various display pipe register
ranges evenly spaced in memory. Change register address calculations
into array lookups.
Tested on SNB, VLV, IVB, Gen2 and HSW w/eDP.
I left the UMS cruft untouched.
Size differences:
text data bss dec hex filename
596431 4634 56 601121 92c21 i915.ko (new)
593199 4634 56 597889 91f81 i915.ko (old)
Signed-off-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-02-04 20:22:24 +08:00
|
|
|
GEN_DEFAULT_PIPEOFFSETS,
|
2014-06-05 08:09:30 +08:00
|
|
|
IVB_CURSOR_OFFSETS,
|
2013-11-04 08:47:33 +08:00
|
|
|
};
|
|
|
|
|
2014-04-17 10:37:35 +08:00
|
|
|
static const struct intel_device_info intel_broadwell_gt3d_info = {
|
|
|
|
.gen = 8, .num_pipes = 3,
|
|
|
|
.need_gfx_hws = 1, .has_hotplug = 1,
|
2014-04-17 10:37:37 +08:00
|
|
|
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
|
2014-04-17 10:37:35 +08:00
|
|
|
.has_llc = 1,
|
|
|
|
.has_ddi = 1,
|
2014-07-17 04:49:30 +08:00
|
|
|
.has_fpga_dbg = 1,
|
2014-04-17 10:37:35 +08:00
|
|
|
.has_fbc = 1,
|
|
|
|
GEN_DEFAULT_PIPEOFFSETS,
|
2014-06-05 08:09:30 +08:00
|
|
|
IVB_CURSOR_OFFSETS,
|
2014-04-17 10:37:35 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct intel_device_info intel_broadwell_gt3m_info = {
|
|
|
|
.gen = 8, .is_mobile = 1, .num_pipes = 3,
|
|
|
|
.need_gfx_hws = 1, .has_hotplug = 1,
|
2014-04-17 10:37:37 +08:00
|
|
|
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
|
2014-04-17 10:37:35 +08:00
|
|
|
.has_llc = 1,
|
|
|
|
.has_ddi = 1,
|
2014-07-17 04:49:30 +08:00
|
|
|
.has_fpga_dbg = 1,
|
2014-04-17 10:37:35 +08:00
|
|
|
.has_fbc = 1,
|
|
|
|
GEN_DEFAULT_PIPEOFFSETS,
|
2014-04-09 18:28:53 +08:00
|
|
|
IVB_CURSOR_OFFSETS,
|
2014-04-17 10:37:35 +08:00
|
|
|
};
|
|
|
|
|
2014-04-09 23:19:04 +08:00
|
|
|
static const struct intel_device_info intel_cherryview_info = {
|
2014-04-09 18:28:54 +08:00
|
|
|
.gen = 8, .num_pipes = 3,
|
2014-04-09 23:19:04 +08:00
|
|
|
.need_gfx_hws = 1, .has_hotplug = 1,
|
|
|
|
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
|
|
|
|
.is_valleyview = 1,
|
|
|
|
.display_mmio_offset = VLV_DISPLAY_BASE,
|
2014-04-28 19:00:42 +08:00
|
|
|
GEN_CHV_PIPEOFFSETS,
|
2014-04-09 18:28:53 +08:00
|
|
|
CURSOR_OFFSETS,
|
2014-04-09 23:19:04 +08:00
|
|
|
};
|
|
|
|
|
2013-02-13 23:27:37 +08:00
|
|
|
static const struct intel_device_info intel_skylake_info = {
|
|
|
|
.is_preliminary = 1,
|
2014-04-02 13:54:50 +08:00
|
|
|
.is_skylake = 1,
|
2013-02-13 23:27:37 +08:00
|
|
|
.gen = 9, .num_pipes = 3,
|
|
|
|
.need_gfx_hws = 1, .has_hotplug = 1,
|
|
|
|
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
|
|
|
|
.has_llc = 1,
|
|
|
|
.has_ddi = 1,
|
2014-04-24 08:13:09 +08:00
|
|
|
.has_fbc = 1,
|
2013-02-13 23:27:37 +08:00
|
|
|
GEN_DEFAULT_PIPEOFFSETS,
|
|
|
|
IVB_CURSOR_OFFSETS,
|
|
|
|
};
|
|
|
|
|
2015-02-04 21:22:27 +08:00
|
|
|
static const struct intel_device_info intel_skylake_gt3_info = {
|
|
|
|
.is_preliminary = 1,
|
|
|
|
.is_skylake = 1,
|
|
|
|
.gen = 9, .num_pipes = 3,
|
|
|
|
.need_gfx_hws = 1, .has_hotplug = 1,
|
|
|
|
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
|
|
|
|
.has_llc = 1,
|
|
|
|
.has_ddi = 1,
|
|
|
|
.has_fbc = 1,
|
|
|
|
GEN_DEFAULT_PIPEOFFSETS,
|
|
|
|
IVB_CURSOR_OFFSETS,
|
|
|
|
};
|
|
|
|
|
2015-03-17 17:39:27 +08:00
|
|
|
static const struct intel_device_info intel_broxton_info = {
|
|
|
|
.is_preliminary = 1,
|
|
|
|
.gen = 9,
|
|
|
|
.need_gfx_hws = 1, .has_hotplug = 1,
|
|
|
|
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
|
|
|
|
.num_pipes = 3,
|
|
|
|
.has_ddi = 1,
|
2015-03-17 17:39:28 +08:00
|
|
|
.has_fbc = 1,
|
2015-03-17 17:39:27 +08:00
|
|
|
GEN_DEFAULT_PIPEOFFSETS,
|
|
|
|
IVB_CURSOR_OFFSETS,
|
|
|
|
};
|
|
|
|
|
2013-07-27 04:32:51 +08:00
|
|
|
/*
|
|
|
|
* Make sure any device matches here are from most specific to most
|
|
|
|
* general. For example, since the Quanta match is based on the subsystem
|
|
|
|
* and subvendor IDs, we need it to come before the more general IVB
|
|
|
|
* PCI ID matches, otherwise we'll use the wrong info struct above.
|
|
|
|
*/
|
|
|
|
#define INTEL_PCI_IDS \
|
|
|
|
INTEL_I830_IDS(&intel_i830_info), \
|
|
|
|
INTEL_I845G_IDS(&intel_845g_info), \
|
|
|
|
INTEL_I85X_IDS(&intel_i85x_info), \
|
|
|
|
INTEL_I865G_IDS(&intel_i865g_info), \
|
|
|
|
INTEL_I915G_IDS(&intel_i915g_info), \
|
|
|
|
INTEL_I915GM_IDS(&intel_i915gm_info), \
|
|
|
|
INTEL_I945G_IDS(&intel_i945g_info), \
|
|
|
|
INTEL_I945GM_IDS(&intel_i945gm_info), \
|
|
|
|
INTEL_I965G_IDS(&intel_i965g_info), \
|
|
|
|
INTEL_G33_IDS(&intel_g33_info), \
|
|
|
|
INTEL_I965GM_IDS(&intel_i965gm_info), \
|
|
|
|
INTEL_GM45_IDS(&intel_gm45_info), \
|
|
|
|
INTEL_G45_IDS(&intel_g45_info), \
|
|
|
|
INTEL_PINEVIEW_IDS(&intel_pineview_info), \
|
|
|
|
INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \
|
|
|
|
INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \
|
|
|
|
INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \
|
|
|
|
INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \
|
|
|
|
INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
|
|
|
|
INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \
|
|
|
|
INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \
|
|
|
|
INTEL_HSW_D_IDS(&intel_haswell_d_info), \
|
|
|
|
INTEL_HSW_M_IDS(&intel_haswell_m_info), \
|
|
|
|
INTEL_VLV_M_IDS(&intel_valleyview_m_info), \
|
2013-11-04 08:47:33 +08:00
|
|
|
INTEL_VLV_D_IDS(&intel_valleyview_d_info), \
|
2014-04-17 10:37:35 +08:00
|
|
|
INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \
|
|
|
|
INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \
|
|
|
|
INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
|
2014-04-09 23:19:04 +08:00
|
|
|
INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
|
2013-02-13 23:27:37 +08:00
|
|
|
INTEL_CHV_IDS(&intel_cherryview_info), \
|
2015-02-04 21:22:27 +08:00
|
|
|
INTEL_SKL_GT1_IDS(&intel_skylake_info), \
|
|
|
|
INTEL_SKL_GT2_IDS(&intel_skylake_info), \
|
2015-03-17 17:39:27 +08:00
|
|
|
INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), \
|
|
|
|
INTEL_BXT_IDS(&intel_broxton_info)
|
2013-07-27 04:32:51 +08:00
|
|
|
|
2010-07-06 01:01:47 +08:00
|
|
|
static const struct pci_device_id pciidlist[] = { /* aka */
|
2013-07-27 04:32:51 +08:00
|
|
|
INTEL_PCI_IDS,
|
2009-12-17 04:16:15 +08:00
|
|
|
{0, 0, 0}
|
2005-04-17 06:20:36 +08:00
|
|
|
};
|
|
|
|
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 06:24:08 +08:00
|
|
|
#if defined(CONFIG_DRM_I915_KMS)
|
|
|
|
MODULE_DEVICE_TABLE(pci, pciidlist);
|
|
|
|
#endif
|
|
|
|
|
2011-08-17 03:34:10 +08:00
|
|
|
void intel_detect_pch(struct drm_device *dev)
|
2010-04-07 16:15:53 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2014-02-15 02:23:54 +08:00
|
|
|
struct pci_dev *pch = NULL;
|
2010-04-07 16:15:53 +08:00
|
|
|
|
2013-04-06 04:12:44 +08:00
|
|
|
/* In all current cases, num_pipes is equivalent to the PCH_NOP setting
|
|
|
|
* (which really amounts to a PCH but no South Display).
|
|
|
|
*/
|
|
|
|
if (INTEL_INFO(dev)->num_pipes == 0) {
|
|
|
|
dev_priv->pch_type = PCH_NOP;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2010-04-07 16:15:53 +08:00
|
|
|
/*
|
|
|
|
* The reason to probe ISA bridge instead of Dev31:Fun0 is to
|
|
|
|
* make graphics device passthrough work easy for VMM, that only
|
|
|
|
* need to expose ISA bridge to let driver know the real hardware
|
|
|
|
* underneath. This is a requirement from virtualization team.
|
2013-06-19 21:10:23 +08:00
|
|
|
*
|
|
|
|
* In some virtualized environments (e.g. XEN), there is irrelevant
|
|
|
|
* ISA bridge in the system. To work reliably, we should scan trhough
|
|
|
|
* all the ISA bridge devices and check for the first match, instead
|
|
|
|
* of only checking the first one.
|
2010-04-07 16:15:53 +08:00
|
|
|
*/
|
2014-02-15 02:23:54 +08:00
|
|
|
while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
|
2010-04-07 16:15:53 +08:00
|
|
|
if (pch->vendor == PCI_VENDOR_ID_INTEL) {
|
2014-02-15 02:23:54 +08:00
|
|
|
unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
|
2012-11-21 01:12:07 +08:00
|
|
|
dev_priv->pch_id = id;
|
2010-04-07 16:15:53 +08:00
|
|
|
|
2011-04-29 05:48:02 +08:00
|
|
|
if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
|
|
|
|
dev_priv->pch_type = PCH_IBX;
|
|
|
|
DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
|
2012-11-01 05:52:27 +08:00
|
|
|
WARN_ON(!IS_GEN5(dev));
|
2011-04-29 05:48:02 +08:00
|
|
|
} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
|
2010-04-07 16:15:53 +08:00
|
|
|
dev_priv->pch_type = PCH_CPT;
|
|
|
|
DRM_DEBUG_KMS("Found CougarPoint PCH\n");
|
2012-11-01 05:52:27 +08:00
|
|
|
WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
|
2011-04-08 03:33:56 +08:00
|
|
|
} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
|
|
|
|
/* PantherPoint is CPT compatible */
|
|
|
|
dev_priv->pch_type = PCH_CPT;
|
2013-10-01 17:12:33 +08:00
|
|
|
DRM_DEBUG_KMS("Found PantherPoint PCH\n");
|
2012-11-01 05:52:27 +08:00
|
|
|
WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
|
2012-03-29 23:32:20 +08:00
|
|
|
} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
|
|
|
|
dev_priv->pch_type = PCH_LPT;
|
|
|
|
DRM_DEBUG_KMS("Found LynxPoint PCH\n");
|
2015-01-22 02:33:53 +08:00
|
|
|
WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
|
|
|
|
WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
|
2013-11-08 13:40:41 +08:00
|
|
|
} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
|
|
|
|
dev_priv->pch_type = PCH_LPT;
|
|
|
|
DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
|
2015-01-22 02:33:53 +08:00
|
|
|
WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
|
|
|
|
WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
|
2014-04-09 13:38:57 +08:00
|
|
|
} else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
|
|
|
|
dev_priv->pch_type = PCH_SPT;
|
|
|
|
DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
|
|
|
|
WARN_ON(!IS_SKYLAKE(dev));
|
|
|
|
} else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
|
|
|
|
dev_priv->pch_type = PCH_SPT;
|
|
|
|
DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
|
|
|
|
WARN_ON(!IS_SKYLAKE(dev));
|
2014-02-15 02:23:54 +08:00
|
|
|
} else
|
|
|
|
continue;
|
|
|
|
|
2013-06-19 21:10:23 +08:00
|
|
|
break;
|
2010-04-07 16:15:53 +08:00
|
|
|
}
|
|
|
|
}
|
2013-06-19 21:10:23 +08:00
|
|
|
if (!pch)
|
2014-02-15 02:23:54 +08:00
|
|
|
DRM_DEBUG_KMS("No PCH found.\n");
|
|
|
|
|
|
|
|
pci_dev_put(pch);
|
2010-04-07 16:15:53 +08:00
|
|
|
}
|
|
|
|
|
2012-04-06 05:47:36 +08:00
|
|
|
bool i915_semaphore_is_enabled(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
if (INTEL_INFO(dev)->gen < 6)
|
2013-12-17 16:56:53 +08:00
|
|
|
return false;
|
2012-04-06 05:47:36 +08:00
|
|
|
|
2014-01-21 17:24:25 +08:00
|
|
|
if (i915.semaphores >= 0)
|
|
|
|
return i915.semaphores;
|
2012-04-06 05:47:36 +08:00
|
|
|
|
2014-07-25 00:04:44 +08:00
|
|
|
/* TODO: make semaphores and Execlists play nicely together */
|
|
|
|
if (i915.enable_execlists)
|
|
|
|
return false;
|
|
|
|
|
2014-08-05 02:15:19 +08:00
|
|
|
/* Until we get further testing... */
|
|
|
|
if (IS_GEN8(dev))
|
|
|
|
return false;
|
|
|
|
|
2012-04-03 02:48:43 +08:00
|
|
|
#ifdef CONFIG_INTEL_IOMMU
|
2012-04-06 05:47:36 +08:00
|
|
|
/* Enable semaphores on SNB when IO remapping is off */
|
2012-04-03 02:48:43 +08:00
|
|
|
if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
|
|
|
|
return false;
|
|
|
|
#endif
|
2012-04-06 05:47:36 +08:00
|
|
|
|
2013-12-17 16:56:53 +08:00
|
|
|
return true;
|
2012-04-06 05:47:36 +08:00
|
|
|
}
|
|
|
|
|
2014-08-18 19:42:44 +08:00
|
|
|
void intel_hpd_cancel_work(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
spin_lock_irq(&dev_priv->irq_lock);
|
|
|
|
|
|
|
|
dev_priv->long_hpd_port_mask = 0;
|
|
|
|
dev_priv->short_hpd_port_mask = 0;
|
|
|
|
dev_priv->hpd_event_bits = 0;
|
|
|
|
|
|
|
|
spin_unlock_irq(&dev_priv->irq_lock);
|
|
|
|
|
|
|
|
cancel_work_sync(&dev_priv->dig_port_work);
|
|
|
|
cancel_work_sync(&dev_priv->hotplug_work);
|
|
|
|
cancel_delayed_work_sync(&dev_priv->hotplug_reenable_work);
|
|
|
|
}
|
|
|
|
|
drm/i915/skl: Add support to load SKL CSR firmware.
Display Context Save and Restore support is needed for
various SKL Display C states like DC5, DC6.
This implementation is added based on first version of DMC CSR program
that we received from h/w team.
Here we are using request_firmware based design.
Finally this firmware should end up in linux-firmware tree.
For SKL platform its mandatory to ensure that we load this
csr program before enabling DC states like DC5/DC6.
As CSR program gets reset on various conditions, we should ensure
to load it during boot and in future change to be added to load
this system resume sequence too.
v1: Initial relese as RFC patch
v2: Design change as per Daniel, Damien and Shobit's review comments
request firmware method followed.
v3: Some optimization and functional changes.
Pulled register defines into drivers/gpu/drm/i915/i915_reg.h
Used kmemdup to allocate and duplicate firmware content.
Ensured to free allocated buffer.
v4: Modified as per review comments from Satheesh and Daniel
Removed temporary buffer.
Optimized number of writes by replacing I915_WRITE with I915_WRITE64.
v5:
Modified as per review comemnts from Damien.
- Changed name for functions and firmware.
- Introduced HAS_CSR.
- Reverted back previous change and used csr_buf with u8 size.
- Using cpu_to_be64 for endianness change.
Modified as per review comments from Imre.
- Modified registers and macro names to be a bit closer to bspec terminology
and the existing register naming in the driver.
- Early return for non SKL platforms in intel_load_csr_program function.
- Added locking around CSR program load function as it may be called
concurrently during system/runtime resume.
- Releasing the fw before loading the program for consistency
- Handled error path during f/w load.
v6: Modified as per review comments from Imre.
- Corrected out_freecsr sequence.
v7: Modified as per review comments from Imre.
Fail loading fw if fw->size%8!=0.
v8: Rebase to latest.
v9: Rebase on top of -nightly (Damien)
v10: Enabled support for dmc firmware ver 1.0.
According to ver 1.0 in a single binary package all the firmware's that are
required for different stepping's of the product will be stored. The package
contains the css header, followed by the package header and the actual dmc
firmwares. Package header contains the firmware/stepping mapping table and
the corresponding firmware offsets to the individual binaries, within the
package. Each individual program binary contains the header and the payload
sections whose size is specified in the header section. This changes are done
to extract the specific firmaware from the package. (Animesh)
v11: Modified as per review comemnts from Imre.
- Added code comment from bpec for header structure elements.
- Added __packed to avoid structure padding.
- Added helper functions for stepping and substepping info.
- Added code comment for CSR_MAX_FW_SIZE.
- Disabled BXT firmware loading, will be enabled with dmc 1.0 support.
- Changed skl_stepping_info based on bspec, earlier used from config DB.
- Removed duplicate call of cpu_to_be* from intel_csr_load_program function.
- Used cpu_to_be32 instead of cpu_to_be64 as firmware binary in dword aligned.
- Added sanity check for header length.
- Added sanity check for mmio address got from firmware binary.
- kmalloc done separately for dmc header and dmc firmware. (Animesh)
v12: Modified as per review comemnts from Imre.
- Corrected the typo error in skl stepping info structure.
- Added out-of-bound access for skl_stepping_info.
- Sanity check for mmio address modified.
- Sanity check added for stepping and substeppig.
- Modified the intel_dmc_info structure, cache only the required header info. (Animesh)
v13: clarify firmware load error message.
The reason for a firmware loading failure can be obscure if the driver
is built-in. Provide an explanation to the user about the likely reason for
the failure and how to resolve it. (Imre)
v14: Suggested by Jani.
- fix s/I915/CONFIG_DRM_I915/ typo
- add fw_path to the firmware object instead of using a static ptr (Jani)
v15:
1) Changed the firmware name as dmc_gen9.bin, everytime for a new firmware version a symbolic link
with same name will help not to build kernel again.
2) Changes done as per review comments from Imre.
- Error check removed for intel_csr_ucode_init.
- Moved csr-specific data structure to intel_csr.h and optimization done on structure definition.
- fw->data used directly for parsing the header info & memory allocation
only done separately for payload. (Animesh)
v16:
- No need for out_regs label in i915_driver_load(), so removed it.
- Changed the firmware name as skl_dmc_ver1.bin, followed naming convention <platform>_dmc_<api-version>.bin (Animesh)
Issue: VIZ-2569
Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-05-04 20:58:44 +08:00
|
|
|
void i915_firmware_load_error_print(const char *fw_path, int err)
|
|
|
|
{
|
|
|
|
DRM_ERROR("failed to load firmware %s (%d)\n", fw_path, err);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If the reason is not known assume -ENOENT since that's the most
|
|
|
|
* usual failure mode.
|
|
|
|
*/
|
|
|
|
if (!err)
|
|
|
|
err = -ENOENT;
|
|
|
|
|
|
|
|
if (!(IS_BUILTIN(CONFIG_DRM_I915) && err == -ENOENT))
|
|
|
|
return;
|
|
|
|
|
|
|
|
DRM_ERROR(
|
|
|
|
"The driver is built-in, so to load the firmware you need to\n"
|
|
|
|
"include it either in the kernel (see CONFIG_EXTRA_FIRMWARE) or\n"
|
|
|
|
"in your initrd/initramfs image.\n");
|
|
|
|
}
|
|
|
|
|
2014-08-18 19:42:45 +08:00
|
|
|
static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = dev_priv->dev;
|
|
|
|
struct drm_encoder *encoder;
|
|
|
|
|
|
|
|
drm_modeset_lock_all(dev);
|
|
|
|
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
|
|
|
|
struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
|
|
|
|
|
|
|
|
if (intel_encoder->suspend)
|
|
|
|
intel_encoder->suspend(intel_encoder);
|
|
|
|
}
|
|
|
|
drm_modeset_unlock_all(dev);
|
|
|
|
}
|
|
|
|
|
2014-08-14 01:37:05 +08:00
|
|
|
static int intel_suspend_complete(struct drm_i915_private *dev_priv);
|
2014-10-28 03:54:32 +08:00
|
|
|
static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
|
|
|
|
bool rpm_resume);
|
2015-04-16 16:52:11 +08:00
|
|
|
static int skl_resume_prepare(struct drm_i915_private *dev_priv);
|
2015-05-20 21:45:14 +08:00
|
|
|
static int bxt_resume_prepare(struct drm_i915_private *dev_priv);
|
2015-04-16 16:52:11 +08:00
|
|
|
|
2014-08-14 01:37:05 +08:00
|
|
|
|
2014-10-24 00:23:25 +08:00
|
|
|
static int i915_drm_suspend(struct drm_device *dev)
|
2007-11-22 12:14:14 +08:00
|
|
|
{
|
2010-02-19 06:06:27 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-03-27 00:25:45 +08:00
|
|
|
struct drm_crtc *crtc;
|
2014-06-12 23:35:47 +08:00
|
|
|
pci_power_t opregion_target_state;
|
2015-02-23 19:03:26 +08:00
|
|
|
int error;
|
2010-02-19 06:06:27 +08:00
|
|
|
|
i915: ignore lid open event when resuming
i915 driver needs to do modeset when
1. system resumes from sleep
2. lid is opened
In PM_SUSPEND_MEM state, all the GPEs are cleared when system resumes,
thus it is the i915_resume code does the modeset rather than intel_lid_notify().
But in PM_SUSPEND_FREEZE state, this will be broken because
system is still responsive to the lid events.
1. When we close the lid in Freeze state, intel_lid_notify() sets modeset_on_lid.
2. When we reopen the lid, intel_lid_notify() will do a modeset,
before the system is resumed.
here is the error log,
[92146.548074] WARNING: at drivers/gpu/drm/i915/intel_display.c:1028 intel_wait_for_pipe_off+0x184/0x190 [i915]()
[92146.548076] Hardware name: VGN-Z540N
[92146.548078] pipe_off wait timed out
[92146.548167] Modules linked in: hid_generic usbhid hid snd_hda_codec_realtek snd_hda_intel snd_hda_codec parport_pc snd_hwdep ppdev snd_pcm_oss i915 snd_mixer_oss snd_pcm arc4 iwldvm snd_seq_dummy mac80211 snd_seq_oss snd_seq_midi fbcon tileblit font bitblit softcursor drm_kms_helper snd_rawmidi snd_seq_midi_event coretemp drm snd_seq kvm btusb bluetooth snd_timer iwlwifi pcmcia tpm_infineon i2c_algo_bit joydev snd_seq_device intel_agp cfg80211 snd intel_gtt yenta_socket pcmcia_rsrc sony_laptop agpgart microcode psmouse tpm_tis serio_raw mxm_wmi soundcore snd_page_alloc tpm acpi_cpufreq lpc_ich pcmcia_core tpm_bios mperf processor lp parport firewire_ohci firewire_core crc_itu_t sdhci_pci sdhci thermal e1000e
[92146.548173] Pid: 4304, comm: kworker/0:0 Tainted: G W 3.8.0-rc3-s0i3-v3-test+ #9
[92146.548175] Call Trace:
[92146.548189] [<c10378e2>] warn_slowpath_common+0x72/0xa0
[92146.548227] [<f86398b4>] ? intel_wait_for_pipe_off+0x184/0x190 [i915]
[92146.548263] [<f86398b4>] ? intel_wait_for_pipe_off+0x184/0x190 [i915]
[92146.548270] [<c10379b3>] warn_slowpath_fmt+0x33/0x40
[92146.548307] [<f86398b4>] intel_wait_for_pipe_off+0x184/0x190 [i915]
[92146.548344] [<f86399c2>] intel_disable_pipe+0x102/0x190 [i915]
[92146.548380] [<f8639ea4>] ? intel_disable_plane+0x64/0x80 [i915]
[92146.548417] [<f8639f7c>] i9xx_crtc_disable+0xbc/0x150 [i915]
[92146.548456] [<f863ebee>] intel_crtc_update_dpms+0x5e/0x90 [i915]
[92146.548493] [<f86437cf>] intel_modeset_setup_hw_state+0x42f/0x8f0 [i915]
[92146.548535] [<f8645b0b>] intel_lid_notify+0x9b/0xc0 [i915]
[92146.548543] [<c15610d3>] notifier_call_chain+0x43/0x60
[92146.548550] [<c105d1e1>] __blocking_notifier_call_chain+0x41/0x80
[92146.548556] [<c105d23f>] blocking_notifier_call_chain+0x1f/0x30
[92146.548563] [<c131a684>] acpi_lid_send_state+0x78/0xa4
[92146.548569] [<c131aa9e>] acpi_button_notify+0x3b/0xf1
[92146.548577] [<c12df56a>] ? acpi_os_execute+0x17/0x19
[92146.548582] [<c12e591a>] ? acpi_ec_sync_query+0xa5/0xbc
[92146.548589] [<c12e2b82>] acpi_device_notify+0x16/0x18
[92146.548595] [<c12f4904>] acpi_ev_notify_dispatch+0x38/0x4f
[92146.548600] [<c12df0e8>] acpi_os_execute_deferred+0x20/0x2b
[92146.548607] [<c1051208>] process_one_work+0x128/0x3f0
[92146.548613] [<c1564f73>] ? common_interrupt+0x33/0x38
[92146.548618] [<c104f8c0>] ? wake_up_worker+0x30/0x30
[92146.548624] [<c12df0c8>] ? acpi_os_wait_events_complete+0x1e/0x1e
[92146.548629] [<c10524f9>] worker_thread+0x119/0x3b0
[92146.548634] [<c10523e0>] ? manage_workers+0x240/0x240
[92146.548640] [<c1056e84>] kthread+0x94/0xa0
[92146.548647] [<c1060000>] ? ftrace_raw_output_sched_stat_runtime+0x70/0xf0
[92146.548652] [<c15649b7>] ret_from_kernel_thread+0x1b/0x28
[92146.548658] [<c1056df0>] ? kthread_create_on_node+0xc0/0xc0
three different modeset flags are introduced in this patch
MODESET_ON_LID_OPEN: do modeset on next lid open event
MODESET_DONE: modeset already done
MODESET_SUSPENDED: suspended, only do modeset when system is resumed
In this way,
1. when lid is closed, MODESET_ON_LID_OPEN is set so that
we'll do modeset on next lid open event.
2. when lid is opened, MODESET_DONE is set
so that duplicate lid open events will be ignored.
3. when system suspends, MODESET_SUSPENDED is set.
In this case, we will not do modeset on any lid events.
Plus, locking mechanism is also introduced to avoid racing.
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-02-05 15:41:53 +08:00
|
|
|
/* ignore lid events during suspend */
|
|
|
|
mutex_lock(&dev_priv->modeset_restore_lock);
|
|
|
|
dev_priv->modeset_restore = MODESET_SUSPENDED;
|
|
|
|
mutex_unlock(&dev_priv->modeset_restore_lock);
|
|
|
|
|
2013-08-20 00:18:09 +08:00
|
|
|
/* We do a lot of poking in a lot of registers, make sure they work
|
|
|
|
* properly. */
|
2014-02-18 06:02:02 +08:00
|
|
|
intel_display_set_init_power(dev_priv, true);
|
2013-01-26 02:59:15 +08:00
|
|
|
|
2010-12-07 07:20:40 +08:00
|
|
|
drm_kms_helper_poll_disable(dev);
|
|
|
|
|
2007-11-22 12:14:14 +08:00
|
|
|
pci_save_state(dev->pdev);
|
|
|
|
|
2015-02-23 19:03:26 +08:00
|
|
|
error = i915_gem_suspend(dev);
|
|
|
|
if (error) {
|
|
|
|
dev_err(&dev->pdev->dev,
|
|
|
|
"GEM idle failed, resume might fail\n");
|
|
|
|
return error;
|
|
|
|
}
|
2013-07-09 22:51:37 +08:00
|
|
|
|
2015-02-23 19:03:26 +08:00
|
|
|
intel_suspend_gt_powersave(dev);
|
2012-07-27 01:21:47 +08:00
|
|
|
|
2015-02-23 19:03:26 +08:00
|
|
|
/*
|
|
|
|
* Disable CRTCs directly since we want to preserve sw state
|
|
|
|
* for _thaw. Also, power gate the CRTC power wells.
|
|
|
|
*/
|
|
|
|
drm_modeset_lock_all(dev);
|
|
|
|
for_each_crtc(dev, crtc)
|
|
|
|
intel_crtc_control(crtc, false);
|
|
|
|
drm_modeset_unlock_all(dev);
|
2014-11-19 21:30:05 +08:00
|
|
|
|
2015-02-23 19:03:26 +08:00
|
|
|
intel_dp_mst_suspend(dev);
|
2013-04-17 19:04:50 +08:00
|
|
|
|
2015-02-23 19:03:26 +08:00
|
|
|
intel_runtime_pm_disable_interrupts(dev_priv);
|
|
|
|
intel_hpd_cancel_work(dev_priv);
|
2014-07-23 12:25:24 +08:00
|
|
|
|
2015-02-23 19:03:26 +08:00
|
|
|
intel_suspend_encoders(dev_priv);
|
2014-05-02 12:02:48 +08:00
|
|
|
|
2015-02-23 19:03:26 +08:00
|
|
|
intel_suspend_hw(dev);
|
2009-02-18 07:13:31 +08:00
|
|
|
|
2013-10-17 00:21:30 +08:00
|
|
|
i915_gem_suspend_gtt_mappings(dev);
|
|
|
|
|
2009-06-23 09:05:12 +08:00
|
|
|
i915_save_state(dev);
|
|
|
|
|
2014-06-23 20:46:02 +08:00
|
|
|
opregion_target_state = PCI_D3cold;
|
|
|
|
#if IS_ENABLED(CONFIG_ACPI_SLEEP)
|
|
|
|
if (acpi_target_system_state() < ACPI_STATE_S3)
|
2014-06-12 23:35:47 +08:00
|
|
|
opregion_target_state = PCI_D1;
|
2014-06-23 20:46:02 +08:00
|
|
|
#endif
|
2014-06-12 23:35:47 +08:00
|
|
|
intel_opregion_notify_adapter(dev, opregion_target_state);
|
|
|
|
|
2014-06-12 23:35:45 +08:00
|
|
|
intel_uncore_forcewake_reset(dev, false);
|
2010-08-19 23:09:23 +08:00
|
|
|
intel_opregion_fini(dev);
|
2008-08-06 02:37:25 +08:00
|
|
|
|
2014-08-13 20:09:46 +08:00
|
|
|
intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
|
2012-03-28 17:48:49 +08:00
|
|
|
|
2014-02-25 23:11:28 +08:00
|
|
|
dev_priv->suspend_count++;
|
|
|
|
|
2014-06-12 23:35:44 +08:00
|
|
|
intel_display_set_init_power(dev_priv, false);
|
|
|
|
|
2010-02-19 06:06:27 +08:00
|
|
|
return 0;
|
2010-02-08 04:48:24 +08:00
|
|
|
}
|
|
|
|
|
2015-03-02 19:04:41 +08:00
|
|
|
static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
|
2014-10-24 00:23:15 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = drm_dev->dev_private;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = intel_suspend_complete(dev_priv);
|
|
|
|
|
|
|
|
if (ret) {
|
|
|
|
DRM_ERROR("Suspend complete failed: %d\n", ret);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
pci_disable_device(drm_dev->pdev);
|
2015-03-02 19:04:41 +08:00
|
|
|
/*
|
|
|
|
* During hibernation on some GEN4 platforms the BIOS may try to access
|
|
|
|
* the device even though it's already in D3 and hang the machine. So
|
|
|
|
* leave the device in D0 on those platforms and hope the BIOS will
|
|
|
|
* power down the device properly. Platforms where this was seen:
|
|
|
|
* Lenovo Thinkpad X301, X61s
|
|
|
|
*/
|
|
|
|
if (!(hibernation &&
|
|
|
|
drm_dev->pdev->subsystem_vendor == PCI_VENDOR_ID_LENOVO &&
|
|
|
|
INTEL_INFO(dev_priv)->gen == 4))
|
|
|
|
pci_set_power_state(drm_dev->pdev, PCI_D3hot);
|
2014-10-24 00:23:15 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-10-24 00:23:27 +08:00
|
|
|
int i915_suspend_legacy(struct drm_device *dev, pm_message_t state)
|
2010-02-08 04:48:24 +08:00
|
|
|
{
|
|
|
|
int error;
|
|
|
|
|
|
|
|
if (!dev || !dev->dev_private) {
|
|
|
|
DRM_ERROR("dev: %p\n", dev);
|
|
|
|
DRM_ERROR("DRM not initialized, aborting suspend.\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
2014-09-10 23:16:55 +08:00
|
|
|
if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
|
|
|
|
state.event != PM_EVENT_FREEZE))
|
|
|
|
return -EINVAL;
|
2010-12-07 07:20:40 +08:00
|
|
|
|
|
|
|
if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
|
|
|
|
return 0;
|
2010-09-08 16:45:11 +08:00
|
|
|
|
2014-10-24 00:23:25 +08:00
|
|
|
error = i915_drm_suspend(dev);
|
2010-02-08 04:48:24 +08:00
|
|
|
if (error)
|
|
|
|
return error;
|
|
|
|
|
2015-03-02 19:04:41 +08:00
|
|
|
return i915_drm_suspend_late(dev, false);
|
2007-11-22 12:14:14 +08:00
|
|
|
}
|
|
|
|
|
2014-10-24 00:23:25 +08:00
|
|
|
static int i915_drm_resume(struct drm_device *dev)
|
2014-04-02 00:55:22 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-09-13 05:06:43 +08:00
|
|
|
|
2015-02-23 19:03:26 +08:00
|
|
|
mutex_lock(&dev->struct_mutex);
|
|
|
|
i915_gem_restore_gtt_mappings(dev);
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
2013-09-13 05:06:43 +08:00
|
|
|
|
2010-02-19 06:06:27 +08:00
|
|
|
i915_restore_state(dev);
|
2010-08-19 23:09:23 +08:00
|
|
|
intel_opregion_setup(dev);
|
2010-02-19 06:06:27 +08:00
|
|
|
|
2015-02-23 19:03:26 +08:00
|
|
|
intel_init_pch_refclk(dev);
|
|
|
|
drm_mode_config_reset(dev);
|
2012-05-09 18:56:28 +08:00
|
|
|
|
2015-05-11 15:50:45 +08:00
|
|
|
/*
|
|
|
|
* Interrupts have to be enabled before any batches are run. If not the
|
|
|
|
* GPU will hang. i915_gem_init_hw() will initiate batches to
|
|
|
|
* update/restore the context.
|
|
|
|
*
|
|
|
|
* Modeset enabling in intel_modeset_init_hw() also needs working
|
|
|
|
* interrupts.
|
|
|
|
*/
|
|
|
|
intel_runtime_pm_enable_interrupts(dev_priv);
|
|
|
|
|
2015-02-23 19:03:26 +08:00
|
|
|
mutex_lock(&dev->struct_mutex);
|
|
|
|
if (i915_gem_init_hw(dev)) {
|
|
|
|
DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
|
|
|
|
atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
|
|
|
|
}
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
2009-02-24 07:41:09 +08:00
|
|
|
|
2015-02-23 19:03:26 +08:00
|
|
|
intel_modeset_init_hw(dev);
|
2013-03-27 00:25:45 +08:00
|
|
|
|
2015-02-23 19:03:26 +08:00
|
|
|
spin_lock_irq(&dev_priv->irq_lock);
|
|
|
|
if (dev_priv->display.hpd_irq_setup)
|
|
|
|
dev_priv->display.hpd_irq_setup(dev);
|
|
|
|
spin_unlock_irq(&dev_priv->irq_lock);
|
2014-05-02 12:02:48 +08:00
|
|
|
|
2015-02-23 19:03:26 +08:00
|
|
|
drm_modeset_lock_all(dev);
|
|
|
|
intel_modeset_setup_hw_state(dev, true);
|
|
|
|
drm_modeset_unlock_all(dev);
|
2013-03-05 16:50:58 +08:00
|
|
|
|
2015-02-23 19:03:26 +08:00
|
|
|
intel_dp_mst_resume(dev);
|
2014-12-08 11:23:37 +08:00
|
|
|
|
2015-02-23 19:03:26 +08:00
|
|
|
/*
|
|
|
|
* ... but also need to make sure that hotplug processing
|
|
|
|
* doesn't cause havoc. Like in the driver load code we don't
|
|
|
|
* bother with the tiny race here where we might loose hotplug
|
|
|
|
* notifications.
|
|
|
|
* */
|
|
|
|
intel_hpd_init(dev_priv);
|
|
|
|
/* Config may have changed between suspend and resume */
|
|
|
|
drm_helper_hpd_irq_event(dev);
|
2011-01-06 04:01:25 +08:00
|
|
|
|
2010-08-19 23:09:23 +08:00
|
|
|
intel_opregion_init(dev);
|
|
|
|
|
2014-08-13 20:09:46 +08:00
|
|
|
intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
|
2012-11-03 02:13:59 +08:00
|
|
|
|
i915: ignore lid open event when resuming
i915 driver needs to do modeset when
1. system resumes from sleep
2. lid is opened
In PM_SUSPEND_MEM state, all the GPEs are cleared when system resumes,
thus it is the i915_resume code does the modeset rather than intel_lid_notify().
But in PM_SUSPEND_FREEZE state, this will be broken because
system is still responsive to the lid events.
1. When we close the lid in Freeze state, intel_lid_notify() sets modeset_on_lid.
2. When we reopen the lid, intel_lid_notify() will do a modeset,
before the system is resumed.
here is the error log,
[92146.548074] WARNING: at drivers/gpu/drm/i915/intel_display.c:1028 intel_wait_for_pipe_off+0x184/0x190 [i915]()
[92146.548076] Hardware name: VGN-Z540N
[92146.548078] pipe_off wait timed out
[92146.548167] Modules linked in: hid_generic usbhid hid snd_hda_codec_realtek snd_hda_intel snd_hda_codec parport_pc snd_hwdep ppdev snd_pcm_oss i915 snd_mixer_oss snd_pcm arc4 iwldvm snd_seq_dummy mac80211 snd_seq_oss snd_seq_midi fbcon tileblit font bitblit softcursor drm_kms_helper snd_rawmidi snd_seq_midi_event coretemp drm snd_seq kvm btusb bluetooth snd_timer iwlwifi pcmcia tpm_infineon i2c_algo_bit joydev snd_seq_device intel_agp cfg80211 snd intel_gtt yenta_socket pcmcia_rsrc sony_laptop agpgart microcode psmouse tpm_tis serio_raw mxm_wmi soundcore snd_page_alloc tpm acpi_cpufreq lpc_ich pcmcia_core tpm_bios mperf processor lp parport firewire_ohci firewire_core crc_itu_t sdhci_pci sdhci thermal e1000e
[92146.548173] Pid: 4304, comm: kworker/0:0 Tainted: G W 3.8.0-rc3-s0i3-v3-test+ #9
[92146.548175] Call Trace:
[92146.548189] [<c10378e2>] warn_slowpath_common+0x72/0xa0
[92146.548227] [<f86398b4>] ? intel_wait_for_pipe_off+0x184/0x190 [i915]
[92146.548263] [<f86398b4>] ? intel_wait_for_pipe_off+0x184/0x190 [i915]
[92146.548270] [<c10379b3>] warn_slowpath_fmt+0x33/0x40
[92146.548307] [<f86398b4>] intel_wait_for_pipe_off+0x184/0x190 [i915]
[92146.548344] [<f86399c2>] intel_disable_pipe+0x102/0x190 [i915]
[92146.548380] [<f8639ea4>] ? intel_disable_plane+0x64/0x80 [i915]
[92146.548417] [<f8639f7c>] i9xx_crtc_disable+0xbc/0x150 [i915]
[92146.548456] [<f863ebee>] intel_crtc_update_dpms+0x5e/0x90 [i915]
[92146.548493] [<f86437cf>] intel_modeset_setup_hw_state+0x42f/0x8f0 [i915]
[92146.548535] [<f8645b0b>] intel_lid_notify+0x9b/0xc0 [i915]
[92146.548543] [<c15610d3>] notifier_call_chain+0x43/0x60
[92146.548550] [<c105d1e1>] __blocking_notifier_call_chain+0x41/0x80
[92146.548556] [<c105d23f>] blocking_notifier_call_chain+0x1f/0x30
[92146.548563] [<c131a684>] acpi_lid_send_state+0x78/0xa4
[92146.548569] [<c131aa9e>] acpi_button_notify+0x3b/0xf1
[92146.548577] [<c12df56a>] ? acpi_os_execute+0x17/0x19
[92146.548582] [<c12e591a>] ? acpi_ec_sync_query+0xa5/0xbc
[92146.548589] [<c12e2b82>] acpi_device_notify+0x16/0x18
[92146.548595] [<c12f4904>] acpi_ev_notify_dispatch+0x38/0x4f
[92146.548600] [<c12df0e8>] acpi_os_execute_deferred+0x20/0x2b
[92146.548607] [<c1051208>] process_one_work+0x128/0x3f0
[92146.548613] [<c1564f73>] ? common_interrupt+0x33/0x38
[92146.548618] [<c104f8c0>] ? wake_up_worker+0x30/0x30
[92146.548624] [<c12df0c8>] ? acpi_os_wait_events_complete+0x1e/0x1e
[92146.548629] [<c10524f9>] worker_thread+0x119/0x3b0
[92146.548634] [<c10523e0>] ? manage_workers+0x240/0x240
[92146.548640] [<c1056e84>] kthread+0x94/0xa0
[92146.548647] [<c1060000>] ? ftrace_raw_output_sched_stat_runtime+0x70/0xf0
[92146.548652] [<c15649b7>] ret_from_kernel_thread+0x1b/0x28
[92146.548658] [<c1056df0>] ? kthread_create_on_node+0xc0/0xc0
three different modeset flags are introduced in this patch
MODESET_ON_LID_OPEN: do modeset on next lid open event
MODESET_DONE: modeset already done
MODESET_SUSPENDED: suspended, only do modeset when system is resumed
In this way,
1. when lid is closed, MODESET_ON_LID_OPEN is set so that
we'll do modeset on next lid open event.
2. when lid is opened, MODESET_DONE is set
so that duplicate lid open events will be ignored.
3. when system suspends, MODESET_SUSPENDED is set.
In this case, we will not do modeset on any lid events.
Plus, locking mechanism is also introduced to avoid racing.
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-02-05 15:41:53 +08:00
|
|
|
mutex_lock(&dev_priv->modeset_restore_lock);
|
|
|
|
dev_priv->modeset_restore = MODESET_DONE;
|
|
|
|
mutex_unlock(&dev_priv->modeset_restore_lock);
|
2013-12-07 06:32:13 +08:00
|
|
|
|
2014-06-12 23:35:47 +08:00
|
|
|
intel_opregion_notify_adapter(dev, PCI_D0);
|
|
|
|
|
2014-10-24 00:23:22 +08:00
|
|
|
drm_kms_helper_poll_enable(dev);
|
|
|
|
|
2014-04-09 16:19:43 +08:00
|
|
|
return 0;
|
2010-02-08 04:48:24 +08:00
|
|
|
}
|
|
|
|
|
2014-10-24 00:23:25 +08:00
|
|
|
static int i915_drm_resume_early(struct drm_device *dev)
|
2010-02-08 04:48:24 +08:00
|
|
|
{
|
2014-10-24 00:23:24 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2014-10-28 03:54:32 +08:00
|
|
|
int ret = 0;
|
2014-10-24 00:23:24 +08:00
|
|
|
|
2014-04-02 00:55:22 +08:00
|
|
|
/*
|
|
|
|
* We have a resume ordering issue with the snd-hda driver also
|
|
|
|
* requiring our device to be power up. Due to the lack of a
|
|
|
|
* parent/child relationship we currently solve this with an early
|
|
|
|
* resume hook.
|
|
|
|
*
|
|
|
|
* FIXME: This should be solved with a special hdmi sink device or
|
|
|
|
* similar so that power domains can be employed.
|
|
|
|
*/
|
2010-02-08 04:48:24 +08:00
|
|
|
if (pci_enable_device(dev->pdev))
|
|
|
|
return -EIO;
|
|
|
|
|
|
|
|
pci_set_master(dev->pdev);
|
|
|
|
|
2014-10-28 03:54:33 +08:00
|
|
|
if (IS_VALLEYVIEW(dev_priv))
|
2014-10-28 03:54:32 +08:00
|
|
|
ret = vlv_resume_prepare(dev_priv, false);
|
2014-10-24 00:23:24 +08:00
|
|
|
if (ret)
|
2015-05-20 21:45:15 +08:00
|
|
|
DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
|
|
|
|
ret);
|
2014-10-24 00:23:24 +08:00
|
|
|
|
|
|
|
intel_uncore_early_sanitize(dev, true);
|
2014-10-28 03:54:33 +08:00
|
|
|
|
2015-05-20 21:45:14 +08:00
|
|
|
if (IS_BROXTON(dev))
|
|
|
|
ret = bxt_resume_prepare(dev_priv);
|
2015-04-16 16:52:11 +08:00
|
|
|
else if (IS_SKYLAKE(dev_priv))
|
|
|
|
ret = skl_resume_prepare(dev_priv);
|
2015-05-20 21:45:14 +08:00
|
|
|
else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
|
|
|
|
hsw_disable_pc8(dev_priv);
|
2014-10-28 03:54:33 +08:00
|
|
|
|
2014-10-24 00:23:24 +08:00
|
|
|
intel_uncore_sanitize(dev);
|
|
|
|
intel_power_domains_init_hw(dev_priv);
|
|
|
|
|
|
|
|
return ret;
|
2014-04-02 00:55:22 +08:00
|
|
|
}
|
|
|
|
|
2014-10-24 00:23:27 +08:00
|
|
|
int i915_resume_legacy(struct drm_device *dev)
|
2014-04-02 00:55:22 +08:00
|
|
|
{
|
2014-10-24 00:23:17 +08:00
|
|
|
int ret;
|
2014-04-02 00:55:22 +08:00
|
|
|
|
2014-10-24 00:23:19 +08:00
|
|
|
if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
|
|
|
|
return 0;
|
|
|
|
|
2014-10-24 00:23:25 +08:00
|
|
|
ret = i915_drm_resume_early(dev);
|
2014-10-24 00:23:17 +08:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2014-10-24 00:23:18 +08:00
|
|
|
return i915_drm_resume(dev);
|
|
|
|
}
|
|
|
|
|
2009-09-15 05:48:45 +08:00
|
|
|
/**
|
2011-11-29 02:15:17 +08:00
|
|
|
* i915_reset - reset chip after a hang
|
2009-09-15 05:48:45 +08:00
|
|
|
* @dev: drm device to reset
|
|
|
|
*
|
|
|
|
* Reset the chip. Useful if a hang is detected. Returns zero on successful
|
|
|
|
* reset or otherwise an error code.
|
|
|
|
*
|
|
|
|
* Procedure is fairly simple:
|
|
|
|
* - reset the chip using the reset reg
|
|
|
|
* - re-init context state
|
|
|
|
* - re-init hardware status page
|
|
|
|
* - re-init ring buffer
|
|
|
|
* - re-init interrupt state
|
|
|
|
* - re-init display
|
|
|
|
*/
|
2012-04-27 21:17:44 +08:00
|
|
|
int i915_reset(struct drm_device *dev)
|
2009-09-15 05:48:45 +08:00
|
|
|
{
|
2014-03-31 19:27:21 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-05-28 17:38:44 +08:00
|
|
|
bool simulated;
|
2010-09-11 18:17:19 +08:00
|
|
|
int ret;
|
2009-09-15 05:48:45 +08:00
|
|
|
|
2014-01-21 17:24:25 +08:00
|
|
|
if (!i915.reset)
|
2010-12-23 21:33:15 +08:00
|
|
|
return 0;
|
|
|
|
|
2014-12-16 00:59:28 +08:00
|
|
|
intel_reset_gt_powersave(dev);
|
|
|
|
|
2012-07-05 04:18:39 +08:00
|
|
|
mutex_lock(&dev->struct_mutex);
|
2009-09-15 05:48:45 +08:00
|
|
|
|
2010-09-30 23:53:18 +08:00
|
|
|
i915_gem_reset(dev);
|
2010-09-19 19:31:36 +08:00
|
|
|
|
2013-05-28 17:38:44 +08:00
|
|
|
simulated = dev_priv->gpu_error.stop_rings != 0;
|
|
|
|
|
2013-08-30 21:19:28 +08:00
|
|
|
ret = intel_gpu_reset(dev);
|
|
|
|
|
|
|
|
/* Also reset the gpu hangman. */
|
|
|
|
if (simulated) {
|
|
|
|
DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
|
|
|
|
dev_priv->gpu_error.stop_rings = 0;
|
|
|
|
if (ret == -ENODEV) {
|
2013-11-07 16:48:57 +08:00
|
|
|
DRM_INFO("Reset not implemented, but ignoring "
|
|
|
|
"error for simulated gpu hangs\n");
|
2013-08-30 21:19:28 +08:00
|
|
|
ret = 0;
|
|
|
|
}
|
2013-05-28 17:38:44 +08:00
|
|
|
}
|
2013-08-30 21:19:28 +08:00
|
|
|
|
2014-10-01 07:02:04 +08:00
|
|
|
if (i915_stop_ring_allow_warn(dev_priv))
|
|
|
|
pr_notice("drm/i915: Resetting chip after gpu hang\n");
|
|
|
|
|
2010-09-11 18:17:19 +08:00
|
|
|
if (ret) {
|
2013-11-07 16:48:57 +08:00
|
|
|
DRM_ERROR("Failed to reset chip: %i\n", ret);
|
2010-05-17 21:23:52 +08:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
2010-09-19 19:38:26 +08:00
|
|
|
return ret;
|
2009-09-15 05:48:45 +08:00
|
|
|
}
|
|
|
|
|
2014-11-26 23:07:29 +08:00
|
|
|
intel_overlay_reset(dev_priv);
|
|
|
|
|
2009-09-15 05:48:45 +08:00
|
|
|
/* Ok, now get things going again... */
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Everything depends on having the GTT running, so we need to start
|
|
|
|
* there. Fortunately we don't need to do this unless we reset the
|
|
|
|
* chip at a PCI level.
|
|
|
|
*
|
|
|
|
* Next we need to restore the context, but we don't use those
|
|
|
|
* yet either...
|
|
|
|
*
|
|
|
|
* Ring buffer needs to be re-initialized in the KMS case, or if X
|
|
|
|
* was running at the time of the reset (i.e. we weren't VT
|
|
|
|
* switched away).
|
|
|
|
*/
|
2014-08-16 01:51:35 +08:00
|
|
|
|
2015-02-23 19:03:27 +08:00
|
|
|
/* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
|
|
|
|
dev_priv->gpu_error.reload_in_reset = true;
|
2014-08-16 01:51:35 +08:00
|
|
|
|
2015-02-23 19:03:27 +08:00
|
|
|
ret = i915_gem_init_hw(dev);
|
2014-08-16 01:51:35 +08:00
|
|
|
|
2015-02-23 19:03:27 +08:00
|
|
|
dev_priv->gpu_error.reload_in_reset = false;
|
2012-04-10 21:50:11 +08:00
|
|
|
|
2015-02-23 19:03:27 +08:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
if (ret) {
|
|
|
|
DRM_ERROR("Failed hw init on reset %d\n", ret);
|
|
|
|
return ret;
|
2009-09-15 05:48:45 +08:00
|
|
|
}
|
|
|
|
|
2015-02-23 19:03:27 +08:00
|
|
|
/*
|
|
|
|
* rps/rc6 re-init is necessary to restore state lost after the
|
|
|
|
* reset and the re-install of gt irqs. Skip for ironlake per
|
|
|
|
* previous concerns that it doesn't respond well to some forms
|
|
|
|
* of re-init after reset.
|
|
|
|
*/
|
|
|
|
if (INTEL_INFO(dev)->gen > 5)
|
|
|
|
intel_enable_gt_powersave(dev);
|
|
|
|
|
2009-09-15 05:48:45 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-12-22 07:09:25 +08:00
|
|
|
static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
2009-01-05 05:55:33 +08:00
|
|
|
{
|
2012-06-25 21:58:49 +08:00
|
|
|
struct intel_device_info *intel_info =
|
|
|
|
(struct intel_device_info *) ent->driver_data;
|
|
|
|
|
2014-01-21 17:24:25 +08:00
|
|
|
if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
|
2013-08-24 07:00:07 +08:00
|
|
|
DRM_INFO("This hardware requires preliminary hardware support.\n"
|
|
|
|
"See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
2011-02-02 03:43:02 +08:00
|
|
|
/* Only bind to function 0 of the device. Early generations
|
|
|
|
* used function 1 as a placeholder for multi-head. This causes
|
|
|
|
* us confusion instead, especially on the systems where both
|
|
|
|
* functions have the same PCI-ID!
|
|
|
|
*/
|
|
|
|
if (PCI_FUNC(pdev->devfn))
|
|
|
|
return -ENODEV;
|
|
|
|
|
2013-12-11 18:34:33 +08:00
|
|
|
driver.driver_features &= ~(DRIVER_USE_AGP);
|
2012-06-25 21:58:49 +08:00
|
|
|
|
2010-05-28 03:40:25 +08:00
|
|
|
return drm_get_pci_dev(pdev, ent, &driver);
|
2009-01-05 05:55:33 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
i915_pci_remove(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = pci_get_drvdata(pdev);
|
|
|
|
|
|
|
|
drm_put_dev(dev);
|
|
|
|
}
|
|
|
|
|
2010-02-08 04:48:24 +08:00
|
|
|
static int i915_pm_suspend(struct device *dev)
|
2009-01-05 05:55:33 +08:00
|
|
|
{
|
2010-02-08 04:48:24 +08:00
|
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
|
|
|
struct drm_device *drm_dev = pci_get_drvdata(pdev);
|
2009-01-05 05:55:33 +08:00
|
|
|
|
2010-02-08 04:48:24 +08:00
|
|
|
if (!drm_dev || !drm_dev->dev_private) {
|
|
|
|
dev_err(dev, "DRM not initialized, aborting suspend.\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
2009-01-05 05:55:33 +08:00
|
|
|
|
2010-12-07 07:20:40 +08:00
|
|
|
if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
|
|
|
|
return 0;
|
|
|
|
|
2014-10-24 00:23:25 +08:00
|
|
|
return i915_drm_suspend(drm_dev);
|
2014-04-02 00:55:22 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int i915_pm_suspend_late(struct device *dev)
|
|
|
|
{
|
2015-01-08 23:54:13 +08:00
|
|
|
struct drm_device *drm_dev = dev_to_i915(dev)->dev;
|
2014-04-02 00:55:22 +08:00
|
|
|
|
|
|
|
/*
|
2015-05-19 02:53:48 +08:00
|
|
|
* We have a suspend ordering issue with the snd-hda driver also
|
2014-04-02 00:55:22 +08:00
|
|
|
* requiring our device to be power up. Due to the lack of a
|
|
|
|
* parent/child relationship we currently solve this with an late
|
|
|
|
* suspend hook.
|
|
|
|
*
|
|
|
|
* FIXME: This should be solved with a special hdmi sink device or
|
|
|
|
* similar so that power domains can be employed.
|
|
|
|
*/
|
|
|
|
if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
|
|
|
|
return 0;
|
2009-01-05 05:55:33 +08:00
|
|
|
|
2015-03-02 19:04:41 +08:00
|
|
|
return i915_drm_suspend_late(drm_dev, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int i915_pm_poweroff_late(struct device *dev)
|
|
|
|
{
|
|
|
|
struct drm_device *drm_dev = dev_to_i915(dev)->dev;
|
|
|
|
|
|
|
|
if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
return i915_drm_suspend_late(drm_dev, true);
|
2009-12-16 13:36:10 +08:00
|
|
|
}
|
|
|
|
|
2014-04-02 00:55:22 +08:00
|
|
|
static int i915_pm_resume_early(struct device *dev)
|
|
|
|
{
|
2015-01-08 23:54:13 +08:00
|
|
|
struct drm_device *drm_dev = dev_to_i915(dev)->dev;
|
2014-04-02 00:55:22 +08:00
|
|
|
|
2014-10-24 00:23:19 +08:00
|
|
|
if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
|
|
|
|
return 0;
|
|
|
|
|
2014-10-24 00:23:25 +08:00
|
|
|
return i915_drm_resume_early(drm_dev);
|
2014-04-02 00:55:22 +08:00
|
|
|
}
|
|
|
|
|
2010-02-08 04:48:24 +08:00
|
|
|
static int i915_pm_resume(struct device *dev)
|
2009-12-16 13:36:10 +08:00
|
|
|
{
|
2015-01-08 23:54:13 +08:00
|
|
|
struct drm_device *drm_dev = dev_to_i915(dev)->dev;
|
2010-02-08 04:48:24 +08:00
|
|
|
|
2014-10-24 00:23:19 +08:00
|
|
|
if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
|
|
|
|
return 0;
|
|
|
|
|
2014-10-24 00:23:18 +08:00
|
|
|
return i915_drm_resume(drm_dev);
|
2009-12-16 13:36:10 +08:00
|
|
|
}
|
|
|
|
|
2015-04-16 16:52:11 +08:00
|
|
|
static int skl_suspend_complete(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
/* Enabling DC6 is not a hard requirement to enter runtime D3 */
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This is to ensure that CSR isn't identified as loaded before
|
|
|
|
* CSR-loading program is called during runtime-resume.
|
|
|
|
*/
|
|
|
|
intel_csr_load_status_set(dev_priv, FW_UNINITIALIZED);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-08-14 01:37:05 +08:00
|
|
|
static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
|
2014-03-08 07:12:33 +08:00
|
|
|
{
|
2014-03-08 07:12:35 +08:00
|
|
|
hsw_enable_pc8(dev_priv);
|
2014-04-15 21:39:45 +08:00
|
|
|
|
|
|
|
return 0;
|
2014-03-08 07:12:33 +08:00
|
|
|
}
|
|
|
|
|
2014-11-24 16:07:45 +08:00
|
|
|
static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = dev_priv->dev;
|
|
|
|
|
|
|
|
/* TODO: when DC5 support is added disable DC5 here. */
|
|
|
|
|
|
|
|
broxton_ddi_phy_uninit(dev);
|
|
|
|
broxton_uninit_cdclk(dev);
|
|
|
|
bxt_enable_dc9(dev_priv);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = dev_priv->dev;
|
|
|
|
|
|
|
|
/* TODO: when CSR FW support is added make sure the FW is loaded */
|
|
|
|
|
|
|
|
bxt_disable_dc9(dev_priv);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* TODO: when DC5 support is added enable DC5 here if the CSR FW
|
|
|
|
* is available.
|
|
|
|
*/
|
|
|
|
broxton_init_cdclk(dev);
|
|
|
|
broxton_ddi_phy_init(dev);
|
|
|
|
intel_prepare_ddi(dev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-04-16 16:52:11 +08:00
|
|
|
static int skl_resume_prepare(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = dev_priv->dev;
|
|
|
|
|
|
|
|
intel_csr_load_program(dev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-05-05 20:19:56 +08:00
|
|
|
/*
|
|
|
|
* Save all Gunit registers that may be lost after a D3 and a subsequent
|
|
|
|
* S0i[R123] transition. The list of registers needing a save/restore is
|
|
|
|
* defined in the VLV2_S0IXRegs document. This documents marks all Gunit
|
|
|
|
* registers in the following way:
|
|
|
|
* - Driver: saved/restored by the driver
|
|
|
|
* - Punit : saved/restored by the Punit firmware
|
|
|
|
* - No, w/o marking: no need to save/restore, since the register is R/O or
|
|
|
|
* used internally by the HW in a way that doesn't depend
|
|
|
|
* keeping the content across a suspend/resume.
|
|
|
|
* - Debug : used for debugging
|
|
|
|
*
|
|
|
|
* We save/restore all registers marked with 'Driver', with the following
|
|
|
|
* exceptions:
|
|
|
|
* - Registers out of use, including also registers marked with 'Debug'.
|
|
|
|
* These have no effect on the driver's operation, so we don't save/restore
|
|
|
|
* them to reduce the overhead.
|
|
|
|
* - Registers that are fully setup by an initialization function called from
|
|
|
|
* the resume path. For example many clock gating and RPS/RC6 registers.
|
|
|
|
* - Registers that provide the right functionality with their reset defaults.
|
|
|
|
*
|
|
|
|
* TODO: Except for registers that based on the above 3 criteria can be safely
|
|
|
|
* ignored, we save/restore all others, practically treating the HW context as
|
|
|
|
* a black-box for the driver. Further investigation is needed to reduce the
|
|
|
|
* saved/restored registers even further, by following the same 3 criteria.
|
|
|
|
*/
|
|
|
|
static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* GAM 0x4000-0x4770 */
|
|
|
|
s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
|
|
|
|
s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
|
|
|
|
s->arb_mode = I915_READ(ARB_MODE);
|
|
|
|
s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
|
|
|
|
s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
|
|
|
|
s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
|
|
|
|
|
|
|
|
s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
|
2015-04-16 07:52:30 +08:00
|
|
|
s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
|
2014-05-05 20:19:56 +08:00
|
|
|
|
|
|
|
s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
|
|
|
|
s->ecochk = I915_READ(GAM_ECOCHK);
|
|
|
|
s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
|
|
|
|
s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
|
|
|
|
|
|
|
|
s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
|
|
|
|
|
|
|
|
/* MBC 0x9024-0x91D0, 0x8500 */
|
|
|
|
s->g3dctl = I915_READ(VLV_G3DCTL);
|
|
|
|
s->gsckgctl = I915_READ(VLV_GSCKGCTL);
|
|
|
|
s->mbctl = I915_READ(GEN6_MBCTL);
|
|
|
|
|
|
|
|
/* GCP 0x9400-0x9424, 0x8100-0x810C */
|
|
|
|
s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
|
|
|
|
s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
|
|
|
|
s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
|
|
|
|
s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
|
|
|
|
s->rstctl = I915_READ(GEN6_RSTCTL);
|
|
|
|
s->misccpctl = I915_READ(GEN7_MISCCPCTL);
|
|
|
|
|
|
|
|
/* GPM 0xA000-0xAA84, 0x8000-0x80FC */
|
|
|
|
s->gfxpause = I915_READ(GEN6_GFXPAUSE);
|
|
|
|
s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
|
|
|
|
s->rpdeuc = I915_READ(GEN6_RPDEUC);
|
|
|
|
s->ecobus = I915_READ(ECOBUS);
|
|
|
|
s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
|
|
|
|
s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
|
|
|
|
s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
|
|
|
|
s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
|
|
|
|
s->rcedata = I915_READ(VLV_RCEDATA);
|
|
|
|
s->spare2gh = I915_READ(VLV_SPAREG2H);
|
|
|
|
|
|
|
|
/* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
|
|
|
|
s->gt_imr = I915_READ(GTIMR);
|
|
|
|
s->gt_ier = I915_READ(GTIER);
|
|
|
|
s->pm_imr = I915_READ(GEN6_PMIMR);
|
|
|
|
s->pm_ier = I915_READ(GEN6_PMIER);
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
|
|
|
|
s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
|
|
|
|
|
|
|
|
/* GT SA CZ domain, 0x100000-0x138124 */
|
|
|
|
s->tilectl = I915_READ(TILECTL);
|
|
|
|
s->gt_fifoctl = I915_READ(GTFIFOCTL);
|
|
|
|
s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
|
|
|
|
s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
|
|
|
|
s->pmwgicz = I915_READ(VLV_PMWGICZ);
|
|
|
|
|
|
|
|
/* Gunit-Display CZ domain, 0x182028-0x1821CF */
|
|
|
|
s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
|
|
|
|
s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
|
2015-04-02 05:22:57 +08:00
|
|
|
s->pcbr = I915_READ(VLV_PCBR);
|
2014-05-05 20:19:56 +08:00
|
|
|
s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Not saving any of:
|
|
|
|
* DFT, 0x9800-0x9EC0
|
|
|
|
* SARB, 0xB000-0xB1FC
|
|
|
|
* GAC, 0x5208-0x524C, 0x14000-0x14C000
|
|
|
|
* PCI CFG
|
|
|
|
*/
|
|
|
|
}
|
|
|
|
|
|
|
|
static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
|
|
|
|
u32 val;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* GAM 0x4000-0x4770 */
|
|
|
|
I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
|
|
|
|
I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
|
|
|
|
I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
|
|
|
|
I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
|
|
|
|
I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
|
|
|
|
I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
|
|
|
|
|
|
|
|
I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
|
2015-04-16 07:52:30 +08:00
|
|
|
I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
|
2014-05-05 20:19:56 +08:00
|
|
|
|
|
|
|
I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
|
|
|
|
I915_WRITE(GAM_ECOCHK, s->ecochk);
|
|
|
|
I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
|
|
|
|
I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
|
|
|
|
|
|
|
|
I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
|
|
|
|
|
|
|
|
/* MBC 0x9024-0x91D0, 0x8500 */
|
|
|
|
I915_WRITE(VLV_G3DCTL, s->g3dctl);
|
|
|
|
I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
|
|
|
|
I915_WRITE(GEN6_MBCTL, s->mbctl);
|
|
|
|
|
|
|
|
/* GCP 0x9400-0x9424, 0x8100-0x810C */
|
|
|
|
I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
|
|
|
|
I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
|
|
|
|
I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
|
|
|
|
I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
|
|
|
|
I915_WRITE(GEN6_RSTCTL, s->rstctl);
|
|
|
|
I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
|
|
|
|
|
|
|
|
/* GPM 0xA000-0xAA84, 0x8000-0x80FC */
|
|
|
|
I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
|
|
|
|
I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
|
|
|
|
I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
|
|
|
|
I915_WRITE(ECOBUS, s->ecobus);
|
|
|
|
I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
|
|
|
|
I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
|
|
|
|
I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
|
|
|
|
I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
|
|
|
|
I915_WRITE(VLV_RCEDATA, s->rcedata);
|
|
|
|
I915_WRITE(VLV_SPAREG2H, s->spare2gh);
|
|
|
|
|
|
|
|
/* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
|
|
|
|
I915_WRITE(GTIMR, s->gt_imr);
|
|
|
|
I915_WRITE(GTIER, s->gt_ier);
|
|
|
|
I915_WRITE(GEN6_PMIMR, s->pm_imr);
|
|
|
|
I915_WRITE(GEN6_PMIER, s->pm_ier);
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
|
|
|
|
I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
|
|
|
|
|
|
|
|
/* GT SA CZ domain, 0x100000-0x138124 */
|
|
|
|
I915_WRITE(TILECTL, s->tilectl);
|
|
|
|
I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
|
|
|
|
/*
|
|
|
|
* Preserve the GT allow wake and GFX force clock bit, they are not
|
|
|
|
* be restored, as they are used to control the s0ix suspend/resume
|
|
|
|
* sequence by the caller.
|
|
|
|
*/
|
|
|
|
val = I915_READ(VLV_GTLC_WAKE_CTRL);
|
|
|
|
val &= VLV_GTLC_ALLOWWAKEREQ;
|
|
|
|
val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
|
|
|
|
I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
|
|
|
|
|
|
|
|
val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
|
|
|
|
val &= VLV_GFX_CLK_FORCE_ON_BIT;
|
|
|
|
val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
|
|
|
|
I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
|
|
|
|
|
|
|
|
I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
|
|
|
|
|
|
|
|
/* Gunit-Display CZ domain, 0x182028-0x1821CF */
|
|
|
|
I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
|
|
|
|
I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
|
2015-04-02 05:22:57 +08:00
|
|
|
I915_WRITE(VLV_PCBR, s->pcbr);
|
2014-05-05 20:19:56 +08:00
|
|
|
I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
|
|
|
|
}
|
|
|
|
|
2014-04-18 21:35:02 +08:00
|
|
|
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
|
|
|
|
{
|
|
|
|
u32 val;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
#define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
|
|
|
|
|
|
|
|
val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
|
|
|
|
val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
|
|
|
|
if (force_on)
|
|
|
|
val |= VLV_GFX_CLK_FORCE_ON_BIT;
|
|
|
|
I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
|
|
|
|
|
|
|
|
if (!force_on)
|
|
|
|
return 0;
|
|
|
|
|
2014-04-15 01:24:43 +08:00
|
|
|
err = wait_for(COND, 20);
|
2014-04-18 21:35:02 +08:00
|
|
|
if (err)
|
|
|
|
DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
|
|
|
|
I915_READ(VLV_GTLC_SURVIVABILITY_REG));
|
|
|
|
|
|
|
|
return err;
|
|
|
|
#undef COND
|
|
|
|
}
|
|
|
|
|
2014-05-05 20:19:56 +08:00
|
|
|
static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
|
|
|
|
{
|
|
|
|
u32 val;
|
|
|
|
int err = 0;
|
|
|
|
|
|
|
|
val = I915_READ(VLV_GTLC_WAKE_CTRL);
|
|
|
|
val &= ~VLV_GTLC_ALLOWWAKEREQ;
|
|
|
|
if (allow)
|
|
|
|
val |= VLV_GTLC_ALLOWWAKEREQ;
|
|
|
|
I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
|
|
|
|
POSTING_READ(VLV_GTLC_WAKE_CTRL);
|
|
|
|
|
|
|
|
#define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
|
|
|
|
allow)
|
|
|
|
err = wait_for(COND, 1);
|
|
|
|
if (err)
|
|
|
|
DRM_ERROR("timeout disabling GT waking\n");
|
|
|
|
return err;
|
|
|
|
#undef COND
|
|
|
|
}
|
|
|
|
|
|
|
|
static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
|
|
|
|
bool wait_for_on)
|
|
|
|
{
|
|
|
|
u32 mask;
|
|
|
|
u32 val;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
|
|
|
|
val = wait_for_on ? mask : 0;
|
|
|
|
#define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
|
|
|
|
if (COND)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
|
|
|
|
wait_for_on ? "on" : "off",
|
|
|
|
I915_READ(VLV_GTLC_PW_STATUS));
|
|
|
|
|
|
|
|
/*
|
|
|
|
* RC6 transitioning can be delayed up to 2 msec (see
|
|
|
|
* valleyview_enable_rps), use 3 msec for safety.
|
|
|
|
*/
|
|
|
|
err = wait_for(COND, 3);
|
|
|
|
if (err)
|
|
|
|
DRM_ERROR("timeout waiting for GT wells to go %s\n",
|
|
|
|
wait_for_on ? "on" : "off");
|
|
|
|
|
|
|
|
return err;
|
|
|
|
#undef COND
|
|
|
|
}
|
|
|
|
|
|
|
|
static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
|
|
|
|
return;
|
|
|
|
|
|
|
|
DRM_ERROR("GT register access while GT waking disabled\n");
|
|
|
|
I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
|
|
|
|
}
|
|
|
|
|
2014-08-14 01:37:05 +08:00
|
|
|
static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
|
2014-05-05 20:19:56 +08:00
|
|
|
{
|
|
|
|
u32 mask;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Bspec defines the following GT well on flags as debug only, so
|
|
|
|
* don't treat them as hard failures.
|
|
|
|
*/
|
|
|
|
(void)vlv_wait_for_gt_wells(dev_priv, false);
|
|
|
|
|
|
|
|
mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
|
|
|
|
WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
|
|
|
|
|
|
|
|
vlv_check_no_gt_access(dev_priv);
|
|
|
|
|
|
|
|
err = vlv_force_gfx_clock(dev_priv, true);
|
|
|
|
if (err)
|
|
|
|
goto err1;
|
|
|
|
|
|
|
|
err = vlv_allow_gt_wake(dev_priv, false);
|
|
|
|
if (err)
|
|
|
|
goto err2;
|
2014-12-12 16:48:16 +08:00
|
|
|
|
|
|
|
if (!IS_CHERRYVIEW(dev_priv->dev))
|
|
|
|
vlv_save_gunit_s0ix_state(dev_priv);
|
2014-05-05 20:19:56 +08:00
|
|
|
|
|
|
|
err = vlv_force_gfx_clock(dev_priv, false);
|
|
|
|
if (err)
|
|
|
|
goto err2;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err2:
|
|
|
|
/* For safety always re-enable waking and disable gfx clock forcing */
|
|
|
|
vlv_allow_gt_wake(dev_priv, true);
|
|
|
|
err1:
|
|
|
|
vlv_force_gfx_clock(dev_priv, false);
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2014-08-14 01:37:06 +08:00
|
|
|
static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
|
|
|
|
bool rpm_resume)
|
2014-05-05 20:19:56 +08:00
|
|
|
{
|
|
|
|
struct drm_device *dev = dev_priv->dev;
|
|
|
|
int err;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If any of the steps fail just try to continue, that's the best we
|
|
|
|
* can do at this point. Return the first error code (which will also
|
|
|
|
* leave RPM permanently disabled).
|
|
|
|
*/
|
|
|
|
ret = vlv_force_gfx_clock(dev_priv, true);
|
|
|
|
|
2014-12-12 16:48:16 +08:00
|
|
|
if (!IS_CHERRYVIEW(dev_priv->dev))
|
|
|
|
vlv_restore_gunit_s0ix_state(dev_priv);
|
2014-05-05 20:19:56 +08:00
|
|
|
|
|
|
|
err = vlv_allow_gt_wake(dev_priv, true);
|
|
|
|
if (!ret)
|
|
|
|
ret = err;
|
|
|
|
|
|
|
|
err = vlv_force_gfx_clock(dev_priv, false);
|
|
|
|
if (!ret)
|
|
|
|
ret = err;
|
|
|
|
|
|
|
|
vlv_check_no_gt_access(dev_priv);
|
|
|
|
|
2014-08-14 01:37:06 +08:00
|
|
|
if (rpm_resume) {
|
|
|
|
intel_init_clock_gating(dev);
|
|
|
|
i915_gem_restore_fences(dev);
|
|
|
|
}
|
2014-05-05 20:19:56 +08:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2014-03-08 07:12:33 +08:00
|
|
|
static int intel_runtime_suspend(struct device *device)
|
2013-12-07 06:32:13 +08:00
|
|
|
{
|
|
|
|
struct pci_dev *pdev = to_pci_dev(device);
|
|
|
|
struct drm_device *dev = pci_get_drvdata(pdev);
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2014-04-15 21:39:45 +08:00
|
|
|
int ret;
|
2013-12-07 06:32:13 +08:00
|
|
|
|
2014-04-15 01:24:36 +08:00
|
|
|
if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
|
2014-04-15 01:24:29 +08:00
|
|
|
return -ENODEV;
|
|
|
|
|
2014-08-26 18:26:56 +08:00
|
|
|
if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
|
|
|
|
return -ENODEV;
|
|
|
|
|
2013-12-07 06:32:13 +08:00
|
|
|
DRM_DEBUG_KMS("Suspending device\n");
|
|
|
|
|
2014-05-08 00:57:49 +08:00
|
|
|
/*
|
|
|
|
* We could deadlock here in case another thread holding struct_mutex
|
|
|
|
* calls RPM suspend concurrently, since the RPM suspend will wait
|
|
|
|
* first for this RPM suspend to finish. In this case the concurrent
|
|
|
|
* RPM resume will be followed by its RPM suspend counterpart. Still
|
|
|
|
* for consistency return -EAGAIN, which will reschedule this suspend.
|
|
|
|
*/
|
|
|
|
if (!mutex_trylock(&dev->struct_mutex)) {
|
|
|
|
DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
|
|
|
|
/*
|
|
|
|
* Bump the expiration timestamp, otherwise the suspend won't
|
|
|
|
* be rescheduled.
|
|
|
|
*/
|
|
|
|
pm_runtime_mark_last_busy(device);
|
|
|
|
|
|
|
|
return -EAGAIN;
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
* We are safe here against re-faults, since the fault handler takes
|
|
|
|
* an RPM reference.
|
|
|
|
*/
|
|
|
|
i915_gem_release_all_mmaps(dev_priv);
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
|
2014-10-31 01:59:31 +08:00
|
|
|
intel_suspend_gt_powersave(dev);
|
2014-11-19 21:30:05 +08:00
|
|
|
intel_runtime_pm_disable_interrupts(dev_priv);
|
2014-04-15 01:24:37 +08:00
|
|
|
|
2014-08-14 01:37:05 +08:00
|
|
|
ret = intel_suspend_complete(dev_priv);
|
2014-04-15 21:39:45 +08:00
|
|
|
if (ret) {
|
|
|
|
DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
|
2014-09-30 16:56:44 +08:00
|
|
|
intel_runtime_pm_enable_interrupts(dev_priv);
|
2014-04-15 21:39:45 +08:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
drm/i915: make PC8 be part of runtime PM suspend/resume
Currently, when our driver becomes idle for i915.pc8_timeout (default:
5s) we enable PC8, so we save some power, but not everything we can.
Then, while PC8 is enabled, if we stay idle for more
autosuspend_delay_ms (default: 10s) we'll enter runtime PM and put the
graphics device in D3 state, saving even more power. The two features
are separate things with increasing levels of power savings, but if we
disable PC8 we'll never get into D3.
While from the modularity point of view it would be nice to keep these
features as separate, we have reasons to merge them:
- We are not aware of anybody wanting a "PC8 without D3" environment.
- If we keep both features as separate, we'll have to to test both
PC8 and PC8+D3 code paths. We're already having a major pain to
make QA do automated testing of just one thing, testing both paths
will cost even more.
- Only Haswell+ supports PC8, so if we want to add runtime PM support
to, for example, IVB, we'll have to copy some code from the PC8
feature to runtime PM, so merging both features as a single thing
will make it easier for enabling runtime PM on other platforms.
This patch only does the very basic steps required to have PC8 and
runtime PM merged on a single feature: the next patches will take care
of cleaning up everything.
v2: - Rebase.
v3: - Rebase.
- Fully remove the deprecated i915 params since Daniel doesn't
consider them as part of the ABI.
v4: - Rebase.
- Fix typo in the commit message.
v5: - Rebase, again.
- Add a huge comment explaining the different forcewake usage
(Chris, Daniel).
- Use open-coded forcewake functions (Daniel).
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-03-08 07:08:05 +08:00
|
|
|
|
2015-01-27 00:03:03 +08:00
|
|
|
cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
|
2015-01-16 17:34:34 +08:00
|
|
|
intel_uncore_forcewake_reset(dev, false);
|
2013-12-07 06:32:13 +08:00
|
|
|
dev_priv->pm.suspended = true;
|
2014-01-15 07:36:15 +08:00
|
|
|
|
|
|
|
/*
|
2014-08-22 04:09:38 +08:00
|
|
|
* FIXME: We really should find a document that references the arguments
|
|
|
|
* used below!
|
2014-01-15 07:36:15 +08:00
|
|
|
*/
|
2014-08-22 04:09:38 +08:00
|
|
|
if (IS_HASWELL(dev)) {
|
|
|
|
/*
|
|
|
|
* current versions of firmware which depend on this opregion
|
|
|
|
* notification have repurposed the D1 definition to mean
|
|
|
|
* "runtime suspended" vs. what you would normally expect (D3)
|
|
|
|
* to distinguish it from notifications that might be sent via
|
|
|
|
* the suspend path.
|
|
|
|
*/
|
|
|
|
intel_opregion_notify_adapter(dev, PCI_D1);
|
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
|
|
|
|
* being detected, and the call we do at intel_runtime_resume()
|
|
|
|
* won't be able to restore them. Since PCI_D3hot matches the
|
|
|
|
* actual specification and appears to be working, use it. Let's
|
|
|
|
* assume the other non-Haswell platforms will stay the same as
|
|
|
|
* Broadwell.
|
|
|
|
*/
|
|
|
|
intel_opregion_notify_adapter(dev, PCI_D3hot);
|
|
|
|
}
|
2013-12-07 06:32:13 +08:00
|
|
|
|
2015-01-16 17:34:40 +08:00
|
|
|
assert_forcewakes_inactive(dev_priv);
|
2015-01-16 17:34:34 +08:00
|
|
|
|
drm/i915: make PC8 be part of runtime PM suspend/resume
Currently, when our driver becomes idle for i915.pc8_timeout (default:
5s) we enable PC8, so we save some power, but not everything we can.
Then, while PC8 is enabled, if we stay idle for more
autosuspend_delay_ms (default: 10s) we'll enter runtime PM and put the
graphics device in D3 state, saving even more power. The two features
are separate things with increasing levels of power savings, but if we
disable PC8 we'll never get into D3.
While from the modularity point of view it would be nice to keep these
features as separate, we have reasons to merge them:
- We are not aware of anybody wanting a "PC8 without D3" environment.
- If we keep both features as separate, we'll have to to test both
PC8 and PC8+D3 code paths. We're already having a major pain to
make QA do automated testing of just one thing, testing both paths
will cost even more.
- Only Haswell+ supports PC8, so if we want to add runtime PM support
to, for example, IVB, we'll have to copy some code from the PC8
feature to runtime PM, so merging both features as a single thing
will make it easier for enabling runtime PM on other platforms.
This patch only does the very basic steps required to have PC8 and
runtime PM merged on a single feature: the next patches will take care
of cleaning up everything.
v2: - Rebase.
v3: - Rebase.
- Fully remove the deprecated i915 params since Daniel doesn't
consider them as part of the ABI.
v4: - Rebase.
- Fix typo in the commit message.
v5: - Rebase, again.
- Add a huge comment explaining the different forcewake usage
(Chris, Daniel).
- Use open-coded forcewake functions (Daniel).
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-03-08 07:08:05 +08:00
|
|
|
DRM_DEBUG_KMS("Device suspended\n");
|
2013-12-07 06:32:13 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-03-08 07:12:33 +08:00
|
|
|
static int intel_runtime_resume(struct device *device)
|
2013-12-07 06:32:13 +08:00
|
|
|
{
|
|
|
|
struct pci_dev *pdev = to_pci_dev(device);
|
|
|
|
struct drm_device *dev = pci_get_drvdata(pdev);
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2014-10-28 03:54:32 +08:00
|
|
|
int ret = 0;
|
2013-12-07 06:32:13 +08:00
|
|
|
|
2014-08-26 18:26:56 +08:00
|
|
|
if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
|
|
|
|
return -ENODEV;
|
2013-12-07 06:32:13 +08:00
|
|
|
|
|
|
|
DRM_DEBUG_KMS("Resuming device\n");
|
|
|
|
|
2013-12-07 06:34:21 +08:00
|
|
|
intel_opregion_notify_adapter(dev, PCI_D0);
|
2013-12-07 06:32:13 +08:00
|
|
|
dev_priv->pm.suspended = false;
|
|
|
|
|
2014-10-28 03:54:32 +08:00
|
|
|
if (IS_GEN6(dev_priv))
|
|
|
|
intel_init_pch_refclk(dev);
|
2014-11-24 16:07:45 +08:00
|
|
|
|
|
|
|
if (IS_BROXTON(dev))
|
|
|
|
ret = bxt_resume_prepare(dev_priv);
|
2015-04-16 16:52:11 +08:00
|
|
|
else if (IS_SKYLAKE(dev))
|
|
|
|
ret = skl_resume_prepare(dev_priv);
|
2014-10-28 03:54:32 +08:00
|
|
|
else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
|
|
|
|
hsw_disable_pc8(dev_priv);
|
|
|
|
else if (IS_VALLEYVIEW(dev_priv))
|
|
|
|
ret = vlv_resume_prepare(dev_priv, true);
|
|
|
|
|
2014-04-15 21:39:45 +08:00
|
|
|
/*
|
|
|
|
* No point of rolling back things in case of an error, as the best
|
|
|
|
* we can do is to hope that things will still work (and disable RPM).
|
|
|
|
*/
|
2014-04-15 01:24:39 +08:00
|
|
|
i915_gem_init_swizzling(dev);
|
|
|
|
gen6_update_ring_freq(dev);
|
|
|
|
|
2014-09-30 16:56:44 +08:00
|
|
|
intel_runtime_pm_enable_interrupts(dev_priv);
|
2014-10-31 01:59:31 +08:00
|
|
|
intel_enable_gt_powersave(dev);
|
2014-04-15 01:24:37 +08:00
|
|
|
|
2014-04-15 21:39:45 +08:00
|
|
|
if (ret)
|
|
|
|
DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
|
|
|
|
else
|
|
|
|
DRM_DEBUG_KMS("Device resumed\n");
|
|
|
|
|
|
|
|
return ret;
|
2013-12-07 06:32:13 +08:00
|
|
|
}
|
|
|
|
|
2014-08-14 01:37:06 +08:00
|
|
|
/*
|
|
|
|
* This function implements common functionality of runtime and system
|
|
|
|
* suspend sequence.
|
|
|
|
*/
|
2014-08-14 01:37:05 +08:00
|
|
|
static int intel_suspend_complete(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = dev_priv->dev;
|
|
|
|
int ret;
|
|
|
|
|
2014-11-24 16:07:45 +08:00
|
|
|
if (IS_BROXTON(dev))
|
|
|
|
ret = bxt_suspend_complete(dev_priv);
|
2015-04-16 16:52:11 +08:00
|
|
|
else if (IS_SKYLAKE(dev))
|
|
|
|
ret = skl_suspend_complete(dev_priv);
|
2014-11-24 16:07:45 +08:00
|
|
|
else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
|
2014-08-14 01:37:05 +08:00
|
|
|
ret = hsw_suspend_complete(dev_priv);
|
2014-08-26 18:26:56 +08:00
|
|
|
else if (IS_VALLEYVIEW(dev))
|
2014-08-14 01:37:05 +08:00
|
|
|
ret = vlv_suspend_complete(dev_priv);
|
2014-08-26 18:26:56 +08:00
|
|
|
else
|
|
|
|
ret = 0;
|
2014-08-14 01:37:05 +08:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2010-06-06 22:40:20 +08:00
|
|
|
static const struct dev_pm_ops i915_pm_ops = {
|
2014-10-24 00:23:28 +08:00
|
|
|
/*
|
|
|
|
* S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
|
|
|
|
* PMSG_RESUME]
|
|
|
|
*/
|
2011-08-17 03:34:10 +08:00
|
|
|
.suspend = i915_pm_suspend,
|
2014-04-02 00:55:22 +08:00
|
|
|
.suspend_late = i915_pm_suspend_late,
|
|
|
|
.resume_early = i915_pm_resume_early,
|
2011-08-17 03:34:10 +08:00
|
|
|
.resume = i915_pm_resume,
|
2014-10-24 00:23:28 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* S4 event handlers
|
|
|
|
* @freeze, @freeze_late : called (1) before creating the
|
|
|
|
* hibernation image [PMSG_FREEZE] and
|
|
|
|
* (2) after rebooting, before restoring
|
|
|
|
* the image [PMSG_QUIESCE]
|
|
|
|
* @thaw, @thaw_early : called (1) after creating the hibernation
|
|
|
|
* image, before writing it [PMSG_THAW]
|
|
|
|
* and (2) after failing to create or
|
|
|
|
* restore the image [PMSG_RECOVER]
|
|
|
|
* @poweroff, @poweroff_late: called after writing the hibernation
|
|
|
|
* image, before rebooting [PMSG_HIBERNATE]
|
|
|
|
* @restore, @restore_early : called after rebooting and restoring the
|
|
|
|
* hibernation image [PMSG_RESTORE]
|
|
|
|
*/
|
2014-10-24 00:23:24 +08:00
|
|
|
.freeze = i915_pm_suspend,
|
|
|
|
.freeze_late = i915_pm_suspend_late,
|
|
|
|
.thaw_early = i915_pm_resume_early,
|
|
|
|
.thaw = i915_pm_resume,
|
|
|
|
.poweroff = i915_pm_suspend,
|
2015-03-02 19:04:41 +08:00
|
|
|
.poweroff_late = i915_pm_poweroff_late,
|
2014-04-02 00:55:22 +08:00
|
|
|
.restore_early = i915_pm_resume_early,
|
2011-08-17 03:34:10 +08:00
|
|
|
.restore = i915_pm_resume,
|
2014-10-24 00:23:28 +08:00
|
|
|
|
|
|
|
/* S0ix (via runtime suspend) event handlers */
|
2014-03-08 07:12:33 +08:00
|
|
|
.runtime_suspend = intel_runtime_suspend,
|
|
|
|
.runtime_resume = intel_runtime_resume,
|
2009-12-16 13:36:10 +08:00
|
|
|
};
|
|
|
|
|
2012-05-17 19:27:22 +08:00
|
|
|
static const struct vm_operations_struct i915_gem_vm_ops = {
|
2008-11-13 02:03:55 +08:00
|
|
|
.fault = i915_gem_fault,
|
2009-02-12 06:01:46 +08:00
|
|
|
.open = drm_gem_vm_open,
|
|
|
|
.close = drm_gem_vm_close,
|
2008-11-13 02:03:55 +08:00
|
|
|
};
|
|
|
|
|
2011-10-31 22:28:57 +08:00
|
|
|
static const struct file_operations i915_driver_fops = {
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.open = drm_open,
|
|
|
|
.release = drm_release,
|
|
|
|
.unlocked_ioctl = drm_ioctl,
|
|
|
|
.mmap = drm_gem_mmap,
|
|
|
|
.poll = drm_poll,
|
|
|
|
.read = drm_read,
|
|
|
|
#ifdef CONFIG_COMPAT
|
|
|
|
.compat_ioctl = i915_compat_ioctl,
|
|
|
|
#endif
|
|
|
|
.llseek = noop_llseek,
|
|
|
|
};
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
static struct drm_driver driver = {
|
2011-08-26 01:55:54 +08:00
|
|
|
/* Don't use MTRRs here; the Xserver or userspace app should
|
|
|
|
* deal with them for Intel hardware.
|
2005-11-11 20:30:27 +08:00
|
|
|
*/
|
2008-07-31 03:06:12 +08:00
|
|
|
.driver_features =
|
2013-12-11 18:34:33 +08:00
|
|
|
DRIVER_USE_AGP |
|
2013-08-26 00:29:01 +08:00
|
|
|
DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
|
|
|
|
DRIVER_RENDER,
|
2005-11-10 19:16:34 +08:00
|
|
|
.load = i915_driver_load,
|
2007-11-22 12:14:14 +08:00
|
|
|
.unload = i915_driver_unload,
|
2008-07-31 03:06:12 +08:00
|
|
|
.open = i915_driver_open,
|
2005-11-10 19:16:34 +08:00
|
|
|
.lastclose = i915_driver_lastclose,
|
|
|
|
.preclose = i915_driver_preclose,
|
2008-07-31 03:06:12 +08:00
|
|
|
.postclose = i915_driver_postclose,
|
2014-08-29 18:12:43 +08:00
|
|
|
.set_busid = drm_pci_set_busid,
|
2010-01-09 07:45:33 +08:00
|
|
|
|
|
|
|
/* Used in place of i915_pm_ops for non-DRIVER_MODESET */
|
2014-10-24 00:23:27 +08:00
|
|
|
.suspend = i915_suspend_legacy,
|
2014-04-02 00:55:22 +08:00
|
|
|
.resume = i915_resume_legacy,
|
2010-01-09 07:45:33 +08:00
|
|
|
|
2005-07-10 15:31:26 +08:00
|
|
|
.device_is_agp = i915_driver_device_is_agp,
|
2009-02-18 09:08:49 +08:00
|
|
|
#if defined(CONFIG_DEBUG_FS)
|
2009-07-02 10:26:52 +08:00
|
|
|
.debugfs_init = i915_debugfs_init,
|
|
|
|
.debugfs_cleanup = i915_debugfs_cleanup,
|
2009-02-18 09:08:49 +08:00
|
|
|
#endif
|
2008-07-31 03:06:12 +08:00
|
|
|
.gem_free_object = i915_gem_free_object,
|
2008-11-13 02:03:55 +08:00
|
|
|
.gem_vm_ops = &i915_gem_vm_ops,
|
2012-05-10 21:25:09 +08:00
|
|
|
|
|
|
|
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
|
|
|
|
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
|
|
|
|
.gem_prime_export = i915_gem_prime_export,
|
|
|
|
.gem_prime_import = i915_gem_prime_import,
|
|
|
|
|
2011-02-07 10:16:14 +08:00
|
|
|
.dumb_create = i915_gem_dumb_create,
|
2014-12-24 11:11:17 +08:00
|
|
|
.dumb_map_offset = i915_gem_mmap_gtt,
|
2013-07-16 15:12:04 +08:00
|
|
|
.dumb_destroy = drm_gem_dumb_destroy,
|
2005-04-17 06:20:36 +08:00
|
|
|
.ioctls = i915_ioctls,
|
2011-10-31 22:28:57 +08:00
|
|
|
.fops = &i915_driver_fops,
|
2005-11-10 19:16:34 +08:00
|
|
|
.name = DRIVER_NAME,
|
|
|
|
.desc = DRIVER_DESC,
|
|
|
|
.date = DRIVER_DATE,
|
|
|
|
.major = DRIVER_MAJOR,
|
|
|
|
.minor = DRIVER_MINOR,
|
|
|
|
.patchlevel = DRIVER_PATCHLEVEL,
|
2005-04-17 06:20:36 +08:00
|
|
|
};
|
|
|
|
|
2010-12-15 01:16:38 +08:00
|
|
|
static struct pci_driver i915_pci_driver = {
|
|
|
|
.name = DRIVER_NAME,
|
|
|
|
.id_table = pciidlist,
|
|
|
|
.probe = i915_pci_probe,
|
|
|
|
.remove = i915_pci_remove,
|
|
|
|
.driver.pm = &i915_pm_ops,
|
|
|
|
};
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
static int __init i915_init(void)
|
|
|
|
{
|
|
|
|
driver.num_ioctls = i915_max_ioctl;
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 06:24:08 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* If CONFIG_DRM_I915_KMS is set, default to KMS unless
|
|
|
|
* explicitly disabled with the module pararmeter.
|
|
|
|
*
|
|
|
|
* Otherwise, just follow the parameter (defaulting to off).
|
|
|
|
*
|
|
|
|
* Allow optional vga_text_mode_force boot option to override
|
|
|
|
* the default behavior.
|
|
|
|
*/
|
|
|
|
#if defined(CONFIG_DRM_I915_KMS)
|
2014-01-21 17:24:25 +08:00
|
|
|
if (i915.modeset != 0)
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 06:24:08 +08:00
|
|
|
driver.driver_features |= DRIVER_MODESET;
|
|
|
|
#endif
|
2014-01-21 17:24:25 +08:00
|
|
|
if (i915.modeset == 1)
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 06:24:08 +08:00
|
|
|
driver.driver_features |= DRIVER_MODESET;
|
|
|
|
|
|
|
|
#ifdef CONFIG_VGA_CONSOLE
|
2014-01-21 17:24:25 +08:00
|
|
|
if (vgacon_text_force() && i915.modeset == -1)
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 06:24:08 +08:00
|
|
|
driver.driver_features &= ~DRIVER_MODESET;
|
|
|
|
#endif
|
|
|
|
|
2013-11-14 05:11:25 +08:00
|
|
|
if (!(driver.driver_features & DRIVER_MODESET)) {
|
2011-01-23 18:45:14 +08:00
|
|
|
driver.get_vblank_timestamp = NULL;
|
2013-11-14 05:11:25 +08:00
|
|
|
/* Silently fail loading to not upset userspace. */
|
2014-06-02 21:58:30 +08:00
|
|
|
DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
|
2013-11-14 05:11:25 +08:00
|
|
|
return 0;
|
|
|
|
}
|
2011-01-23 18:45:14 +08:00
|
|
|
|
2015-01-23 08:53:12 +08:00
|
|
|
/*
|
|
|
|
* FIXME: Note that we're lying to the DRM core here so that we can get access
|
|
|
|
* to the atomic ioctl and the atomic properties. Only plane operations on
|
|
|
|
* a single CRTC will actually work.
|
|
|
|
*/
|
|
|
|
if (i915.nuclear_pageflip)
|
|
|
|
driver.driver_features |= DRIVER_ATOMIC;
|
|
|
|
|
2010-12-15 01:16:38 +08:00
|
|
|
return drm_pci_init(&driver, &i915_pci_driver);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void __exit i915_exit(void)
|
|
|
|
{
|
2013-11-16 00:16:33 +08:00
|
|
|
if (!(driver.driver_features & DRIVER_MODESET))
|
|
|
|
return; /* Never loaded a driver. */
|
|
|
|
|
2010-12-15 01:16:38 +08:00
|
|
|
drm_pci_exit(&driver, &i915_pci_driver);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
module_init(i915_init);
|
|
|
|
module_exit(i915_exit);
|
|
|
|
|
2014-08-27 18:30:20 +08:00
|
|
|
MODULE_AUTHOR("Tungsten Graphics, Inc.");
|
2014-08-27 18:30:21 +08:00
|
|
|
MODULE_AUTHOR("Intel Corporation");
|
2014-08-27 18:30:20 +08:00
|
|
|
|
2005-09-25 12:28:13 +08:00
|
|
|
MODULE_DESCRIPTION(DRIVER_DESC);
|
2005-04-17 06:20:36 +08:00
|
|
|
MODULE_LICENSE("GPL and additional rights");
|