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dt-bindings: mmc: Convert Cadence SD/SDIO/eMMC controller to json-schema 

Convert the Cadence SD/SDIO/eMMC host controller IP (a.k.a. SD4HC)
binding to DT schema format.

Socionext UniPhier ARM 64-bit SoCs are integrated with this IP.

Cc: Piotr Sroka <piotrs@cadence.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Masahiro Yamada 2020-02-22 23:34:44 +09:00 committed by Rob Herring
parent 82ba499712
commit 06efe64822
2 changed files with 143 additions and 80 deletions
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143
Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/cdns,sdhci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)
maintainers:
- Masahiro Yamada <yamada.masahiro@socionext.com>
- Piotr Sroka <piotrs@cadence.com>
allOf:
- $ref: mmc-controller.yaml
properties:
compatible:
items:
- enum:
- socionext,uniphier-sd4hc
- const: cdns,sd4hc
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
# PHY DLL input delays:
# They are used to delay the data valid window, and align the window to
# sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
# and it is increased by 2.5ns in each step.
cdns,phy-input-delay-sd-highspeed:
description: Value of the delay in the input path for SD high-speed timing
allOf:
- $ref: "/schemas/types.yaml#/definitions/uint32"
- minimum: 0
- maximum: 0x1f
cdns,phy-input-delay-legacy:
description: Value of the delay in the input path for legacy timing
allOf:
- $ref: "/schemas/types.yaml#/definitions/uint32"
- minimum: 0
- maximum: 0x1f
cdns,phy-input-delay-sd-uhs-sdr12:
description: Value of the delay in the input path for SD UHS SDR12 timing
allOf:
- $ref: "/schemas/types.yaml#/definitions/uint32"
- minimum: 0
- maximum: 0x1f
cdns,phy-input-delay-sd-uhs-sdr25:
description: Value of the delay in the input path for SD UHS SDR25 timing
allOf:
- $ref: "/schemas/types.yaml#/definitions/uint32"
- minimum: 0
- maximum: 0x1f
cdns,phy-input-delay-sd-uhs-sdr50:
description: Value of the delay in the input path for SD UHS SDR50 timing
allOf:
- $ref: "/schemas/types.yaml#/definitions/uint32"
- minimum: 0
- maximum: 0x1f
cdns,phy-input-delay-sd-uhs-ddr50:
description: Value of the delay in the input path for SD UHS DDR50 timing
allOf:
- $ref: "/schemas/types.yaml#/definitions/uint32"
- minimum: 0
- maximum: 0x1f
cdns,phy-input-delay-mmc-highspeed:
description: Value of the delay in the input path for MMC high-speed timing
allOf:
- $ref: "/schemas/types.yaml#/definitions/uint32"
- minimum: 0
- maximum: 0x1f
cdns,phy-input-delay-mmc-ddr:
description: Value of the delay in the input path for eMMC high-speed DDR timing
allOf:
- $ref: "/schemas/types.yaml#/definitions/uint32"
- minimum: 0
- maximum: 0x1f
# PHY DLL clock delays:
# Each delay property represents the fraction of the clock period.
# The approximate delay value will be
# (<delay property value>/128)*sdmclk_clock_period.
cdns,phy-dll-delay-sdclk:
description: |
Value of the delay introduced on the sdclk output for all modes except
HS200, HS400 and HS400_ES.
allOf:
- $ref: "/schemas/types.yaml#/definitions/uint32"
- minimum: 0
- maximum: 0x7f
cdns,phy-dll-delay-sdclk-hsmmc:
description: |
Value of the delay introduced on the sdclk output for HS200, HS400 and
HS400_ES speed modes.
allOf:
- $ref: "/schemas/types.yaml#/definitions/uint32"
- minimum: 0
- maximum: 0x7f
cdns,phy-dll-delay-strobe:
description: |
Value of the delay introduced on the dat_strobe input used in
HS400 / HS400_ES speed modes.
allOf:
- $ref: "/schemas/types.yaml#/definitions/uint32"
- minimum: 0
- maximum: 0x7f
required:
- compatible
- reg
- interrupts
- clocks
examples:
- |
emmc: mmc@5a000000 {
compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
reg = <0x5a000000 0x400>;
interrupts = <0 78 4>;
clocks = <&clk 4>;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
cdns,phy-dll-delay-sdclk = <0>;
};

80
Documentation/devicetree/bindings/mmc/sdhci-cadence.txt
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* Cadence SD/SDIO/eMMC Host Controller
Required properties:
- compatible: should be one of the following:
"cdns,sd4hc" - default of the IP
"socionext,uniphier-sd4hc" - for Socionext UniPhier SoCs
- reg: offset and length of the register set for the device.
- interrupts: a single interrupt specifier.
- clocks: phandle to the input clock.
Optional properties:
For eMMC configuration, supported speed modes are not indicated by the SDHCI
Capabilities Register. Instead, the following properties should be specified
if supported. See mmc.txt for details.
- mmc-ddr-1_8v
- mmc-ddr-1_2v
- mmc-hs200-1_8v
- mmc-hs200-1_2v
- mmc-hs400-1_8v
- mmc-hs400-1_2v
Some PHY delays can be configured by following properties.
PHY DLL input delays:
They are used to delay the data valid window, and align the window
to sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
and it is increased by 2.5ns in each step.
- cdns,phy-input-delay-sd-highspeed:
Value of the delay in the input path for SD high-speed timing
Valid range = [0:0x1F].
- cdns,phy-input-delay-legacy:
Value of the delay in the input path for legacy timing
Valid range = [0:0x1F].
- cdns,phy-input-delay-sd-uhs-sdr12:
Value of the delay in the input path for SD UHS SDR12 timing
Valid range = [0:0x1F].
- cdns,phy-input-delay-sd-uhs-sdr25:
Value of the delay in the input path for SD UHS SDR25 timing
Valid range = [0:0x1F].
- cdns,phy-input-delay-sd-uhs-sdr50:
Value of the delay in the input path for SD UHS SDR50 timing
Valid range = [0:0x1F].
- cdns,phy-input-delay-sd-uhs-ddr50:
Value of the delay in the input path for SD UHS DDR50 timing
Valid range = [0:0x1F].
- cdns,phy-input-delay-mmc-highspeed:
Value of the delay in the input path for MMC high-speed timing
Valid range = [0:0x1F].
- cdns,phy-input-delay-mmc-ddr:
Value of the delay in the input path for eMMC high-speed DDR timing
Valid range = [0:0x1F].
PHY DLL clock delays:
Each delay property represents the fraction of the clock period.
The approximate delay value will be
(<delay property value>/128)*sdmclk_clock_period.
- cdns,phy-dll-delay-sdclk:
Value of the delay introduced on the sdclk output
for all modes except HS200, HS400 and HS400_ES.
Valid range = [0:0x7F].
- cdns,phy-dll-delay-sdclk-hsmmc:
Value of the delay introduced on the sdclk output
for HS200, HS400 and HS400_ES speed modes.
Valid range = [0:0x7F].
- cdns,phy-dll-delay-strobe:
Value of the delay introduced on the dat_strobe input
used in HS400 / HS400_ES speed modes.
Valid range = [0:0x7F].
Example:
emmc: sdhci@5a000000 {
compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
reg = <0x5a000000 0x400>;
interrupts = <0 78 4>;
clocks = <&clk 4>;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
cdns,phy-dll-delay-sdclk = <0>;
};