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i.MX device tree changes for 3.16: 

- New board support: imx35-pdk, imx51-digi-connectcore, imx6dl-phytec,
    imx6dl-riotboard, and vf610-colibri.
  - Improve device tree support for imx51-babbage and eukrea-cpuimx51 to
    get the same level support as board files, so that we can kill the
    board files.
  - Quite some updates on imx27-phytec-phycore board support from
    Alexander Shiyan
  - Enable USB, sound and touchscreen on the eukrea imx25/35/51 boards,
    from Denis Carikli
  - Quite a lot of patches from Fabio Estevam, updating Freescale
    imx25-pdk and imx27-pdk board support
  - Correct USB device configuration for imx25/35
  - Fixes i2c4 device node in imx6dl.dtsi regarding to compatible string
    and clock data
  - Enable HDMI, TVE, LVDS display support on a bunch of imx5/6 boards
  - Update PCIe to the new binding and enable PCIe support on
    imx6qdl-sabresd board
  - A couple of imx6q-dmo-edmqmx6 updates from Lucas Stach, adding pfuze
    irq gpio and SPI flash
  - Enable CODA7541 VPU for i.MX53
  - A series of updates on imx6qdl-phytec boards from Philipp Zabel
  - Small cleanups and fixes on board imx28-duckbill - Michael Heimpold
  - Add stdout-path property to i.MX boards
  - Karo TX25 board updates from Sascha Hauer
  - Enable pwm and sdhc devices for board vf610-twr
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Merge tag 'imx-dt-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt

Merge "ARM: imx: device tree changes for 3.16" from Shawn Guo:

i.MX device tree changes for 3.16:
 - New board support: imx35-pdk, imx51-digi-connectcore, imx6dl-phytec,
   imx6dl-riotboard, and vf610-colibri.
 - Improve device tree support for imx51-babbage and eukrea-cpuimx51 to
   get the same level support as board files, so that we can kill the
   board files.
 - Quite some updates on imx27-phytec-phycore board support from
   Alexander Shiyan
 - Enable USB, sound and touchscreen on the eukrea imx25/35/51 boards,
   from Denis Carikli
 - Quite a lot of patches from Fabio Estevam, updating Freescale
   imx25-pdk and imx27-pdk board support
 - Correct USB device configuration for imx25/35
 - Fixes i2c4 device node in imx6dl.dtsi regarding to compatible string
   and clock data
 - Enable HDMI, TVE, LVDS display support on a bunch of imx5/6 boards
 - Update PCIe to the new binding and enable PCIe support on
   imx6qdl-sabresd board
 - A couple of imx6q-dmo-edmqmx6 updates from Lucas Stach, adding pfuze
   irq gpio and SPI flash
 - Enable CODA7541 VPU for i.MX53
 - A series of updates on imx6qdl-phytec boards from Philipp Zabel
 - Small cleanups and fixes on board imx28-duckbill - Michael Heimpold
 - Add stdout-path property to i.MX boards
 - Karo TX25 board updates from Sascha Hauer
 - Enable pwm and sdhc devices for board vf610-twr

* tag 'imx-dt-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (105 commits)
  ARM: dts: imx35-pdk: Fix memory region description
  ARM: dts: imx51-eukrea-mbimxsd51-baseboard: Add CAN support
  ARM: dts: imx6: add new board RIoTboard
  ARM: dts: imx6: i2c4 cleanup
  ARM: dts: imx6: edmqmx6: add vcc and vio power supplies to stmpe
  ARM: dts: Karo TX25: use hardware ecc
  ARM: dts: Karo TX25: Add phy reset gpio and supply for FEC
  ARM: dts: Karo TX25: Add pinctrl nodes
  ARM: dts: i.MX25: Add IRAM node
  ARM: dts: i.MX25: Add mmc aliases
  ARM: dts: i.MX51 babbage: Fix FEC pad ctrl settings
  ARM: dts: imx6qdl-sabresd: Add USDHC4 support
  ARM: imx: add HDMI support for SolidRun HummingBoard and Cubox-i
  ARM: dts: imx6: edmqmx6: add SPI bus and flash
  ARM: dts: imx6: edmqmx6: add pinctrl for pfuze irq gpio
  ARM: dts: imx6q-udoo: Add HDMI support
  ARM: dts: Add stdout-path property to i.MX boards
  ARM: dts: imx: Fix LVDS mapping for Ventana GW52xx
  ARM: dts: imx: add LVDS backlight for Ventana
  ARM: dts: imx6qdl-sabresd: remove power-on gpio from pcie
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2014-05-21 14:59:21 -07:00
parent a59a591104 c6f0b878f9
commit 072a4fd2b1
55 changed files with 3260 additions and 541 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/vendor-prefixes.txt
View File

@ -125,6 +125,7 @@ stericsson ST-Ericsson
synology Synology, Inc. synology Synology, Inc.
ti Texas Instruments ti Texas Instruments
tlm Trusted Logic Mobility tlm Trusted Logic Mobility
toradex Toradex AG
toshiba Toshiba Corporation toshiba Toshiba Corporation
toumaz Toumaz toumaz Toumaz
usi Universal Scientifc Industrial Co., Ltd. usi Universal Scientifc Industrial Co., Ltd.

5
arch/arm/boot/dts/Makefile
View File

@ -157,10 +157,12 @@ dtb-$(CONFIG_ARCH_MXC) += \
imx27-phytec-phycard-s-rdk.dtb \ imx27-phytec-phycard-s-rdk.dtb \
imx31-bug.dtb \ imx31-bug.dtb \
imx35-eukrea-mbimxsd35-baseboard.dtb \ imx35-eukrea-mbimxsd35-baseboard.dtb \
imx35-pdk.dtb \
imx50-evk.dtb \ imx50-evk.dtb \
imx51-apf51.dtb \ imx51-apf51.dtb \
imx51-apf51dev.dtb \ imx51-apf51dev.dtb \
imx51-babbage.dtb \ imx51-babbage.dtb \
imx51-digi-connectcore-jsk.dtb \
imx51-eukrea-mbimxsd51-baseboard.dtb \ imx51-eukrea-mbimxsd51-baseboard.dtb \
imx53-ard.dtb \ imx53-ard.dtb \
imx53-m53evk.dtb \ imx53-m53evk.dtb \
@ -179,6 +181,8 @@ dtb-$(CONFIG_ARCH_MXC) += \
imx6dl-gw54xx.dtb \ imx6dl-gw54xx.dtb \
imx6dl-hummingboard.dtb \ imx6dl-hummingboard.dtb \
imx6dl-nitrogen6x.dtb \ imx6dl-nitrogen6x.dtb \
imx6dl-phytec-pbab01.dtb \
imx6dl-riotboard.dtb \
imx6dl-sabreauto.dtb \ imx6dl-sabreauto.dtb \
imx6dl-sabrelite.dtb \ imx6dl-sabrelite.dtb \
imx6dl-sabresd.dtb \ imx6dl-sabresd.dtb \
@ -203,6 +207,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
imx6q-udoo.dtb \ imx6q-udoo.dtb \
imx6q-wandboard.dtb \ imx6q-wandboard.dtb \
imx6sl-evk.dtb \ imx6sl-evk.dtb \
vf610-colibri.dtb \
vf610-cosmic.dtb \ vf610-cosmic.dtb \
vf610-twr.dtb vf610-twr.dtb
dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \

13
arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
View File

@ -172,3 +172,16 @@ &uart2 {
fsl,uart-has-rtscts; fsl,uart-has-rtscts;
status = "okay"; status = "okay";
}; };
&usbhost1 {
phy_type = "serial";
dr_mode = "host";
status = "okay";
};
&usbotg {
phy_type = "utmi";
dr_mode = "otg";
external-vbus-divider;
status = "okay";
};

77
arch/arm/boot/dts/imx25-karo-tx25.dts
View File

@ -16,21 +16,98 @@ / {
model = "Ka-Ro TX25"; model = "Ka-Ro TX25";
compatible = "karo,imx25-tx25", "fsl,imx25"; compatible = "karo,imx25-tx25", "fsl,imx25";
chosen {
stdout-path = &uart1;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_fec_phy: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "fec-phy";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 9 0>;
enable-active-high;
};
};
memory { memory {
reg = <0x80000000 0x02000000 0x90000000 0x02000000>; reg = <0x80000000 0x02000000 0x90000000 0x02000000>;
}; };
}; };
&iomuxc {
pinctrl_uart1: uart1grp {
fsl,pins = <
MX25_PAD_UART1_TXD__UART1_TXD 0x80000000
MX25_PAD_UART1_RXD__UART1_RXD 0x80000000
MX25_PAD_UART1_CTS__UART1_CTS 0x80000000
MX25_PAD_UART1_RTS__UART1_RTS 0x80000000
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX25_PAD_D11__GPIO_4_9 0x80000000 /* FEC PHY power on pin */
MX25_PAD_D13__GPIO_4_7 0x80000000 /* FEC reset */
MX25_PAD_FEC_MDC__FEC_MDC 0x80000000
MX25_PAD_FEC_MDIO__FEC_MDIO 0x80000000
MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000
MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000
MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000
MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000
MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000
MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000
>;
};
pinctrl_nfc: nfcgrp {
fsl,pins = <
MX25_PAD_NF_CE0__NF_CE0 0x80000000
MX25_PAD_NFWE_B__NFWE_B 0x80000000
MX25_PAD_NFRE_B__NFRE_B 0x80000000
MX25_PAD_NFALE__NFALE 0x80000000
MX25_PAD_NFCLE__NFCLE 0x80000000
MX25_PAD_NFWP_B__NFWP_B 0x80000000
MX25_PAD_NFRB__NFRB 0x80000000
MX25_PAD_D7__D7 0x80000000
MX25_PAD_D6__D6 0x80000000
MX25_PAD_D5__D5 0x80000000
MX25_PAD_D4__D4 0x80000000
MX25_PAD_D3__D3 0x80000000
MX25_PAD_D2__D2 0x80000000
MX25_PAD_D1__D1 0x80000000
MX25_PAD_D0__D0 0x80000000
>;
};
};
&uart1 { &uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay"; status = "okay";
}; };
&fec { &fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-reset-gpios = <&gpio3 7 0>;
phy-mode = "rmii"; phy-mode = "rmii";
phy-supply = <&reg_fec_phy>;
status = "okay"; status = "okay";
}; };
&nfc { &nfc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nfc>;
nand-on-flash-bbt; nand-on-flash-bbt;
nand-ecc-mode = "hw";
nand-bus-width = <8>;
status = "okay"; status = "okay";
}; };

217
arch/arm/boot/dts/imx25-pdk.dts
View File

@ -10,6 +10,7 @@
*/ */
/dts-v1/; /dts-v1/;
#include <dt-bindings/input/input.h>
#include "imx25.dtsi" #include "imx25.dtsi"
/ { / {
@ -19,18 +20,232 @@ / {
memory { memory {
reg = <0x80000000 0x4000000>; reg = <0x80000000 0x4000000>;
}; };
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_fec_3v3: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "fec-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 3 0>;
enable-active-high;
};
reg_2p5v: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "2P5V";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
};
reg_3p3v: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_can_3v3: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "can-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 6 0>;
};
};
sound {
compatible = "fsl,imx25-pdk-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "imx25-pdk-sgtl5000";
ssi-controller = <&ssi1>;
audio-codec = <&codec>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
mux-int-port = <1>;
mux-ext-port = <4>;
};
}; };
&uart1 { &audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1>;
xceiver-supply = <&reg_can_3v3>;
status = "okay";
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
cd-gpios = <&gpio2 1 0>;
wp-gpios = <&gpio2 0 0>;
status = "okay"; status = "okay";
}; };
&fec { &fec {
phy-mode = "rmii"; phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-supply = <&reg_fec_3v3>;
phy-reset-gpios = <&gpio4 8 0>;
status = "okay"; status = "okay";
}; };
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
codec: sgtl5000@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&clks 129>;
VDDA-supply = <&reg_2p5v>;
VDDIO-supply = <&reg_3p3v>;
};
};
&iomuxc {
imx25-pdk {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX25_PAD_RW__AUD4_TXFS 0xe0
MX25_PAD_OE__AUD4_TXC 0xe0
MX25_PAD_EB0__AUD4_TXD 0xe0
MX25_PAD_EB1__AUD4_RXD 0xe0
>;
};
pinctrl_can1: can1grp {
fsl,pins = <
MX25_PAD_GPIO_A__CAN1_TX 0x0
MX25_PAD_GPIO_B__CAN1_RX 0x0
MX25_PAD_D14__GPIO_4_6 0x80000000
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX25_PAD_SD1_CMD__SD1_CMD 0x80000000
MX25_PAD_SD1_CLK__SD1_CLK 0x80000000
MX25_PAD_SD1_DATA0__SD1_DATA0 0x80000000
MX25_PAD_SD1_DATA1__SD1_DATA1 0x80000000
MX25_PAD_SD1_DATA2__SD1_DATA2 0x80000000
MX25_PAD_SD1_DATA3__SD1_DATA3 0x80000000
MX25_PAD_A14__GPIO_2_0 0x80000000
MX25_PAD_A15__GPIO_2_1 0x80000000
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX25_PAD_FEC_MDC__FEC_MDC 0x80000000
MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0
MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000
MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000
MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000
MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000
MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000
MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0
MX25_PAD_A17__GPIO_2_3 0x80000000
MX25_PAD_D12__GPIO_4_8 0x80000000
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000
MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000
>;
};
pinctrl_kpp: kppgrp {
fsl,pins = <
MX25_PAD_KPP_ROW0__KPP_ROW0 0x80000000
MX25_PAD_KPP_ROW1__KPP_ROW1 0x80000000
MX25_PAD_KPP_ROW2__KPP_ROW2 0x80000000
MX25_PAD_KPP_ROW3__KPP_ROW3 0x80000000
MX25_PAD_KPP_COL0__KPP_COL0 0x80000000
MX25_PAD_KPP_COL1__KPP_COL1 0x80000000
MX25_PAD_KPP_COL2__KPP_COL2 0x80000000
MX25_PAD_KPP_COL3__KPP_COL3 0x80000000
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX25_PAD_UART1_RTS__UART1_RTS 0xe0
MX25_PAD_UART1_CTS__UART1_CTS 0xe0
MX25_PAD_UART1_TXD__UART1_TXD 0x80000000
MX25_PAD_UART1_RXD__UART1_RXD 0xc0
>;
};
};
};
&nfc { &nfc {
nand-on-flash-bbt; nand-on-flash-bbt;
status = "okay"; status = "okay";
}; };
&kpp {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_kpp>;
linux,keymap = <
MATRIX_KEY(0x0, 0x0, KEY_UP)
MATRIX_KEY(0x0, 0x1, KEY_DOWN)
MATRIX_KEY(0x0, 0x2, KEY_VOLUMEDOWN)
MATRIX_KEY(0x0, 0x3, KEY_HOME)
MATRIX_KEY(0x1, 0x0, KEY_RIGHT)
MATRIX_KEY(0x1, 0x1, KEY_LEFT)
MATRIX_KEY(0x1, 0x2, KEY_ENTER)
MATRIX_KEY(0x1, 0x3, KEY_VOLUMEUP)
MATRIX_KEY(0x2, 0x0, KEY_F6)
MATRIX_KEY(0x2, 0x1, KEY_F8)
MATRIX_KEY(0x2, 0x2, KEY_F9)
MATRIX_KEY(0x2, 0x3, KEY_F10)
MATRIX_KEY(0x3, 0x0, KEY_F1)
MATRIX_KEY(0x3, 0x1, KEY_F2)
MATRIX_KEY(0x3, 0x2, KEY_F3)
MATRIX_KEY(0x3, 0x2, KEY_POWER)
>;
status = "okay";
};
&ssi1 {
codec-handle = <&codec>;
fsl,mode = "i2s-slave";
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
fsl,uart-has-rtscts;
status = "okay";
};
&usbhost1 {
phy_type = "serial";
dr_mode = "host";
status = "okay";
};

46
arch/arm/boot/dts/imx25.dtsi
View File

@ -14,6 +14,7 @@
/ { / {
aliases { aliases {
ethernet0 = &fec;
gpio0 = &gpio1; gpio0 = &gpio1;
gpio1 = &gpio2; gpio1 = &gpio2;
gpio2 = &gpio3; gpio2 = &gpio3;
@ -21,6 +22,8 @@ aliases {
i2c0 = &i2c1; i2c0 = &i2c1;
i2c1 = &i2c2; i2c1 = &i2c2;
i2c2 = &i2c3; i2c2 = &i2c3;
mmc0 = &esdhc1;
mmc1 = &esdhc2;
serial0 = &uart1; serial0 = &uart1;
serial1 = &uart2; serial1 = &uart2;
serial2 = &uart3; serial2 = &uart3;
@ -165,9 +168,10 @@ spi1: cspi@43fa4000 {
status = "disabled"; status = "disabled";
}; };
kpp@43fa8000 { kpp: kpp@43fa8000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,imx25-kpp", "fsl,imx21-kpp";
reg = <0x43fa8000 0x4000>; reg = <0x43fa8000 0x4000>;
clocks = <&clks 102>; clocks = <&clks 102>;
clock-names = ""; clock-names = "";
@ -482,23 +486,13 @@ iim: iim@53ff0000 {
clocks = <&clks 99>; clocks = <&clks 99>;
}; };
usbphy1: usbphy@1 {
compatible = "nop-usbphy";
status = "disabled";
};
usbphy2: usbphy@2 {
compatible = "nop-usbphy";
status = "disabled";
};
usbotg: usb@53ff4000 { usbotg: usb@53ff4000 {
compatible = "fsl,imx25-usb", "fsl,imx27-usb"; compatible = "fsl,imx25-usb", "fsl,imx27-usb";
reg = <0x53ff4000 0x0200>; reg = <0x53ff4000 0x0200>;
interrupts = <37>; interrupts = <37>;
clocks = <&clks 9>, <&clks 70>, <&clks 8>; clocks = <&clks 70>;
clock-names = "ipg", "ahb", "per";
fsl,usbmisc = <&usbmisc 0>; fsl,usbmisc = <&usbmisc 0>;
fsl,usbphy = <&usbphy0>;
status = "disabled"; status = "disabled";
}; };
@ -506,9 +500,9 @@ usbhost1: usb@53ff4400 {
compatible = "fsl,imx25-usb", "fsl,imx27-usb"; compatible = "fsl,imx25-usb", "fsl,imx27-usb";
reg = <0x53ff4400 0x0200>; reg = <0x53ff4400 0x0200>;
interrupts = <35>; interrupts = <35>;
clocks = <&clks 9>, <&clks 70>, <&clks 8>; clocks = <&clks 70>;
clock-names = "ipg", "ahb", "per";
fsl,usbmisc = <&usbmisc 1>; fsl,usbmisc = <&usbmisc 1>;
fsl,usbphy = <&usbphy1>;
status = "disabled"; status = "disabled";
}; };
@ -518,7 +512,6 @@ usbmisc: usbmisc@53ff4600 {
clocks = <&clks 9>, <&clks 70>, <&clks 8>; clocks = <&clks 9>, <&clks 70>, <&clks 8>;
clock-names = "ipg", "ahb", "per"; clock-names = "ipg", "ahb", "per";
reg = <0x53ff4600 0x00f>; reg = <0x53ff4600 0x00f>;
status = "disabled";
}; };
dryice@53ffc000 { dryice@53ffc000 {
@ -530,6 +523,11 @@ dryice@53ffc000 {
}; };
}; };
iram: sram@78000000 {
compatible = "mmio-sram";
reg = <0x78000000 0x20000>;
};
emi@80000000 { emi@80000000 {
compatible = "fsl,emi-bus", "simple-bus"; compatible = "fsl,emi-bus", "simple-bus";
#address-cells = <1>; #address-cells = <1>;
@ -550,4 +548,20 @@ nfc: nand@bb000000 {
}; };
}; };
}; };
usbphy {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
usbphy0: usb-phy@0 {
reg = <0>;
compatible = "usb-nop-xceiv";
};
usbphy1: usb-phy@1 {
reg = <1>;
compatible = "usb-nop-xceiv";
};
};
}; };

170
arch/arm/boot/dts/imx27-pdk.dts
View File

@ -17,15 +17,181 @@ / {
compatible = "fsl,imx27-pdk", "fsl,imx27"; compatible = "fsl,imx27-pdk", "fsl,imx27";
memory { memory {
reg = <0x0 0x0>; reg = <0xa0000000 0x08000000>;
}; };
usbphy {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
usbphy0: usbphy@0 {
compatible = "usb-nop-xceiv";
reg = <0>;
clocks = <&clks 0>;
clock-names = "main_clk";
};
};
};
&cspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cspi2>;
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
status = "okay";
pmic: mc13783@0 {
compatible = "fsl,mc13783";
reg = <0>;
spi-cs-high;
spi-max-frequency = <1000000>;
interrupt-parent = <&gpio3>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
regulators {
vgen_reg: vgen {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
};
vmmc1_reg: vmmc1 {
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3000000>;
};
gpo1_reg: gpo1 {
regulator-always-on;
regulator-boot-on;
};
gpo3_reg: gpo3 {
regulator-always-on;
regulator-boot-on;
};
};
};
};
&fec {
phy-mode = "mii";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
status = "okay";
};
&kpp {
linux,keymap = <
MATRIX_KEY(0, 0, KEY_UP)
MATRIX_KEY(0, 1, KEY_DOWN)
MATRIX_KEY(1, 0, KEY_RIGHT)
MATRIX_KEY(1, 1, KEY_LEFT)
MATRIX_KEY(1, 2, KEY_ENTER)
MATRIX_KEY(2, 0, KEY_F6)
MATRIX_KEY(2, 1, KEY_F8)
MATRIX_KEY(2, 2, KEY_F9)
MATRIX_KEY(2, 3, KEY_F10)
>;
status = "okay";
};
&nfc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
nand-ecc-mode = "hw";
nand-on-flash-bbt;
status = "okay";
}; };
&uart1 { &uart1 {
fsl,uart-has-rtscts; fsl,uart-has-rtscts;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay"; status = "okay";
}; };
&fec { &usbotg {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
dr_mode = "otg";
fsl,usbphy = <&usbphy0>;
phy_type = "ulpi";
status = "okay"; status = "okay";
}; };
&iomuxc {
imx27-pdk {
pinctrl_cspi2: cspi2grp {
fsl,pins = <
MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0
MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0
MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0
MX27_PAD_CSPI2_SS0__GPIO4_21 0x0 /* SPI2 CS0 */
MX27_PAD_TOUT__GPIO3_14 0x0 /* PMIC IRQ */
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX27_PAD_SD3_CMD__FEC_TXD0 0x0
MX27_PAD_SD3_CLK__FEC_TXD1 0x0
MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
MX27_PAD_ATA_DATA7__FEC_MDC 0x0
MX27_PAD_ATA_DATA8__FEC_CRS 0x0
MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
MX27_PAD_ATA_DATA13__FEC_COL 0x0
MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
>;
};
pinctrl_nand: nandgrp {
fsl,pins = <
MX27_PAD_NFRB__NFRB 0x0
MX27_PAD_NFCLE__NFCLE 0x0
MX27_PAD_NFWP_B__NFWP_B 0x0
MX27_PAD_NFCE_B__NFCE_B 0x0
MX27_PAD_NFALE__NFALE 0x0
MX27_PAD_NFRE_B__NFRE_B 0x0
MX27_PAD_NFWE_B__NFWE_B 0x0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX27_PAD_UART1_TXD__UART1_TXD 0x0
MX27_PAD_UART1_RXD__UART1_RXD 0x0
MX27_PAD_UART1_CTS__UART1_CTS 0x0
MX27_PAD_UART1_RTS__UART1_RTS 0x0
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
>;
};
};
};

4
arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
View File

@ -15,6 +15,10 @@ / {
model = "Phytec pca100 rapid development kit"; model = "Phytec pca100 rapid development kit";
compatible = "phytec,imx27-pca100-rdk", "phytec,imx27-pca100", "fsl,imx27"; compatible = "phytec,imx27-pca100-rdk", "phytec,imx27-pca100", "fsl,imx27";
chosen {
stdout-path = &uart1;
};
display: display { display: display {
model = "Primeview-PD050VL1"; model = "Primeview-PD050VL1";
native-mode = <&timing0>; native-mode = <&timing0>;

116
arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
View File

@ -12,14 +12,79 @@
/ { / {
model = "Phytec pcm970"; model = "Phytec pcm970";
compatible = "phytec,imx27-pcm970", "phytec,imx27-pcm038", "fsl,imx27"; compatible = "phytec,imx27-pcm970", "phytec,imx27-pcm038", "fsl,imx27";
chosen {
stdout-path = &uart1;
};
display0: LQ035Q7 {
model = "Sharp-LQ035Q7";
native-mode = <&timing0>;
bits-per-pixel = <16>;
fsl,pcr = <0xf00080c0>;
display-timings {
timing0: 240x320 {
clock-frequency = <5500000>;
hactive = <240>;
vactive = <320>;
hback-porch = <5>;
hsync-len = <7>;
hfront-porch = <16>;
vback-porch = <7>;
vsync-len = <1>;
vfront-porch = <9>;
pixelclk-active = <1>;
hsync-active = <1>;
vsync-active = <1>;
de-active = <0>;
};
};
};
regulators {
regulator@2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_csien>;
reg = <2>;
regulator-name = "CSI_EN";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 24 GPIO_ACTIVE_LOW>;
regulator-always-on;
};
};
usbphy {
usbphy2: usbphy@2 {
compatible = "usb-nop-xceiv";
reg = <2>;
vcc-supply = <&reg_5v0>;
clocks = <&clks 0>;
clock-names = "main_clk";
};
};
}; };
&cspi1 { &cspi1 {
pinctrl-0 = <&pinctrl_cspi1>, <&pinctrl_cspi1cs1>;
fsl,spi-num-chipselects = <2>; fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>, cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>,
<&gpio4 27 GPIO_ACTIVE_LOW>; <&gpio4 27 GPIO_ACTIVE_LOW>;
}; };
&fb {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_imxfb1>;
display = <&display0>;
lcd-supply = <&reg_5v0>;
fsl,dmacr = <0x00020010>;
fsl,lscr1 = <0x00120300>;
fsl,lpccr = <0x00a903ff>;
status = "okay";
};
&i2c1 { &i2c1 {
clock-frequency = <400000>; clock-frequency = <400000>;
pinctrl-names = "default"; pinctrl-names = "default";
@ -36,6 +101,50 @@ camgpio: pca9536@41 {
&iomuxc { &iomuxc {
imx27_phycore_rdk { imx27_phycore_rdk {
pinctrl_csien: csiengrp {
fsl,pins = <
MX27_PAD_USB_OC_B__GPIO2_24 0x0
>;
};
pinctrl_cspi1cs1: cspi1cs1grp {
fsl,pins = <
MX27_PAD_CSPI1_SS1__GPIO4_27 0x0
>;
};
pinctrl_imxfb1: imxfbgrp {
fsl,pins = <
MX27_PAD_LD0__LD0 0x0
MX27_PAD_LD1__LD1 0x0
MX27_PAD_LD2__LD2 0x0
MX27_PAD_LD3__LD3 0x0
MX27_PAD_LD4__LD4 0x0
MX27_PAD_LD5__LD5 0x0
MX27_PAD_LD6__LD6 0x0
MX27_PAD_LD7__LD7 0x0
MX27_PAD_LD8__LD8 0x0
MX27_PAD_LD9__LD9 0x0
MX27_PAD_LD10__LD10 0x0
MX27_PAD_LD11__LD11 0x0
MX27_PAD_LD12__LD12 0x0
MX27_PAD_LD13__LD13 0x0
MX27_PAD_LD14__LD14 0x0
MX27_PAD_LD15__LD15 0x0
MX27_PAD_LD16__LD16 0x0
MX27_PAD_LD17__LD17 0x0
MX27_PAD_CLS__CLS 0x0
MX27_PAD_CONTRAST__CONTRAST 0x0
MX27_PAD_LSCLK__LSCLK 0x0
MX27_PAD_OE_ACD__OE_ACD 0x0
MX27_PAD_PS__PS 0x0
MX27_PAD_REV__REV 0x0
MX27_PAD_SPL_SPR__SPL_SPR 0x0
MX27_PAD_HSYNC__HSYNC 0x0
MX27_PAD_VSYNC__VSYNC 0x0
>;
};
pinctrl_i2c1: i2c1grp { pinctrl_i2c1: i2c1grp {
/* Add pullup to DATA line */ /* Add pullup to DATA line */
fsl,pins = < fsl,pins = <
@ -193,19 +302,16 @@ &usbh2 {
dr_mode = "host"; dr_mode = "host";
phy_type = "ulpi"; phy_type = "ulpi";
vbus-supply = <&reg_5v0>; vbus-supply = <&reg_5v0>;
fsl,usbphy = <&usbphy2>;
disable-over-current; disable-over-current;
status = "okay"; status = "okay";
}; };
&usbphy2 {
vcc-supply = <&reg_5v0>;
};
&weim { &weim {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_weim>; pinctrl-0 = <&pinctrl_weim>;
can@d4000000 { can@4,0 {
compatible = "nxp,sja1000"; compatible = "nxp,sja1000";
reg = <4 0x00000000 0x00000100>; reg = <4 0x00000000 0x00000100>;
interrupt-parent = <&gpio5>; interrupt-parent = <&gpio5>;

53
arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
View File

@ -41,6 +41,20 @@ reg_5v0: regulator@1 {
regulator-max-microvolt = <5000000>; regulator-max-microvolt = <5000000>;
}; };
}; };
usbphy {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
usbphy0: usbphy@0 {
compatible = "usb-nop-xceiv";
reg = <0>;
vcc-supply = <&sw3_reg>;
clocks = <&clks 0>;
clock-names = "main_clk";
};
};
}; };
&audmux { &audmux {
@ -66,9 +80,9 @@ &cspi1 {
status = "okay"; status = "okay";
pmic: mc13783@0 { pmic: mc13783@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mc13783"; compatible = "fsl,mc13783";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
reg = <0>; reg = <0>;
spi-cs-high; spi-cs-high;
spi-max-frequency = <20000000>; spi-max-frequency = <20000000>;
@ -166,7 +180,7 @@ pwgt1spi_reg: pwgt1spi {
&fec { &fec {
phy-mode = "mii"; phy-mode = "mii";
phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_HIGH>; phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_LOW>;
phy-supply = <&reg_3v3>; phy-supply = <&reg_3v3>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>; pinctrl-0 = <&pinctrl_fec1>;
@ -204,7 +218,6 @@ MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* SPI1 CS0 */ MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* SPI1 CS0 */
MX27_PAD_USB_PWR__GPIO2_23 0x0 /* PMIC IRQ */
>; >;
}; };
@ -251,6 +264,21 @@ MX27_PAD_NFWE_B__NFWE_B 0x0
>; >;
}; };
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX27_PAD_USB_PWR__GPIO2_23 0x0 /* PMIC IRQ */
>;
};
pinctrl_ssi1: ssi1grp {
fsl,pins = <
MX27_PAD_SSI1_FS__SSI1_FS 0x0
MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x0
MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x0
MX27_PAD_SSI1_CLK__SSI1_CLK 0x0
>;
};
pinctrl_usbotg: usbotggrp { pinctrl_usbotg: usbotggrp {
fsl,pins = < fsl,pins = <
MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
@ -279,23 +307,28 @@ &nfc {
status = "okay"; status = "okay";
}; };
&ssi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssi1>;
fsl,mode = "i2s-slave";
status = "okay";
};
&usbotg { &usbotg {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>; pinctrl-0 = <&pinctrl_usbotg>;
dr_mode = "otg"; dr_mode = "otg";
phy_type = "ulpi"; phy_type = "ulpi";
fsl,usbphy = <&usbphy0>;
vbus-supply = <&sw3_reg>; vbus-supply = <&sw3_reg>;
disable-over-current;
status = "okay"; status = "okay";
}; };
&usbphy0 {
vcc-supply = <&sw3_reg>;
};
&weim { &weim {
status = "okay"; status = "okay";
nor: nor@c0000000 { nor: nor@0,0 {
compatible = "cfi-flash"; compatible = "cfi-flash";
reg = <0 0x00000000 0x02000000>; reg = <0 0x00000000 0x02000000>;
bank-width = <2>; bank-width = <2>;
@ -305,7 +338,7 @@ nor: nor@c0000000 {
#size-cells = <1>; #size-cells = <1>;
}; };
sram: sram@c8000000 { sram: sram@1,0 {
compatible = "mtd-ram"; compatible = "mtd-ram";
reg = <1 0x00000000 0x00800000>; reg = <1 0x00000000 0x00800000>;
bank-width = <2>; bank-width = <2>;

30
arch/arm/boot/dts/imx27.dtsi
View File

@ -11,11 +11,13 @@
#include "skeleton.dtsi" #include "skeleton.dtsi"
#include "imx27-pinfunc.h" #include "imx27-pinfunc.h"
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
/ { / {
aliases { aliases {
ethernet0 = &fec;
gpio0 = &gpio1; gpio0 = &gpio1;
gpio1 = &gpio2; gpio1 = &gpio2;
gpio2 = &gpio3; gpio2 = &gpio3;
@ -71,26 +73,6 @@ cpu: cpu@0 {
}; };
}; };
usbphy {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
usbphy0: usbphy@0 {
compatible = "usb-nop-xceiv";
reg = <0>;
clocks = <&clks 75>;
clock-names = "main_clk";
};
usbphy2: usbphy@2 {
compatible = "usb-nop-xceiv";
reg = <2>;
clocks = <&clks 75>;
clock-names = "main_clk";
};
};
soc { soc {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
@ -464,9 +446,8 @@ usbotg: usb@10024000 {
compatible = "fsl,imx27-usb"; compatible = "fsl,imx27-usb";
reg = <0x10024000 0x200>; reg = <0x10024000 0x200>;
interrupts = <56>; interrupts = <56>;
clocks = <&clks 15>; clocks = <&clks 75>;
fsl,usbmisc = <&usbmisc 0>; fsl,usbmisc = <&usbmisc 0>;
fsl,usbphy = <&usbphy0>;
status = "disabled"; status = "disabled";
}; };
@ -474,7 +455,7 @@ usbh1: usb@10024200 {
compatible = "fsl,imx27-usb"; compatible = "fsl,imx27-usb";
reg = <0x10024200 0x200>; reg = <0x10024200 0x200>;
interrupts = <54>; interrupts = <54>;
clocks = <&clks 15>; clocks = <&clks 75>;
fsl,usbmisc = <&usbmisc 1>; fsl,usbmisc = <&usbmisc 1>;
status = "disabled"; status = "disabled";
}; };
@ -483,9 +464,8 @@ usbh2: usb@10024400 {
compatible = "fsl,imx27-usb"; compatible = "fsl,imx27-usb";
reg = <0x10024400 0x200>; reg = <0x10024400 0x200>;
interrupts = <55>; interrupts = <55>;
clocks = <&clks 15>; clocks = <&clks 75>;
fsl,usbmisc = <&usbmisc 2>; fsl,usbmisc = <&usbmisc 2>;
fsl,usbphy = <&usbphy2>;
status = "disabled"; status = "disabled";
}; };

12
arch/arm/boot/dts/imx28-duckbill.dts
View File

@ -25,9 +25,9 @@ apbh@80000000 {
ssp0: ssp@80010000 { ssp0: ssp@80010000 {
compatible = "fsl,imx28-mmc"; compatible = "fsl,imx28-mmc";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&mmc0_8bit_pins_a pinctrl-0 = <&mmc0_4bit_pins_a
&mmc0_cd_cfg &mmc0_sck_cfg>; &mmc0_cd_cfg &mmc0_sck_cfg>;
bus-width = <8>; bus-width = <4>;
vmmc-supply = <&reg_3p3v>; vmmc-supply = <&reg_3p3v>;
status = "okay"; status = "okay";
}; };
@ -39,7 +39,7 @@ pinctrl@80018000 {
hog_pins_a: hog@0 { hog_pins_a: hog@0 {
reg = <0>; reg = <0>;
fsl,pinmux-ids = < fsl,pinmux-ids = <
MX28_PAD_ENET0_RX_CLK__GPIO_4_13 /* PHY Reset */ MX28_PAD_SSP0_DATA7__GPIO_2_7 /* PHY Reset */
>; >;
fsl,drive-strength = <MXS_DRIVE_4mA>; fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>; fsl,voltage = <MXS_VOLTAGE_HIGH>;
@ -82,7 +82,7 @@ mac0: ethernet@800f0000 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&mac0_pins_a>; pinctrl-0 = <&mac0_pins_a>;
phy-supply = <&reg_3p3v>; phy-supply = <&reg_3p3v>;
phy-reset-gpios = <&gpio4 13 0>; phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
phy-reset-duration = <100>; phy-reset-duration = <100>;
status = "okay"; status = "okay";
}; };
@ -110,12 +110,12 @@ leds {
status { status {
label = "duckbill:green:status"; label = "duckbill:green:status";
gpios = <&gpio3 5 0>; gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>;
}; };
failure { failure {
label = "duckbill:red:status"; label = "duckbill:red:status";
gpios = <&gpio3 4 0>; gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
}; };
}; };
}; };

1
arch/arm/boot/dts/imx28.dtsi
View File

@ -9,6 +9,7 @@
* http://www.gnu.org/copyleft/gpl.html * http://www.gnu.org/copyleft/gpl.html
*/ */
#include <dt-bindings/gpio/gpio.h>
#include "skeleton.dtsi" #include "skeleton.dtsi"
#include "imx28-pinfunc.h" #include "imx28-pinfunc.h"

15
arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi
View File

@ -37,6 +37,17 @@ pcf8563@51 {
compatible = "nxp,pcf8563"; compatible = "nxp,pcf8563";
reg = <0x51>; reg = <0x51>;
}; };
tsc2007: tsc2007@48 {
compatible = "ti,tsc2007";
gpios = <&gpio3 2 0>;
interrupt-parent = <&gpio3>;
interrupts = <0x2 0x8>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tsc2007_1>;
reg = <0x48>;
ti,x-plate-ohms = <180>;
};
}; };
&iomuxc { &iomuxc {
@ -70,6 +81,10 @@ MX35_PAD_I2C1_CLK__I2C1_SCL 0x80000000
MX35_PAD_I2C1_DAT__I2C1_SDA 0x80000000 MX35_PAD_I2C1_DAT__I2C1_SDA 0x80000000
>; >;
}; };
pinctrl_tsc2007_1: tsc2007grp-1 {
fsl,pins = <MX35_PAD_ATA_DA2__GPIO3_2 0x80000000>;
};
}; };
}; };

22
arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts
View File

@ -46,6 +46,14 @@ led1 {
linux,default-trigger = "heartbeat"; linux,default-trigger = "heartbeat";
}; };
}; };
sound {
compatible = "eukrea,asoc-tlv320";
eukrea,model = "imx35-eukrea-tlv320aic23";
ssi-controller = <&ssi1>;
fsl,mux-int-port = <1>;
fsl,mux-ext-port = <4>;
};
}; };
&audmux { &audmux {
@ -124,6 +132,7 @@ MX35_PAD_CTS2__UART2_CTS 0x1c5
}; };
&ssi1 { &ssi1 {
codec-handle = <&tlv320aic23>;
fsl,mode = "i2s-slave"; fsl,mode = "i2s-slave";
status = "okay"; status = "okay";
}; };
@ -141,3 +150,16 @@ &uart2 {
fsl,uart-has-rtscts; fsl,uart-has-rtscts;
status = "okay"; status = "okay";
}; };
&usbhost1 {
phy_type = "serial";
dr_mode = "host";
status = "okay";
};
&usbotg {
phy_type = "utmi";
dr_mode = "otg";
external-vbus-divider;
status = "okay";
};

68
arch/arm/boot/dts/imx35-pdk.dts Normal file
View File

@ -0,0 +1,68 @@
/*
* Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
* Copyright 2014 Freescale Semiconductor, Inc.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx35.dtsi"
/ {
model = "Freescale i.MX35 Product Development Kit";
compatible = "fsl,imx35-pdk", "fsl,imx35";
memory {
reg = <0x80000000 0x8000000>,
<0x90000000 0x8000000>;
};
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
status = "okay";
};
&iomuxc {
imx35-pdk {
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000
MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000
MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000
MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000
MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000
MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5
MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5
MX35_PAD_CTS1__UART1_CTS 0x1c5
MX35_PAD_RTS1__UART1_RTS 0x1c5
>;
};
};
};
&nfc {
nand-bus-width = <16>;
nand-ecc-mode = "hw";
nand-on-flash-bbt;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
fsl,uart-has-rtscts;
status = "okay";
};

25
arch/arm/boot/dts/imx35.dtsi
View File

@ -13,6 +13,7 @@
/ { / {
aliases { aliases {
ethernet0 = &fec;
gpio0 = &gpio1; gpio0 = &gpio1;
gpio1 = &gpio2; gpio1 = &gpio2;
gpio2 = &gpio3; gpio2 = &gpio3;
@ -295,9 +296,9 @@ usbotg: usb@53ff4000 {
compatible = "fsl,imx35-usb", "fsl,imx27-usb"; compatible = "fsl,imx35-usb", "fsl,imx27-usb";
reg = <0x53ff4000 0x0200>; reg = <0x53ff4000 0x0200>;
interrupts = <37>; interrupts = <37>;
clocks = <&clks 9>, <&clks 73>, <&clks 28>; clocks = <&clks 73>;
clock-names = "ipg", "ahb", "per";
fsl,usbmisc = <&usbmisc 0>; fsl,usbmisc = <&usbmisc 0>;
fsl,usbphy = <&usbphy0>;
status = "disabled"; status = "disabled";
}; };
@ -305,9 +306,9 @@ usbhost1: usb@53ff4400 {
compatible = "fsl,imx35-usb", "fsl,imx27-usb"; compatible = "fsl,imx35-usb", "fsl,imx27-usb";
reg = <0x53ff4400 0x0200>; reg = <0x53ff4400 0x0200>;
interrupts = <35>; interrupts = <35>;
clocks = <&clks 9>, <&clks 73>, <&clks 28>; clocks = <&clks 73>;
clock-names = "ipg", "ahb", "per";
fsl,usbmisc = <&usbmisc 1>; fsl,usbmisc = <&usbmisc 1>;
fsl,usbphy = <&usbphy1>;
status = "disabled"; status = "disabled";
}; };
@ -356,4 +357,20 @@ weim: weim@b8002000 {
}; };
}; };
}; };
usbphy {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
usbphy0: usb-phy@0 {
reg = <0>;
compatible = "usb-nop-xceiv";
};
usbphy1: usb-phy@1 {
reg = <1>;
compatible = "usb-nop-xceiv";
};
};
}; };

1
arch/arm/boot/dts/imx50.dtsi
View File

@ -17,6 +17,7 @@
/ { / {
aliases { aliases {
ethernet0 = &fec;
gpio0 = &gpio1; gpio0 = &gpio1;
gpio1 = &gpio2; gpio1 = &gpio2;
gpio2 = &gpio3; gpio2 = &gpio3;

380
arch/arm/boot/dts/imx51-babbage.dts
View File

@ -17,10 +17,28 @@ / {
model = "Freescale i.MX51 Babbage Board"; model = "Freescale i.MX51 Babbage Board";
compatible = "fsl,imx51-babbage", "fsl,imx51"; compatible = "fsl,imx51-babbage", "fsl,imx51";
chosen {
stdout-path = &uart1;
};
memory { memory {
reg = <0x90000000 0x20000000>; reg = <0x90000000 0x20000000>;
}; };
clocks {
ckih1 {
clock-frequency = <22579200>;
};
clk_26M: codec_clock {
compatible = "fixed-clock";
reg=<0>;
#clock-cells = <0>;
clock-frequency = <26000000>;
gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
};
};
display0: display@di0 { display0: display@di0 {
compatible = "fsl,imx-parallel-display"; compatible = "fsl,imx-parallel-display";
interface-pix-fmt = "rgb24"; interface-pix-fmt = "rgb24";
@ -82,11 +100,13 @@ display1_in: endpoint {
gpio-keys { gpio-keys {
compatible = "gpio-keys"; compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
power { power {
label = "Power Button"; label = "Power Button";
gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
linux,code = <116>; /* KEY_POWER */ linux,code = <KEY_POWER>;
gpio-key,wakeup; gpio-key,wakeup;
}; };
}; };
@ -102,6 +122,36 @@ led-diagnostic {
}; };
}; };
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usbh1_vbus: regulator@0 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1reg>;
reg = <0>;
regulator-name = "usbh1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usbotg_vbus: regulator@1 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotgreg>;
reg = <1>;
regulator-name = "usbotg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
sound { sound {
compatible = "fsl,imx51-babbage-sgtl5000", compatible = "fsl,imx51-babbage-sgtl5000",
"fsl,imx-audio-sgtl5000"; "fsl,imx-audio-sgtl5000";
@ -116,41 +166,23 @@ sound {
mux-ext-port = <3>; mux-ext-port = <3>;
}; };
clocks { usbphy {
ckih1 { #address-cells = <1>;
clock-frequency = <22579200>; #size-cells = <0>;
}; compatible = "simple-bus";
clk_26M: codec_clock { usbh1phy: usbh1phy@0 {
compatible = "fixed-clock"; compatible = "usb-nop-xceiv";
reg=<0>; reg = <0>;
#clock-cells = <0>; clocks = <&clks IMX5_CLK_DUMMY>;
clock-frequency = <26000000>; clock-names = "main_clk";
gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
}; };
}; };
}; };
&esdhc1 { &audmux {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>; pinctrl-0 = <&pinctrl_audmux>;
fsl,cd-controller;
fsl,wp-controller;
status = "okay";
};
&esdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc2>;
cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
fsl,uart-has-rtscts;
status = "okay"; status = "okay";
}; };
@ -163,9 +195,9 @@ &ecspi1 {
status = "okay"; status = "okay";
pmic: mc13892@0 { pmic: mc13892@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mc13892"; compatible = "fsl,mc13892";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
spi-max-frequency = <6000000>; spi-max-frequency = <6000000>;
spi-cs-high; spi-cs-high;
reg = <0>; reg = <0>;
@ -280,6 +312,53 @@ partition@40000 {
}; };
}; };
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
fsl,cd-controller;
fsl,wp-controller;
status = "okay";
};
&esdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc2>;
cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "mii";
phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
sgtl5000: codec@0a {
compatible = "fsl,sgtl5000";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_clkcodec>;
reg = <0x0a>;
clocks = <&clk_26M>;
VDDA-supply = <&vdig_reg>;
VDDIO-supply = <&vvideo_reg>;
};
};
&ipu_di0_disp0 { &ipu_di0_disp0 {
remote-endpoint = <&display0_in>; remote-endpoint = <&display0_in>;
}; };
@ -288,29 +367,74 @@ &ipu_di1_disp1 {
remote-endpoint = <&display1_in>; remote-endpoint = <&display1_in>;
}; };
&kpp {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_kpp>;
linux,keymap = <
MATRIX_KEY(0, 0, KEY_UP)
MATRIX_KEY(0, 1, KEY_DOWN)
MATRIX_KEY(0, 2, KEY_VOLUMEDOWN)
MATRIX_KEY(0, 3, KEY_HOME)
MATRIX_KEY(1, 0, KEY_RIGHT)
MATRIX_KEY(1, 1, KEY_LEFT)
MATRIX_KEY(1, 2, KEY_ENTER)
MATRIX_KEY(1, 3, KEY_VOLUMEUP)
MATRIX_KEY(2, 0, KEY_F6)
MATRIX_KEY(2, 1, KEY_F8)
MATRIX_KEY(2, 2, KEY_F9)
MATRIX_KEY(2, 3, KEY_F10)
MATRIX_KEY(3, 0, KEY_F1)
MATRIX_KEY(3, 1, KEY_F2)
MATRIX_KEY(3, 2, KEY_F3)
MATRIX_KEY(3, 3, KEY_POWER)
>;
status = "okay";
};
&ssi2 { &ssi2 {
fsl,mode = "i2s-slave"; fsl,mode = "i2s-slave";
status = "okay"; status = "okay";
}; };
&iomuxc { &uart1 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>; pinctrl-0 = <&pinctrl_uart1>;
fsl,uart-has-rtscts;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
fsl,uart-has-rtscts;
status = "okay";
};
&usbh1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
vbus-supply = <&reg_usbh1_vbus>;
fsl,usbphy = <&usbh1phy>;
phy_type = "ulpi";
status = "okay";
};
&usbotg {
dr_mode = "otg";
disable-over-current;
phy_type = "utmi_wide";
vbus-supply = <&reg_usbotg_vbus>;
status = "okay";
};
&iomuxc {
imx51-babbage { imx51-babbage {
pinctrl_hog: hoggrp {
fsl,pins = <
MX51_PAD_GPIO1_0__SD1_CD 0x20d5
MX51_PAD_GPIO1_1__SD1_WP 0x20d5
MX51_PAD_GPIO1_5__GPIO1_5 0x100
MX51_PAD_GPIO1_6__GPIO1_6 0x100
MX51_PAD_EIM_A27__GPIO2_21 0x5
MX51_PAD_CSPI1_SS0__GPIO4_24 0x85
MX51_PAD_CSPI1_SS1__GPIO4_25 0x85
MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000
>;
};
pinctrl_audmux: audmuxgrp { pinctrl_audmux: audmuxgrp {
fsl,pins = < fsl,pins = <
MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
@ -320,11 +444,19 @@ MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
>; >;
}; };
pinctrl_clkcodec: clkcodecgrp {
fsl,pins = <
MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000
>;
};
pinctrl_ecspi1: ecspi1grp { pinctrl_ecspi1: ecspi1grp {
fsl,pins = < fsl,pins = <
MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */
MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 /* CS1 */
>; >;
}; };
@ -336,6 +468,8 @@ MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
MX51_PAD_GPIO1_0__SD1_CD 0x20d5
MX51_PAD_GPIO1_1__SD1_WP 0x20d5
>; >;
}; };
@ -347,29 +481,38 @@ MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
MX51_PAD_GPIO1_5__GPIO1_5 0x100 /* WP */
MX51_PAD_GPIO1_6__GPIO1_6 0x100 /* CD */
>; >;
}; };
pinctrl_fec: fecgrp { pinctrl_fec: fecgrp {
fsl,pins = < fsl,pins = <
MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000 MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5
MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000 MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085
MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000 MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085
MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000 MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085
MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000 MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180
MX51_PAD_EIM_CS5__FEC_CRS 0x80000000 MX51_PAD_EIM_CS5__FEC_CRS 0x00000180
MX51_PAD_NANDF_RB2__FEC_COL 0x80000000 MX51_PAD_NANDF_RB2__FEC_COL 0x00000180
MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x00000180
MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000 MX51_PAD_NANDF_D9__FEC_RDATA0 0x00002180
MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000 MX51_PAD_NANDF_D8__FEC_TDATA0 0x00002004
MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004
MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000 MX51_PAD_NANDF_CS3__FEC_MDC 0x00002004
MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x00002004
MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x00002004
MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x00002004
MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000 MX51_PAD_NANDF_CS7__FEC_TX_EN 0x00002004
MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x00002180
MX51_PAD_EIM_A20__GPIO2_14 0x85 /* Reset */ MX51_PAD_NANDF_D11__FEC_RX_DV 0x000020a4
MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */
>;
};
pinctrl_gpio_keys: gpiokeysgrp {
fsl,pins = <
MX51_PAD_EIM_A27__GPIO2_21 0x5
>; >;
}; };
@ -379,6 +522,13 @@ MX51_PAD_EIM_D22__GPIO2_6 0x80000000
>; >;
}; };
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX51_PAD_EIM_D19__I2C1_SCL 0x400001ed
MX51_PAD_EIM_D16__I2C1_SDA 0x400001ed
>;
};
pinctrl_i2c2: i2c2grp { pinctrl_i2c2: i2c2grp {
fsl,pins = < fsl,pins = <
MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
@ -455,6 +605,12 @@ MX51_PAD_KEY_COL3__KEY_COL3 0xe8
>; >;
}; };
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX51_PAD_GPIO1_8__GPIO1_8 0xe5 /* IRQ */
>;
};
pinctrl_uart1: uart1grp { pinctrl_uart1: uart1grp {
fsl,pins = < fsl,pins = <
MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
@ -479,71 +635,33 @@ MX51_PAD_EIM_D27__UART3_RTS 0x1c5
MX51_PAD_EIM_D24__UART3_CTS 0x1c5 MX51_PAD_EIM_D24__UART3_CTS 0x1c5
>; >;
}; };
pinctrl_usbh1: usbh1grp {
fsl,pins = <
MX51_PAD_USBH1_CLK__USBH1_CLK 0x80000000
MX51_PAD_USBH1_DIR__USBH1_DIR 0x80000000
MX51_PAD_USBH1_NXT__USBH1_NXT 0x80000000
MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x80000000
MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x80000000
MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x80000000
MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x80000000
MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x80000000
MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x80000000
MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x80000000
MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x80000000
>;
};
pinctrl_usbh1reg: usbh1reggrp {
fsl,pins = <
MX51_PAD_EIM_D21__GPIO2_5 0x85
>;
};
pinctrl_usbotgreg: usbotgreggrp {
fsl,pins = <
MX51_PAD_GPIO1_7__GPIO1_7 0x85
>;
};
}; };
}; };
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
fsl,uart-has-rtscts;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
sgtl5000: codec@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&clk_26M>;
VDDA-supply = <&vdig_reg>;
VDDIO-supply = <&vvideo_reg>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "mii";
phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
status = "okay";
};
&kpp {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_kpp>;
linux,keymap = <
MATRIX_KEY(0, 0, KEY_UP)
MATRIX_KEY(0, 1, KEY_DOWN)
MATRIX_KEY(0, 2, KEY_VOLUMEDOWN)
MATRIX_KEY(0, 3, KEY_HOME)
MATRIX_KEY(1, 0, KEY_RIGHT)
MATRIX_KEY(1, 1, KEY_LEFT)
MATRIX_KEY(1, 2, KEY_ENTER)
MATRIX_KEY(1, 3, KEY_VOLUMEUP)
MATRIX_KEY(2, 0, KEY_F6)
MATRIX_KEY(2, 1, KEY_F8)
MATRIX_KEY(2, 2, KEY_F9)
MATRIX_KEY(2, 3, KEY_F10)
MATRIX_KEY(3, 0, KEY_F1)
MATRIX_KEY(3, 1, KEY_F2)
MATRIX_KEY(3, 2, KEY_F3)
MATRIX_KEY(3, 3, KEY_POWER)
>;
status = "okay";
};

108
arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts Normal file
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@ -0,0 +1,108 @@
/*
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include "imx51-digi-connectcore-som.dtsi"
/ {
model = "Digi ConnectCore CC(W)-MX51 JSK";
compatible = "digi,connectcore-ccxmx51-jsk",
"digi,connectcore-ccxmx51-som", "fsl,imx51";
chosen {
linux,stdout-path = &uart1;
};
};
&owire {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_owire>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&usbotg {
dr_mode = "otg";
status = "okay";
};
&usbh1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
dr_mode = "host";
phy_type = "ulpi";
disable-over-current;
status = "okay";
};
&iomuxc {
imx51-digi-connectcore-jsk {
pinctrl_owire: owiregrp {
fsl,pins = <
MX51_PAD_OWIRE_LINE__OWIRE_LINE 0x40000000
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
>;
};
pinctrl_usbh1: usbh1grp {
fsl,pins = <
MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5
MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5
MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5
MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5
MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5
MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5
MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5
MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5
MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5
MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5
MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5
MX51_PAD_USBH1_STP__USBH1_STP 0x1e5
>;
};
};
};

377
arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi Normal file
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@ -0,0 +1,377 @@
/*
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx51.dtsi"
/ {
model = "Digi ConnectCore CC(W)-MX51";
compatible = "digi,connectcore-ccxmx51-som", "fsl,imx51";
memory {
reg = <0x90000000 0x08000000>;
};
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
status = "okay";
pmic: mc13892@0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mc13892>;
compatible = "fsl,mc13892";
spi-max-frequency = <16000000>;
spi-cs-high;
reg = <0>;
interrupt-parent = <&gpio1>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
fsl,mc13xxx-uses-rtc;
regulators {
sw1_reg: sw1 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
sw2_reg: sw2 {
regulator-min-microvolt = <1225000>;
regulator-max-microvolt = <1225000>;
regulator-boot-on;
regulator-always-on;
};
sw3_reg: sw3 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
regulator-always-on;
};
swbst_reg: swbst { };
viohi_reg: viohi {
regulator-always-on;
};
vpll_reg: vpll {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
vdig_reg: vdig {
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
};
vsd_reg: vsd {
regulator-min-microvolt = <3150000>;
regulator-max-microvolt = <3150000>;
regulator-always-on;
};
vusb2_reg: vusb2 {
regulator-min-microvolt = <2600000>;
regulator-max-microvolt = <2600000>;
regulator-always-on;
};
vvideo_reg: vvideo {
regulator-min-microvolt = <2775000>;
regulator-max-microvolt = <2775000>;
regulator-always-on;
};
vaudio_reg: vaudio {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
vcam_reg: vcam {
regulator-min-microvolt = <2750000>;
regulator-max-microvolt = <2750000>;
regulator-always-on;
};
vgen1_reg: vgen1 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
vgen2_reg: vgen2 {
regulator-min-microvolt = <3150000>;
regulator-max-microvolt = <3150000>;
regulator-always-on;
};
vgen3_reg: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
vusb_reg: vusb {
regulator-always-on;
};
gpo1_reg: gpo1 { };
gpo2_reg: gpo2 { };
gpo3_reg: gpo3 { };
gpo4_reg: gpo4 { };
pwgt2spi_reg: pwgt2spi {
regulator-always-on;
};
vcoincell_reg: vcoincell {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
};
};
};
&esdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc2>;
cap-sdio-irq;
enable-sdio-wakeup;
keep-power-in-suspend;
max-frequency = <50000000>;
no-1-8-v;
non-removable;
vmmc-supply = <&gpo4_reg>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "mii";
phy-supply = <&gpo3_reg>;
/* Pins shared with LCD2, keep status disabled */
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clock-frequency = <400000>;
status = "okay";
mma7455l@1d {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mma7455l>;
compatible = "fsl,mma7455l";
reg = <0x1d>;
interrupt-parent = <&gpio1>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH>, <6 IRQ_TYPE_LEVEL_HIGH>;
};
};
&nfc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nfc>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-on-flash-bbt;
status = "okay";
};
&usbotg {
phy_type = "utmi_wide";
disable-over-current;
/* Device role is not known, keep status disabled */
};
&weim {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_weim>;
status = "okay";
lan9221: lan9221@5,0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lan9221>;
compatible = "smsc,lan9221", "smsc,lan9115";
reg = <5 0x00000000 0x1000>;
fsl,weim-cs-timing = <
0x00420081 0x00000000
0x32260000 0x00000000
0x72080f00 0x00000000
>;
clocks = <&clks IMX5_CLK_DUMMY>;
interrupt-parent = <&gpio1>;
interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
phy-mode = "mii";
reg-io-width = <2>;
smsc,irq-push-pull;
vdd33a-supply = <&gpo2_reg>;
vddvario-supply = <&gpo2_reg>;
};
};
&iomuxc {
imx51-digi-connectcore-som {
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */
>;
};
pinctrl_esdhc2: esdhc2grp {
fsl,pins = <
MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed
MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed
>;
};
pinctrl_nfc: nfcgrp {
fsl,pins = <
MX51_PAD_NANDF_D0__NANDF_D0 0x80000000
MX51_PAD_NANDF_D1__NANDF_D1 0x80000000
MX51_PAD_NANDF_D2__NANDF_D2 0x80000000
MX51_PAD_NANDF_D3__NANDF_D3 0x80000000
MX51_PAD_NANDF_D4__NANDF_D4 0x80000000
MX51_PAD_NANDF_D5__NANDF_D5 0x80000000
MX51_PAD_NANDF_D6__NANDF_D6 0x80000000
MX51_PAD_NANDF_D7__NANDF_D7 0x80000000
MX51_PAD_NANDF_ALE__NANDF_ALE 0x80000000
MX51_PAD_NANDF_CLE__NANDF_CLE 0x80000000
MX51_PAD_NANDF_RE_B__NANDF_RE_B 0x80000000
MX51_PAD_NANDF_WE_B__NANDF_WE_B 0x80000000
MX51_PAD_NANDF_WP_B__NANDF_WP_B 0x80000000
MX51_PAD_NANDF_CS0__NANDF_CS0 0x80000000
MX51_PAD_NANDF_RB0__NANDF_RB0 0x80000000
>;
};
pinctrl_lan9221: lan9221grp {
fsl,pins = <
MX51_PAD_GPIO1_9__GPIO1_9 0xe5 /* IRQ */
>;
};
pinctrl_mc13892: mc13892grp {
fsl,pins = <
MX51_PAD_GPIO1_5__GPIO1_5 0xe5 /* IRQ */
>;
};
pinctrl_mma7455l: mma7455lgrp {
fsl,pins = <
MX51_PAD_GPIO1_7__GPIO1_7 0xe5 /* IRQ1 */
MX51_PAD_GPIO1_6__GPIO1_6 0xe5 /* IRQ2 */
>;
};
pinctrl_weim: weimgrp {
fsl,pins = <
MX51_PAD_EIM_DA0__EIM_DA0 0x80000000
MX51_PAD_EIM_DA1__EIM_DA1 0x80000000
MX51_PAD_EIM_DA2__EIM_DA2 0x80000000
MX51_PAD_EIM_DA3__EIM_DA3 0x80000000
MX51_PAD_EIM_DA4__EIM_DA4 0x80000000
MX51_PAD_EIM_DA5__EIM_DA5 0x80000000
MX51_PAD_EIM_DA6__EIM_DA6 0x80000000
MX51_PAD_EIM_DA7__EIM_DA7 0x80000000
MX51_PAD_EIM_DA8__EIM_DA8 0x80000000
MX51_PAD_EIM_DA9__EIM_DA9 0x80000000
MX51_PAD_EIM_DA10__EIM_DA10 0x80000000
MX51_PAD_EIM_DA11__EIM_DA11 0x80000000
MX51_PAD_EIM_DA12__EIM_DA12 0x80000000
MX51_PAD_EIM_DA13__EIM_DA13 0x80000000
MX51_PAD_EIM_DA14__EIM_DA14 0x80000000
MX51_PAD_EIM_DA15__EIM_DA15 0x80000000
MX51_PAD_EIM_A16__EIM_A16 0x80000000
MX51_PAD_EIM_A17__EIM_A17 0x80000000
MX51_PAD_EIM_A18__EIM_A18 0x80000000
MX51_PAD_EIM_A19__EIM_A19 0x80000000
MX51_PAD_EIM_A20__EIM_A20 0x80000000
MX51_PAD_EIM_A21__EIM_A21 0x80000000
MX51_PAD_EIM_A22__EIM_A22 0x80000000
MX51_PAD_EIM_A23__EIM_A23 0x80000000
MX51_PAD_EIM_A24__EIM_A24 0x80000000
MX51_PAD_EIM_A25__EIM_A25 0x80000000
MX51_PAD_EIM_A26__EIM_A26 0x80000000
MX51_PAD_EIM_A27__EIM_A27 0x80000000
MX51_PAD_EIM_D16__EIM_D16 0x80000000
MX51_PAD_EIM_D17__EIM_D17 0x80000000
MX51_PAD_EIM_D18__EIM_D18 0x80000000
MX51_PAD_EIM_D19__EIM_D19 0x80000000
MX51_PAD_EIM_D20__EIM_D20 0x80000000
MX51_PAD_EIM_D21__EIM_D21 0x80000000
MX51_PAD_EIM_D22__EIM_D22 0x80000000
MX51_PAD_EIM_D23__EIM_D23 0x80000000
MX51_PAD_EIM_D24__EIM_D24 0x80000000
MX51_PAD_EIM_D25__EIM_D25 0x80000000
MX51_PAD_EIM_D26__EIM_D26 0x80000000
MX51_PAD_EIM_D27__EIM_D27 0x80000000
MX51_PAD_EIM_D28__EIM_D28 0x80000000
MX51_PAD_EIM_D29__EIM_D29 0x80000000
MX51_PAD_EIM_D30__EIM_D30 0x80000000
MX51_PAD_EIM_D31__EIM_D31 0x80000000
MX51_PAD_EIM_OE__EIM_OE 0x80000000
MX51_PAD_EIM_DTACK__EIM_DTACK 0x80000000
MX51_PAD_EIM_LBA__EIM_LBA 0x80000000
MX51_PAD_EIM_CS5__EIM_CS5 0x80000000 /* CS5 */
>;
};
};
};

11
arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi
View File

@ -42,6 +42,17 @@ pcf8563@51 {
compatible = "nxp,pcf8563"; compatible = "nxp,pcf8563";
reg = <0x51>; reg = <0x51>;
}; };
tsc2007: tsc2007@49 {
compatible = "ti,tsc2007";
gpios = <&gpio4 0 1>;
interrupt-parent = <&gpio4>;
interrupts = <0x0 0x8>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tsc2007_1>;
reg = <0x49>;
ti,x-plate-ohms = <180>;
};
}; };
&iomuxc { &iomuxc {

120
arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
View File

@ -24,6 +24,14 @@ / {
model = "Eukrea CPUIMX51"; model = "Eukrea CPUIMX51";
compatible = "eukrea,mbimxsd51","eukrea,cpuimx51", "fsl,imx51"; compatible = "eukrea,mbimxsd51","eukrea,cpuimx51", "fsl,imx51";
clocks {
clk24M: can_clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
};
gpio_keys { gpio_keys {
compatible = "gpio-keys"; compatible = "gpio-keys";
pinctrl-names = "default"; pinctrl-names = "default";
@ -50,6 +58,23 @@ led1 {
}; };
}; };
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_can: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "CAN_RST";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
startup-delay-us = <20000>;
enable-active-high;
};
};
sound { sound {
compatible = "eukrea,asoc-tlv320"; compatible = "eukrea,asoc-tlv320";
eukrea,model = "imx51-eukrea-tlv320aic23"; eukrea,model = "imx51-eukrea-tlv320aic23";
@ -57,6 +82,20 @@ sound {
fsl,mux-int-port = <2>; fsl,mux-int-port = <2>;
fsl,mux-ext-port = <3>; fsl,mux-ext-port = <3>;
}; };
usbphy {
#address-cells = <1>;
#size-cells = <0>;
compatible = "simple-bus";
usbh1phy: usbh1phy@0 {
compatible = "usb-nop-xceiv";
reg = <0>;
clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
clock-names = "main_clk";
clock-frequency = <19200000>;
};
};
}; };
&audmux { &audmux {
@ -72,6 +111,26 @@ &esdhc1 {
status = "okay"; status = "okay";
}; };
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
status = "okay";
can0: can@0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can>;
compatible = "microchip,mcp2515";
reg = <0>;
clocks = <&clk24M>;
spi-max-frequency = <10000000>;
interrupt-parent = <&gpio1>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
vdd-supply = <&reg_can>;
};
};
&i2c1 { &i2c1 {
tlv320aic23: codec@1a { tlv320aic23: codec@1a {
compatible = "ti,tlv320aic23"; compatible = "ti,tlv320aic23";
@ -90,6 +149,23 @@ MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
>; >;
}; };
pinctrl_can: cangrp {
fsl,pins = <
MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x80000000 /* nReset */
MX51_PAD_GPIO1_1__GPIO1_1 0x80000000 /* IRQ */
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
MX51_PAD_CSPI1_SS0__GPIO4_24 0x80000000 /* CS0 */
>;
};
pinctrl_esdhc1: esdhc1grp { pinctrl_esdhc1: esdhc1grp {
fsl,pins = < fsl,pins = <
MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
@ -151,6 +227,29 @@ pinctrl_reg_lcd_3v3: reg_lcd_3v3 {
MX51_PAD_CSI1_D9__GPIO3_13 0x1f5 MX51_PAD_CSI1_D9__GPIO3_13 0x1f5
>; >;
}; };
pinctrl_usbh1: usbh1grp {
fsl,pins = <
MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5
MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5
MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5
MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5
MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5
MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5
MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5
MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5
MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5
MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5
MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5
MX51_PAD_USBH1_STP__USBH1_STP 0x1e5
>;
};
pinctrl_usbh1_vbus: usbh1-vbusgrp {
fsl,pins = <
MX51_PAD_EIM_CS3__GPIO2_28 0x1f5
>;
};
}; };
}; };
@ -173,3 +272,24 @@ &uart3 {
fsl,uart-has-rtscts; fsl,uart-has-rtscts;
status = "okay"; status = "okay";
}; };
&usbh1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
fsl,usbphy = <&usbh1phy>;
dr_mode = "host";
phy_type = "ulpi";
status = "okay";
};
&usbotg {
dr_mode = "otg";
phy_type = "utmi_wide";
status = "okay";
};
&usbphy0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1_vbus>;
reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
};

3
arch/arm/boot/dts/imx51.dtsi
View File

@ -19,6 +19,7 @@
/ { / {
aliases { aliases {
ethernet0 = &fec;
gpio0 = &gpio1; gpio0 = &gpio1;
gpio1 = &gpio2; gpio1 = &gpio2;
gpio2 = &gpio3; gpio2 = &gpio3;
@ -537,6 +538,8 @@ weim: weim@83fda000 {
}; };
nfc: nand@83fdb000 { nfc: nand@83fdb000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,imx51-nand"; compatible = "fsl,imx51-nand";
reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
interrupts = <8>; interrupts = <8>;

4
arch/arm/boot/dts/imx53-mba53.dts
View File

@ -17,6 +17,10 @@ / {
model = "TQ MBa53 starter kit"; model = "TQ MBa53 starter kit";
compatible = "tq,mba53", "tq,tqma53", "fsl,imx53"; compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";
chosen {
stdout-path = &uart2;
};
backlight { backlight {
compatible = "pwm-backlight"; compatible = "pwm-backlight";
pwms = <&pwm2 0 50000>; pwms = <&pwm2 0 50000>;

21
arch/arm/boot/dts/imx53-qsb-common.dtsi
View File

@ -13,6 +13,10 @@
#include "imx53.dtsi" #include "imx53.dtsi"
/ { / {
chosen {
stdout-path = &uart1;
};
memory { memory {
reg = <0x70000000 0x20000000>, reg = <0x70000000 0x20000000>,
<0xb0000000 0x20000000>; <0xb0000000 0x20000000>;
@ -272,6 +276,14 @@ MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
>; >;
}; };
pinctrl_vga_sync: vgasync-grp {
fsl,pins = <
/* VGA_HSYNC, VSYNC with max drive strength */
MX53_PAD_EIM_OE__IPU_DI1_PIN7 0xe6
MX53_PAD_EIM_RW__IPU_DI1_PIN8 0xe6
>;
};
pinctrl_uart1: uart1grp { pinctrl_uart1: uart1grp {
fsl,pins = < fsl,pins = <
MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
@ -281,6 +293,15 @@ MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
}; };
}; };
&tve {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_vga_sync>;
fsl,tve-mode = "vga";
fsl,hsync-pin = <4>;
fsl,vsync-pin = <6>;
status = "okay";
};
&uart1 { &uart1 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>; pinctrl-0 = <&pinctrl_uart1>;

3
arch/arm/boot/dts/imx53.dtsi
View File

@ -18,6 +18,7 @@
/ { / {
aliases { aliases {
ethernet0 = &fec;
gpio0 = &gpio1; gpio0 = &gpio1;
gpio1 = &gpio2; gpio1 = &gpio2;
gpio2 = &gpio3; gpio2 = &gpio3;
@ -726,8 +727,8 @@ vpu: vpu@63ff4000 {
clocks = <&clks IMX5_CLK_VPU_GATE>, clocks = <&clks IMX5_CLK_VPU_GATE>,
<&clks IMX5_CLK_VPU_GATE>; <&clks IMX5_CLK_VPU_GATE>;
clock-names = "per", "ahb"; clock-names = "per", "ahb";
resets = <&src 1>;
iram = <&ocram>; iram = <&ocram>;
status = "disabled";
}; };
}; };

31
arch/arm/boot/dts/imx6dl-hummingboard.dts
View File

@ -11,6 +11,10 @@ / {
model = "SolidRun HummingBoard DL/Solo"; model = "SolidRun HummingBoard DL/Solo";
compatible = "solidrun,hummingboard", "fsl,imx6dl"; compatible = "solidrun,hummingboard", "fsl,imx6dl";
chosen {
stdout-path = &uart1;
};
ir_recv: ir-receiver { ir_recv: ir-receiver {
compatible = "gpio-ir-receiver"; compatible = "gpio-ir-receiver";
gpios = <&gpio1 2 1>; gpios = <&gpio1 2 1>;
@ -67,6 +71,13 @@ &can1 {
status = "okay"; status = "okay";
}; };
&hdmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_hdmi>;
ddc-i2c-bus = <&i2c2>;
status = "okay";
};
&i2c1 { &i2c1 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_i2c1>; pinctrl-0 = <&pinctrl_hummingboard_i2c1>;
@ -82,6 +93,13 @@ rtc: pcf8523@68 {
*/ */
}; };
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_i2c2>;
status = "okay";
};
&iomuxc { &iomuxc {
hummingboard { hummingboard {
pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 { pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 {
@ -97,6 +115,12 @@ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
>; >;
}; };
pinctrl_hummingboard_hdmi: hummingboard-hdmi {
fsl,pins = <
MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
>;
};
pinctrl_hummingboard_i2c1: hummingboard-i2c1 { pinctrl_hummingboard_i2c1: hummingboard-i2c1 {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
@ -104,6 +128,13 @@ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>; >;
}; };
pinctrl_hummingboard_i2c2: hummingboard-i2c2 {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_hummingboard_spdif: hummingboard-spdif { pinctrl_hummingboard_spdif: hummingboard-spdif {
fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>; fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
}; };

19
arch/arm/boot/dts/imx6dl-phytec-pbab01.dts Normal file
View File

@ -0,0 +1,19 @@
/*
* Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx6dl-phytec-pfla02.dtsi"
#include "imx6qdl-phytec-pbab01.dtsi"
/ {
model = "Phytec phyFLEX-i.MX6 DualLite/Solo Carrier-Board";
compatible = "phytec,imx6dl-pbab01", "phytec,imx6dl-pfla02", "fsl,imx6dl";
};

22
arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi Normal file
View File

@ -0,0 +1,22 @@
/*
* Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include "imx6dl.dtsi"
#include "imx6qdl-phytec-pfla02.dtsi"
/ {
model = "Phytec phyFLEX-i.MX6 DualLite/Solo";
compatible = "phytec,imx6dl-pfla02", "fsl,imx6dl";
memory {
reg = <0x10000000 0x20000000>;
};
};

539
arch/arm/boot/dts/imx6dl-riotboard.dts Normal file
View File

@ -0,0 +1,539 @@
/*
* Copyright 2014 Iain Paton <ipaton0@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "RIoTboard i.MX6S";
compatible = "riot,imx6s-riotboard", "fsl,imx6dl";
memory {
reg = <0x10000000 0x40000000>;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_2p5v: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "2P5V";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
};
reg_3p3v: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_usb_otg_vbus: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 0>;
enable-active-high;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led>;
led0: user1 {
label = "user1";
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
led1: user2 {
label = "user2";
gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};
sound {
compatible = "fsl,imx-audio-sgtl5000";
model = "imx6-riotboard-sgtl5000";
ssi-controller = <&ssi1>;
audio-codec = <&codec>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
mux-int-port = <1>;
mux-ext-port = <3>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio3 31 0>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c2>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
codec: sgtl5000@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&clks 201>;
VDDA-supply = <&reg_2p5v>;
VDDIO-supply = <&reg_3p3v>;
};
pmic: pf0100@08 {
compatible = "fsl,pfuze100";
reg = <0x08>;
interrupt-parent = <&gpio5>;
interrupts = <16 8>;
regulators {
reg_vddcore: sw1ab { /* VDDARM_IN */
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-always-on;
};
reg_vddsoc: sw1c { /* VDDSOC_IN */
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-always-on;
};
reg_gen_3v3: sw2 { /* VDDHIGH_IN */
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_ddr_1v5a: sw3a { /* NVCC_DRAM, NVCC_RGMII */
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-always-on;
};
reg_ddr_1v5b: sw3b { /* NVCC_DRAM, NVCC_RGMII */
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-always-on;
};
reg_ddr_vtt: sw4 { /* MIPI conn */
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-always-on;
};
reg_5v_600mA: swbst { /* not used */
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
reg_snvs_3v: vsnvs { /* VDD_SNVS_IN */
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
vref_reg: vrefddr { /* VREF_DDR */
regulator-boot-on;
regulator-always-on;
};
reg_vgen1_1v5: vgen1 { /* not used */
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
reg_vgen2_1v2_eth: vgen2 { /* pcie ? */
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
regulator-always-on;
};
reg_vgen3_2v8: vgen3 { /* not used */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
reg_vgen4_1v8: vgen4 { /* NVCC_SD3 */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_vgen5_2v5_sgtl: vgen5 { /* Pwr LED & 5V0_delayed enable */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_vgen6_3v3: vgen6 { /* #V#_DELAYED enable, MIPI */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
clocks = <&clks 116>;
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&ssi1 {
fsl,mode = "i2s-slave";
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
};
&usbh1 {
dr_mode = "host";
disable-over-current;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
dr_mode = "otg";
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
cd-gpios = <&gpio1 4 0>;
wp-gpios = <&gpio1 2 0>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
cd-gpios = <&gpio7 0 0>;
wp-gpios = <&gpio7 1 0>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;
vmmc-supply = <&reg_3p3v>;
non-removable;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
imx6-riotboard {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x8000000
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x8000000
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x8000000
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x8000000
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x000b1 /* CS0 */
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x000b1 /* CS1 */
MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1
MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1
MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1 /* CS0 */
MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1
>;
};
pinctrl_ecspi3: ecspi3grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 /* CS0 */
MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x000b1 /* CS1 */
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 /* AR8035 pin strapping: IO voltage: pull up */
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0 /* AR8035 pin strapping: PHYADDR#0: pull down */
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x130b0 /* AR8035 pin strapping: PHYADDR#1: pull down */
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 /* AR8035 pin strapping: MODE#1: pull up */
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 /* AR8035 pin strapping: MODE#3: pull up */
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000 /* GPIO16 -> AR8035 25MHz */
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* AR8035 interrupt */
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1
>;
};
pinctrl_led: ledgrp {
fsl,pins = <
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 /* user led0 */
MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x80000000 /* user led1 */
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */
MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x80000000
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* SD2 CD */
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* SD2 WP */
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3 CD */
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x80000000 /* SD3 WP */
>;
};
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x80000000 /* SD4 RST (eMMC) */
>;
};
};
};

3
arch/arm/boot/dts/imx6dl.dtsi
View File

@ -84,9 +84,10 @@ aips2: aips-bus@02100000 {
i2c4: i2c@021f8000 { i2c4: i2c@021f8000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,imx1-i2c"; compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
reg = <0x021f8000 0x4000>; reg = <0x021f8000 0x4000>;
interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 116>;
status = "disabled"; status = "disabled";
}; };
}; };

40
arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
View File

@ -18,6 +18,10 @@ / {
model = "Data Modul eDM-QMX6 Board"; model = "Data Modul eDM-QMX6 Board";
compatible = "dmo,imx6q-edmqmx6", "fsl,imx6q"; compatible = "dmo,imx6q-edmqmx6", "fsl,imx6q";
chosen {
stdout-path = &uart2;
};
aliases { aliases {
gpio7 = &stmpe_gpio1; gpio7 = &stmpe_gpio1;
gpio8 = &stmpe_gpio2; gpio8 = &stmpe_gpio2;
@ -91,6 +95,20 @@ led-red {
}; };
}; };
&ecspi5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi5>;
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio1 12 0>;
status = "okay";
flash: m25p80@0 {
compatible = "m25p80";
spi-max-frequency = <40000000>;
reg = <0>;
};
};
&fec { &fec {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>; pinctrl-0 = <&pinctrl_enet>;
@ -105,7 +123,8 @@ &i2c2 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2 pinctrl-0 = <&pinctrl_i2c2
&pinctrl_stmpe1 &pinctrl_stmpe1
&pinctrl_stmpe2>; &pinctrl_stmpe2
&pinctrl_pfuze>;
status = "okay"; status = "okay";
pmic: pfuze100@08 { pmic: pfuze100@08 {
@ -216,6 +235,8 @@ stmpe1: stmpe1601@40 {
reg = <0x40>; reg = <0x40>;
interrupts = <30 0>; interrupts = <30 0>;
interrupt-parent = <&gpio3>; interrupt-parent = <&gpio3>;
vcc-supply = <&sw2_reg>;
vio-supply = <&sw2_reg>;
stmpe_gpio1: stmpe_gpio { stmpe_gpio1: stmpe_gpio {
#gpio-cells = <2>; #gpio-cells = <2>;
@ -228,6 +249,8 @@ stmpe2: stmpe1601@44 {
reg = <0x44>; reg = <0x44>;
interrupts = <2 0>; interrupts = <2 0>;
interrupt-parent = <&gpio5>; interrupt-parent = <&gpio5>;
vcc-supply = <&sw2_reg>;
vio-supply = <&sw2_reg>;
stmpe_gpio2: stmpe_gpio { stmpe_gpio2: stmpe_gpio {
#gpio-cells = <2>; #gpio-cells = <2>;
@ -263,6 +286,15 @@ MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x80000000
>; >;
}; };
pinctrl_ecspi5: ecspi5rp-1 {
fsl,pins = <
MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000
MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x80000000
MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x80000000
MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x80000000
>;
};
pinctrl_enet: enetgrp { pinctrl_enet: enetgrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
@ -291,6 +323,12 @@ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>; >;
}; };
pinctrl_pfuze: pfuze100grp1 {
fsl,pins = <
MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x80000000
>;
};
pinctrl_stmpe1: stmpe1grp { pinctrl_stmpe1: stmpe1grp {
fsl,pins = <MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x80000000>; fsl,pins = <MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x80000000>;
}; };

7
arch/arm/boot/dts/imx6q-gk802.dts
View File

@ -14,7 +14,7 @@ / {
compatible = "zealz,imx6q-gk802", "fsl,imx6q"; compatible = "zealz,imx6q-gk802", "fsl,imx6q";
chosen { chosen {
linux,stdout-path = &uart4; stdout-path = &uart4;
}; };
memory { memory {
@ -48,6 +48,11 @@ recovery-button {
}; };
}; };
&hdmi {
ddc-i2c-bus = <&i2c3>;
status = "okay";
};
/* Internal I2C */ /* Internal I2C */
&i2c2 { &i2c2 {
pinctrl-names = "default"; pinctrl-names = "default";

5
arch/arm/boot/dts/imx6q-gw5400-a.dts
View File

@ -157,6 +157,11 @@ &fec {
status = "okay"; status = "okay";
}; };
&hdmi {
ddc-i2c-bus = <&i2c3>;
status = "okay";
};
&i2c1 { &i2c1 {
clock-frequency = <100000>; clock-frequency = <100000>;
pinctrl-names = "default"; pinctrl-names = "default";

33
arch/arm/boot/dts/imx6q-phytec-pbab01.dts
View File

@ -11,40 +11,17 @@
/dts-v1/; /dts-v1/;
#include "imx6q-phytec-pfla02.dtsi" #include "imx6q-phytec-pfla02.dtsi"
#include "imx6qdl-phytec-pbab01.dtsi"
/ { / {
model = "Phytec phyFLEX-i.MX6 Quad Carrier-Board"; model = "Phytec phyFLEX-i.MX6 Quad Carrier-Board";
compatible = "phytec,imx6q-pbab01", "phytec,imx6q-pfla02", "fsl,imx6q"; compatible = "phytec,imx6q-pbab01", "phytec,imx6q-pfla02", "fsl,imx6q";
};
&fec { chosen {
status = "okay"; stdout-path = &uart4;
}; };
&gpmi {
status = "okay";
}; };
&sata { &sata {
status = "okay"; status = "okay";
};
&uart4 {
status = "okay";
};
&usbh1 {
status = "okay";
};
&usbotg {
status = "okay";
};
&usdhc2 {
status = "okay";
};
&usdhc3 {
status = "okay";
}; };

307
arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
View File

@ -10,316 +10,13 @@
*/ */
#include "imx6q.dtsi" #include "imx6q.dtsi"
#include "imx6qdl-phytec-pfla02.dtsi"
/ { / {
model = "Phytec phyFLEX-i.MX6 Ouad"; model = "Phytec phyFLEX-i.MX6 Quad";
compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
memory { memory {
reg = <0x10000000 0x80000000>; reg = <0x10000000 0x80000000>;
}; };
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usb_otg_vbus: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 15 0>;
};
reg_usb_h1_vbus: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 0 0>;
};
};
};
&ecspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
status = "okay";
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 24 0>;
flash@0 {
compatible = "m25p80";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
};
pmic@58 {
compatible = "dialog,da9063";
reg = <0x58>;
interrupt-parent = <&gpio4>;
interrupts = <17 0x8>; /* active-low GPIO4_17 */
regulators {
vddcore_reg: bcore1 {
regulator-min-microvolt = <730000>;
regulator-max-microvolt = <1380000>;
regulator-always-on;
};
vddsoc_reg: bcore2 {
regulator-min-microvolt = <730000>;
regulator-max-microvolt = <1380000>;
regulator-always-on;
};
vdd_ddr3_reg: bpro {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
};
vdd_3v3_reg: bperi {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdd_buckmem_reg: bmem {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdd_eth_reg: bio {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
vdd_eth_io_reg: ldo4 {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
vdd_mx6_snvs_reg: ldo5 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
vdd_3v3_pmic_io_reg: ldo6 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdd_sd0_reg: ldo9 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vdd_sd1_reg: ldo10 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vdd_mx6_high_reg: ldo11 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
};
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx6q-phytec-pfla02 {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000 /* PMIC interrupt */
>;
};
pinctrl_ecspi3: ecspi3grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
>;
};
pinctrl_usbh1: usbh1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x80000000
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
>;
};
pinctrl_usdhc3_cdwp: usdhc3cdwp {
fsl,pins = <
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
>;
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio3 23 0>;
status = "disabled";
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "disabled";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "disabled";
};
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
status = "disabled";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
status = "disabled";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
cd-gpios = <&gpio1 4 0>;
wp-gpios = <&gpio1 2 0>;
status = "disabled";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3
&pinctrl_usdhc3_cdwp>;
cd-gpios = <&gpio1 27 0>;
wp-gpios = <&gpio1 29 0>;
status = "disabled";
}; };

23
arch/arm/boot/dts/imx6q-udoo.dts
View File

@ -16,6 +16,10 @@ / {
model = "Udoo i.MX6 Quad Board"; model = "Udoo i.MX6 Quad Board";
compatible = "udoo,imx6q-udoo", "fsl,imx6q"; compatible = "udoo,imx6q-udoo", "fsl,imx6q";
chosen {
stdout-path = &uart2;
};
memory { memory {
reg = <0x10000000 0x40000000>; reg = <0x10000000 0x40000000>;
}; };
@ -28,6 +32,18 @@ &fec {
status = "okay"; status = "okay";
}; };
&hdmi {
ddc-i2c-bus = <&i2c2>;
status = "okay";
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&iomuxc { &iomuxc {
imx6q-udoo { imx6q-udoo {
pinctrl_enet: enetgrp { pinctrl_enet: enetgrp {
@ -51,6 +67,13 @@ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
>; >;
}; };
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_uart2: uart2grp { pinctrl_uart2: uart2grp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1

27
arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
View File

@ -55,6 +55,20 @@ sound-spdif {
}; };
}; };
&hdmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cubox_i_hdmi>;
ddc-i2c-bus = <&i2c2>;
status = "okay";
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cubox_i_i2c2>;
status = "okay";
};
&i2c3 { &i2c3 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cubox_i_i2c3>; pinctrl-0 = <&pinctrl_cubox_i_i2c3>;
@ -69,6 +83,19 @@ rtc: pcf8523@68 {
&iomuxc { &iomuxc {
cubox_i { cubox_i {
pinctrl_cubox_i_hdmi: cubox-i-hdmi {
fsl,pins = <
MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
>;
};
pinctrl_cubox_i_i2c2: cubox-i-i2c2 {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_cubox_i_i2c3: cubox-i-i2c3 { pinctrl_cubox_i_i2c3: cubox-i-i2c3 {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1

2
arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi
View File

@ -22,7 +22,7 @@ reg_usb_otg_vbus: regulator@1 {
}; };
chosen { chosen {
linux,stdout-path = &uart1; stdout-path = &uart1;
}; };
}; };

5
arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
View File

@ -101,6 +101,11 @@ &gpmi {
status = "okay"; status = "okay";
}; };
&hdmi {
ddc-i2c-bus = <&i2c3>;
status = "okay";
};
&i2c1 { &i2c1 {
clock-frequency = <100000>; clock-frequency = <100000>;
pinctrl-names = "default"; pinctrl-names = "default";

45
arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
View File

@ -27,6 +27,13 @@ chosen {
bootargs = "console=ttymxc1,115200"; bootargs = "console=ttymxc1,115200";
}; };
backlight {
compatible = "pwm-backlight";
pwms = <&pwm4 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
};
leds { leds {
compatible = "gpio-leds"; compatible = "gpio-leds";
@ -148,6 +155,11 @@ &gpmi {
status = "okay"; status = "okay";
}; };
&hdmi {
ddc-i2c-bus = <&i2c3>;
status = "okay";
};
&i2c1 { &i2c1 {
clock-frequency = <100000>; clock-frequency = <100000>;
pinctrl-names = "default"; pinctrl-names = "default";
@ -394,6 +406,12 @@ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>; >;
}; };
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
>;
};
pinctrl_uart1: uart1grp { pinctrl_uart1: uart1grp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
@ -436,6 +454,27 @@ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
&ldb { &ldb {
status = "okay"; status = "okay";
lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
};
};
};
}; };
&pcie { &pcie {
@ -443,6 +482,12 @@ &pcie {
status = "okay"; status = "okay";
}; };
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&ssi1 { &ssi1 {
fsl,mode = "i2s-slave"; fsl,mode = "i2s-slave";
status = "okay"; status = "okay";

24
arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
View File

@ -30,6 +30,13 @@ chosen {
bootargs = "console=ttymxc1,115200"; bootargs = "console=ttymxc1,115200";
}; };
backlight {
compatible = "pwm-backlight";
pwms = <&pwm4 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
};
leds { leds {
compatible = "gpio-leds"; compatible = "gpio-leds";
@ -157,6 +164,11 @@ &gpmi {
status = "okay"; status = "okay";
}; };
&hdmi {
ddc-i2c-bus = <&i2c3>;
status = "okay";
};
&i2c1 { &i2c1 {
clock-frequency = <100000>; clock-frequency = <100000>;
pinctrl-names = "default"; pinctrl-names = "default";
@ -434,6 +446,12 @@ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>; >;
}; };
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
>;
};
pinctrl_uart1: uart1grp { pinctrl_uart1: uart1grp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
@ -508,6 +526,12 @@ eth1: sky2@8 { /* MAC/PHY on bus 8 */
}; };
}; };
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&ssi1 { &ssi1 {
fsl,mode = "i2s-slave"; fsl,mode = "i2s-slave";
status = "okay"; status = "okay";

24
arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
View File

@ -30,6 +30,13 @@ chosen {
bootargs = "console=ttymxc1,115200"; bootargs = "console=ttymxc1,115200";
}; };
backlight {
compatible = "pwm-backlight";
pwms = <&pwm4 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
};
leds { leds {
compatible = "gpio-leds"; compatible = "gpio-leds";
@ -147,6 +154,11 @@ &gpmi {
status = "okay"; status = "okay";
}; };
&hdmi {
ddc-i2c-bus = <&i2c3>;
status = "okay";
};
&i2c1 { &i2c1 {
clock-frequency = <100000>; clock-frequency = <100000>;
pinctrl-names = "default"; pinctrl-names = "default";
@ -456,6 +468,12 @@ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>; >;
}; };
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
>;
};
pinctrl_uart1: uart1grp { pinctrl_uart1: uart1grp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
@ -530,6 +548,12 @@ eth1: sky2@8 { /* MAC/PHY on bus 8 */
}; };
}; };
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&ssi1 { &ssi1 {
fsl,mode = "i2s-slave"; fsl,mode = "i2s-slave";
status = "okay"; status = "okay";

4
arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
View File

@ -14,6 +14,10 @@
#include <dt-bindings/input/input.h> #include <dt-bindings/input/input.h>
/ { / {
chosen {
stdout-path = &uart2;
};
memory { memory {
reg = <0x10000000 0x40000000>; reg = <0x10000000 0x40000000>;
}; };

102
arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi Normal file
View File

@ -0,0 +1,102 @@
/*
* Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/ {
chosen {
linux,stdout-path = &uart4;
};
};
&fec {
status = "okay";
};
&gpmi {
status = "okay";
};
&hdmi {
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clock-frequency = <100000>;
status = "okay";
tlv320@18 {
compatible = "ti,tlv320aic3x";
reg = <0x18>;
};
stmpe@41 {
compatible = "st,stmpe811";
reg = <0x41>;
};
rtc@51 {
compatible = "nxp,rtc8564";
reg = <0x51>;
};
adc@64 {
compatible = "maxim,max1037";
reg = <0x64>;
};
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clock-frequency = <100000>;
status = "okay";
};
&uart3 {
status = "okay";
};
&uart4 {
status = "okay";
};
&usbh1 {
status = "okay";
};
&usbotg {
status = "okay";
};
&usdhc2 {
status = "okay";
};
&usdhc3 {
status = "okay";
};
&iomuxc {
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
>;
};
};

356
arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi Normal file
View File

@ -0,0 +1,356 @@
/*
* Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Phytec phyFLEX-i.MX6 Ouad";
compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
memory {
reg = <0x10000000 0x80000000>;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usb_otg_vbus: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 15 0>;
};
reg_usb_h1_vbus: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 0 0>;
};
};
gpio_leds: leds {
compatible = "gpio-leds";
green {
label = "phyflex:green";
gpios = <&gpio1 30 0>;
};
red {
label = "phyflex:red";
gpios = <&gpio2 31 0>;
};
};
};
&ecspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
status = "okay";
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 24 0>;
flash@0 {
compatible = "m25p80";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
};
pmic@58 {
compatible = "dialog,da9063";
reg = <0x58>;
interrupt-parent = <&gpio4>;
interrupts = <17 0x8>; /* active-low GPIO4_17 */
regulators {
vddcore_reg: bcore1 {
regulator-min-microvolt = <730000>;
regulator-max-microvolt = <1380000>;
regulator-always-on;
};
vddsoc_reg: bcore2 {
regulator-min-microvolt = <730000>;
regulator-max-microvolt = <1380000>;
regulator-always-on;
};
vdd_ddr3_reg: bpro {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
};
vdd_3v3_reg: bperi {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdd_buckmem_reg: bmem {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdd_eth_reg: bio {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
vdd_eth_io_reg: ldo4 {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
vdd_mx6_snvs_reg: ldo5 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
vdd_3v3_pmic_io_reg: ldo6 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdd_sd0_reg: ldo9 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vdd_sd1_reg: ldo10 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vdd_mx6_high_reg: ldo11 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
};
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx6q-phytec-pfla02 {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000 /* PMIC interrupt */
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */
MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */
>;
};
pinctrl_ecspi3: ecspi3grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1
MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
>;
};
pinctrl_usbh1: usbh1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x80000000
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
>;
};
pinctrl_usdhc3_cdwp: usdhc3cdwp {
fsl,pins = <
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
>;
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
status = "disabled";
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "disabled";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "disabled";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "disabled";
};
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
status = "disabled";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
status = "disabled";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
cd-gpios = <&gpio1 4 0>;
wp-gpios = <&gpio1 2 0>;
status = "disabled";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3
&pinctrl_usdhc3_cdwp>;
cd-gpios = <&gpio1 27 0>;
wp-gpios = <&gpio1 29 0>;
status = "disabled";
};

4
arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
View File

@ -13,6 +13,10 @@
#include <dt-bindings/input/input.h> #include <dt-bindings/input/input.h>
/ { / {
chosen {
stdout-path = &uart2;
};
memory { memory {
reg = <0x10000000 0x40000000>; reg = <0x10000000 0x40000000>;
}; };

65
arch/arm/boot/dts/imx6qdl-sabresd.dtsi
View File

@ -14,6 +14,10 @@
#include <dt-bindings/input/input.h> #include <dt-bindings/input/input.h>
/ { / {
chosen {
stdout-path = &uart1;
};
memory { memory {
reg = <0x10000000 0x40000000>; reg = <0x10000000 0x40000000>;
}; };
@ -105,6 +109,17 @@ backlight {
default-brightness-level = <7>; default-brightness-level = <7>;
status = "okay"; status = "okay";
}; };
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
red {
gpios = <&gpio1 2 0>;
default-state = "on";
};
};
}; };
&audmux { &audmux {
@ -137,6 +152,11 @@ &fec {
status = "okay"; status = "okay";
}; };
&hdmi {
ddc-i2c-bus = <&i2c2>;
status = "okay";
};
&i2c1 { &i2c1 {
clock-frequency = <100000>; clock-frequency = <100000>;
pinctrl-names = "default"; pinctrl-names = "default";
@ -373,6 +393,12 @@ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>; >;
}; };
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
>;
};
pinctrl_pwm1: pwm1grp { pinctrl_pwm1: pwm1grp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
@ -421,6 +447,29 @@ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
>; >;
}; };
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
>;
};
};
gpio_leds {
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
>;
};
}; };
}; };
@ -449,6 +498,13 @@ timing0: hsd100pxn1 {
}; };
}; };
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio7 12 0>;
status = "okay";
};
&pwm1 { &pwm1 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>; pinctrl-0 = <&pinctrl_pwm1>;
@ -496,3 +552,12 @@ &usdhc3 {
wp-gpios = <&gpio2 1 0>; wp-gpios = <&gpio2 1 0>;
status = "okay"; status = "okay";
}; };
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;
bus-width = <8>;
non-removable;
no-1-8-v;
status = "okay";
};

19
arch/arm/boot/dts/imx6qdl-wandboard.dtsi
View File

@ -62,6 +62,18 @@ &audmux {
status = "okay"; status = "okay";
}; };
&hdmi {
ddc-i2c-bus = <&i2c1>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c2 { &i2c2 {
clock-frequency = <100000>; clock-frequency = <100000>;
pinctrl-names = "default"; pinctrl-names = "default";
@ -127,6 +139,13 @@ MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>; >;
}; };
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_i2c2: i2c2grp { pinctrl_i2c2: i2c2grp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1

8
arch/arm/boot/dts/imx6qdl.dtsi
View File

@ -16,6 +16,7 @@
/ { / {
aliases { aliases {
ethernet0 = &fec;
can0 = &can1; can0 = &can1;
can1 = &can2; can1 = &can2;
gpio0 = &gpio1; gpio0 = &gpio1;
@ -140,15 +141,16 @@ pcie: pcie@0x01000000 {
0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
num-lanes = <1>; num-lanes = <1>;
interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>; #interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>; interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>; clocks = <&clks 144>, <&clks 206>, <&clks 189>;
clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi"; clock-names = "pcie", "pcie_bus", "pcie_phy";
status = "disabled"; status = "disabled";
}; };

1
arch/arm/boot/dts/imx6sl.dtsi
View File

@ -14,6 +14,7 @@
/ { / {
aliases { aliases {
ethernet0 = &fec;
gpio0 = &gpio1; gpio0 = &gpio1;
gpio1 = &gpio2; gpio1 = &gpio2;
gpio2 = &gpio3; gpio2 = &gpio3;

123
arch/arm/boot/dts/vf610-colibri.dts Normal file
View File

@ -0,0 +1,123 @@
/*
* Copyright 2014 Toradex AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
/dts-v1/;
#include "vf610.dtsi"
/ {
model = "Toradex Colibri VF61 COM";
compatible = "toradex,vf610-colibri", "fsl,vf610";
chosen {
bootargs = "console=ttyLP0,115200";
};
memory {
reg = <0x80000000 0x10000000>;
};
clocks {
enet_ext {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
};
};
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
bus-width = <4>;
status = "okay";
};
&fec1 {
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
status = "okay";
};
&L2 {
arm,data-latency = <2 1 2>;
arm,tag-latency = <3 2 3>;
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&iomuxc {
vf610-colibri {
pinctrl_esdhc1: esdhc1grp {
fsl,fsl,pins = <
VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
VF610_PAD_PTB20__GPIO_42 0x219d
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1
VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
>;
};
pinctrl_uart0: uart0grp {
fsl,pins = <
VF610_PAD_PTB10__UART0_TX 0x21a2
VF610_PAD_PTB11__UART0_RX 0x21a1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
VF610_PAD_PTB4__UART1_TX 0x21a2
VF610_PAD_PTB5__UART1_RX 0x21a1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
VF610_PAD_PTD0__UART2_TX 0x21a2
VF610_PAD_PTD1__UART2_RX 0x21a1
VF610_PAD_PTD2__UART2_RTS 0x21a2
VF610_PAD_PTD3__UART2_CTS 0x21a1
>;
};
};
};

36
arch/arm/boot/dts/vf610-twr.dts
View File

@ -113,6 +113,13 @@ sflash: at26df081a@0 {
}; };
}; };
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
bus-width = <4>;
status = "okay";
};
&fec0 { &fec0 {
phy-mode = "rmii"; phy-mode = "rmii";
pinctrl-names = "default"; pinctrl-names = "default";
@ -160,6 +167,18 @@ VF610_PAD_PTB22__DSPI0_SCK 0x1182
>; >;
}; };
pinctrl_esdhc1: esdhc1grp {
fsl,fsl,pins = <
VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
VF610_PAD_PTA7__GPIO_134 0x219d
>;
};
pinctrl_fec0: fec0grp { pinctrl_fec0: fec0grp {
fsl,pins = < fsl,pins = <
VF610_PAD_PTA6__RMII_CLKIN 0x30d1 VF610_PAD_PTA6__RMII_CLKIN 0x30d1
@ -196,6 +215,17 @@ VF610_PAD_PTB15__I2C0_SDA 0x30d3
>; >;
}; };
pinctrl_pwm0: pwm0grp {
fsl,pins = <
VF610_PAD_PTB0__FTM0_CH0 0x1582
VF610_PAD_PTB1__FTM0_CH1 0x1582
VF610_PAD_PTB2__FTM0_CH2 0x1582
VF610_PAD_PTB3__FTM0_CH3 0x1582
VF610_PAD_PTB6__FTM0_CH6 0x1582
VF610_PAD_PTB7__FTM0_CH7 0x1582
>;
};
pinctrl_sai2: sai2grp { pinctrl_sai2: sai2grp {
fsl,pins = < fsl,pins = <
VF610_PAD_PTA16__SAI2_TX_BCLK 0x02ed VF610_PAD_PTA16__SAI2_TX_BCLK 0x02ed
@ -217,6 +247,12 @@ VF610_PAD_PTB5__UART1_RX 0x21a1
}; };
}; };
&pwm0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0>;
status = "okay";
};
&sai2 { &sai2 {
#sound-dai-cells = <0>; #sound-dai-cells = <0>;
pinctrl-names = "default"; pinctrl-names = "default";

24
arch/arm/boot/dts/vf610.dtsi
View File

@ -183,6 +183,19 @@ pit: pit@40037000 {
clock-names = "pit"; clock-names = "pit";
}; };
pwm0: pwm@40038000 {
compatible = "fsl,vf610-ftm-pwm";
#pwm-cells = <3>;
reg = <0x40038000 0x1000>;
clock-names = "ftm_sys", "ftm_ext",
"ftm_fix", "ftm_cnt_clk_en";
clocks = <&clks VF610_CLK_FTM0>,
<&clks VF610_CLK_FTM0_EXT_SEL>,
<&clks VF610_CLK_FTM0_FIX_SEL>,
<&clks VF610_CLK_FTM0_EXT_FIX_EN>;
status = "disabled";
};
adc0: adc@4003b000 { adc0: adc@4003b000 {
compatible = "fsl,vf610-adc"; compatible = "fsl,vf610-adc";
reg = <0x4003b000 0x1000>; reg = <0x4003b000 0x1000>;
@ -347,6 +360,17 @@ adc1: adc@400bb000 {
status = "disabled"; status = "disabled";
}; };
esdhc1: esdhc@400b2000 {
compatible = "fsl,imx53-esdhc";
reg = <0x400b2000 0x4000>;
interrupts = <0 28 0x04>;
clocks = <&clks VF610_CLK_IPG_BUS>,
<&clks VF610_CLK_PLATFORM_BUS>,
<&clks VF610_CLK_ESDHC1>;
clock-names = "ipg", "ahb", "per";
status = "disabled";
};
fec0: ethernet@400d0000 { fec0: ethernet@400d0000 {
compatible = "fsl,mvf600-fec"; compatible = "fsl,mvf600-fec";
reg = <0x400d0000 0x1000>; reg = <0x400d0000 0x1000>;