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Renesas ARM Based SoC DT Updates for v4.18 

* R-Mobile A1 (r8a7740) SoC
   - Describe CEU, IRQC, SYS-DMAC and USB devices
 
   - Cleanup for consistency with other Renesas SoCs and enhanced maintainability
     + Stop grouping clocks under a "clocks" subnode
     + Add soc node
     + Sort subnodes of root and soc nodes
 
 * RZ/A1H (r7s72100) SoC
   - Describe CEU device
 
 * R-Car Gen2, RZ/G1 and RZ/A1H SoCs
   - Add PMU device nodes
 
     Geert Uytterhoeven says: "This patch series enables support for the ARM
     Performance Monitor Units in Cortex-A7, Cortex-A9, and Cortex-A15 CPU
     cores on Renesas RZ/A1, R-Car Gen2, and RZ/G1 SoCs.  This allows for
     better performance analysis using the "perf" tool."
 
 * RZ/A1H (r7s72100) SoC
   - Correct interrupt types
 
     Geert Uytterhoeven says "RZ/A1H peripherals use a mix of level and edge
     interrupts.
 
     This patch series corrects the interrupt types for watchdog and RTC from
     edge to level, to match the datasheet."
 
 * R-Mobile APE6 (r8a73a4) APE4EVM board and SH-Mobile AG5 (sh73a0) SoC
   - Use generic disable-wp instead of now deprecated
     toshiba,mmc-wrprotect-disable property
 
 * EMMA Mobile EV2 (emev2) and SH-Mobile AG5 (sh73a0) SoCs
   - Add missing interrupt-affinity to PMU
 
     Geert Uytterhoeven says "The Cortex-A9 PMU nodes on SH-Mobile AG5 and
     Emma Mobile EV2 reference two interrupts, but lack interrupt-affinity
     properties, leading to:
 
     hw perfevents: no interrupt-affinity property for /pmu, guessing.
 
     This series adds the missing properties to fix this."
 
 * R-Car H2 (r8a7790) and R-Mobile APE6 (r8a73a4) SoCs
   - Correct mask for GIC PPI interrupts
 
     Geert Uytterhoeven says "R-Car H2 and R-Mobile APE6 contain four
     Cortex-A15 and four Cortex-A7 cores, hence the second interrupt
     specifier cell for Private Peripheral Interrupts should use
     "GIC_CPU_MASK_SIMPLE(8)", to make sure interrupts can be delivered to
     all 8 processor cores.
 
     This brings the predecessors of R-Car Gen3 in line with what we're
     doing on other big.LITTLE SoCs, like R-Car H3 and M3-W."
 
 * Alt board for R-Car E2 (r8a7794) SoC
 
 * RBoards for -Car Gen2 SoCs and kzm9d board for EMMA Mobile EV2 (emev2) SoC
   - Drop unnecessary address properties from VIN port nodes
 
     These are unnecessary as the nodes to not have bus addresses.
 
 * R-Car H2 (r8a7790), M2-W (r8a7791), M2-N (r8a7793) and E2 (r8a7794) SoCs
   - Describe FDP1 instances
 
 * iW-RainboW-G23S board for RZ/G1C (r8a77470) SoC
   - Initial SoC and board support
 
   - Enable EtherAVB
 
   - Describe all SCIF devices
 
 * Boards for R-Car Gen2 SoCs
   - Enable watchdog support
 
     Geert Uytterhoeven says "This patch series enables the builtin watchdog
     timer on R-Car Gen2 SoCs on all supported boards, and builds on top of
     Fabrizio's "[RFC v4 00/26] Fix watchdog on Renesas R-Car Gen2 and
     RZ/G1"."
 
 * R-Car Gen2 and RZ/G1 SoCs
   - Describe watchdog devices
 
   - For R-Car Gen2 this involves updating the SMP routine side as
     it is changed by a driver updated to allow watchdog device support
 
 * Wheat board for V2H (r8a7792) SoC
   - Correct ADV7513 address usage
 
     Kieran Bingham says "The r8a7792 Wheat board has two ADV7513 devices
     sharing a single I2C bus, however in low power mode the ADV7513 will
     reset it's slave maps to use the hardware defined default addresses.
 
     The ADV7511 driver was adapted to allow the two devices to be
     registered correctly - but it did not take into account the fault
     whereby the devices reset the addresses.
 
     This results in an address conflict between the device using the
     default addresses, and the other device if it is in low-power-mode.
 
     Repair this issue by moving both devices away from the default address
     definitions."
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Merge tag 'renesas-dt-for-v4.18' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/late

Renesas ARM Based SoC DT Updates for v4.18

* R-Mobile A1 (r8a7740) SoC
  - Describe CEU, IRQC, SYS-DMAC and USB devices
  - Cleanup for consistency with other Renesas SoCs and enhanced maintainability
* RZ/A1H (r7s72100) SoC
  - Describe CEU device
* R-Car Gen2, RZ/G1 and RZ/A1H SoCs
  - Add PMU device nodes
* RZ/A1H (r7s72100) SoC
  - Correct interrupt types
* R-Mobile APE6 (r8a73a4) APE4EVM board and SH-Mobile AG5 (sh73a0) SoC
  - Use generic disable-wp instead of now deprecated
    toshiba,mmc-wrprotect-disable property
* EMMA Mobile EV2 (emev2) and SH-Mobile AG5 (sh73a0) SoCs
  - Add missing interrupt-affinity to PMU
* R-Car H2 (r8a7790) and R-Mobile APE6 (r8a73a4) SoCs
  - Correct mask for GIC PPI interrupts
* R-Car H2 (r8a7790), M2-W (r8a7791), M2-N (r8a7793) and E2 (r8a7794) SoCs
  - Describe FDP1 instances
* R-Car Gen2 and RZ/G1 SoCs
  - Describe watchdog devices
  - For R-Car Gen2 this involves updating the SMP routine side as
    it is changed by a driver updated to allow watchdog device support

* Alt board for R-Car E2 (r8a7794) SoC
* RBoards for -Car Gen2 SoCs and kzm9d board for EMMA Mobile EV2 (emev2) SoC
* iW-RainboW-G23S board for RZ/G1C (r8a77470) SoC
  - Initial SoC and board support
  - Enable EtherAVB
  - Describe all SCIF devices
* Boards for R-Car Gen2 SoCs
  - Enable watchdog support
* Wheat board for V2H (r8a7792) SoC
  - Correct ADV7513 address usage

* tag 'renesas-dt-for-v4.18' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (69 commits)
  ARM: dts: r8a7740: Add CEU1
  ARM: dts: r8a7740: Add CEU0
  ARM: dts: r8a7745: Add PMU device node
  ARM: dts: r8a7743: Add PMU device node
  ARM: dts: r8a7794: Add PMU device node
  ARM: dts: r8a7793: Add PMU device node
  ARM: dts: r8a7792: Add PMU device node
  ARM: dts: r8a7791: Add PMU device node
  ARM: dts: r8a7790: Add PMU device nodes
  ARM: dts: r7s72100: Add PMU device node
  ARM: dts: r7s72100: Correct RTC interrupt types
  ARM: dts: r7s72100: Correct watchdog timer interrupt type
  ARM: dts: emev2: Add missing interrupt-affinity to PMU node
  ARM: dts: sh73a0: Add missing interrupt-affinity to PMU node
  ARM: dts: r8a73a4: Correct mask for GIC PPI interrupts
  ARM: dts: r8a7790: Correct mask for GIC PPI interrupts
  ARM: shmobile: r8a7794: alt: add EEPROM to DTS
  ARM: dts: kzm9d: Drop unnecessary address properties from gpio_keys node
  ARM: dts: silk: Drop unnecessary address properties from vin port node
  ARM: dts: alt: Drop unnecessary address properties from vin port node
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2018-06-02 01:32:38 -07:00
parent 171d429a1d 7fad92d058
commit 14321604c8
27 changed files with 1250 additions and 569 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/boot/dts/Makefile
View File

@ -795,6 +795,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
r8a7745-iwg22d-sodimm.dtb \
r8a7745-iwg22d-sodimm-dbhd-ca.dtb \
r8a7745-sk-rzg1e.dtb \
r8a77470-iwg23s-sbc.dtb \
r8a7778-bockw.dtb \
r8a7779-marzen.dtb \
r8a7790-lager.dtb \

3
arch/arm/boot/dts/emev2-kzm9d.dts
View File

@ -34,9 +34,6 @@ chosen {
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
one {
debounce-interval = <50>;
wakeup-source;

5
arch/arm/boot/dts/emev2.dtsi
View File

@ -31,13 +31,13 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
clock-frequency = <533000000>;
};
cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
@ -57,6 +57,7 @@ pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
clocks@e0110000 {

1068
arch/arm/boot/dts/r7s72100.dtsi
View File

File diff suppressed because it is too large Load Diff

4
arch/arm/boot/dts/r8a73a4-ape6evm.dts
View File

@ -234,7 +234,7 @@ &scifa0 {
&sdhi0 {
vmmc-supply = <&vcc_sdhi0>;
bus-width = <4>;
toshiba,mmc-wrprotect-disable;
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdhi0_pins>;
status = "okay";
@ -244,7 +244,7 @@ &sdhi1 {
vmmc-supply = <&ape6evm_fixed_3v3>;
bus-width = <4>;
broken-cd;
toshiba,mmc-wrprotect-disable;
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdhi1_pins>;
status = "okay";

10
arch/arm/boot/dts/r8a73a4.dtsi
View File

@ -57,10 +57,10 @@ ptm {
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
dbsc1: memory-controller@e6790000 {
@ -464,7 +464,7 @@ gic: interrupt-controller@f1001000 {
<0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>;
clock-names = "clk";
power-domains = <&pd_c4>;

18
arch/arm/boot/dts/r8a7740.dtsi
View File

@ -67,6 +67,24 @@ ptm {
power-domains = <&pd_d4>;
};
ceu0: ceu@fe910000 {
reg = <0xfe910000 0x3000>;
compatible = "renesas,r8a7740-ceu";
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7740_CLK_CEU20>;
power-domains = <&pd_a4r>;
status = "disabled";
};
ceu1: ceu@fe914000 {
reg = <0xfe914000 0x3000>;
compatible = "renesas,r8a7740-ceu";
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7740_CLK_CEU21>;
power-domains = <&pd_a4r>;
status = "disabled";
};
cmt1: timer@e6138000 {
compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48";
reg = <0xe6138000 0x170>;

5
arch/arm/boot/dts/r8a7743-iwg20m.dtsi
View File

@ -91,6 +91,11 @@ flash: flash@0 {
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-names = "default";

19
arch/arm/boot/dts/r8a7743.dtsi
View File

@ -125,6 +125,13 @@ pcie_bus_clk: pcie_bus {
clock-frequency = <0>;
};
pmu {
compatible = "arm,cortex-a15-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
/* External SCIF clock */
scif_clk: scif {
compatible = "fixed-clock";
@ -297,6 +304,16 @@ rst: reset-controller@e6160000 {
reg = <0 0xe6160000 0 0x100>;
};
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a7743-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 402>;
status = "disabled";
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7743-sysc";
reg = <0 0xe6180000 0 0x200>;
@ -407,7 +424,7 @@ icram1: sram@e63c0000 {
smp-sram@0 {
compatible = "renesas,smp-sram";
reg = <0 0x10>;
reg = <0 0x100>;
};
};

5
arch/arm/boot/dts/r8a7745-iwg22m.dtsi
View File

@ -91,6 +91,11 @@ flash: flash@0 {
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&sdhi1 {
pinctrl-0 = <&sdhi1_pins>;
pinctrl-names = "default";

19
arch/arm/boot/dts/r8a7745.dtsi
View File

@ -105,6 +105,13 @@ extal_clk: extal {
clock-frequency = <0>;
};
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
/* External SCIF clock */
scif_clk: scif {
compatible = "fixed-clock";
@ -262,6 +269,16 @@ rst: reset-controller@e6160000 {
reg = <0 0xe6160000 0 0x100>;
};
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a7745-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 402>;
status = "disabled";
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7745-sysc";
reg = <0 0xe6180000 0 0x200>;
@ -360,7 +377,7 @@ icram1: sram@e63c0000 {
smp-sram@0 {
compatible = "renesas,smp-sram";
reg = <0 0x10>;
reg = <0 0x100>;
};
};

48
arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts Normal file
View File

@ -0,0 +1,48 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the iWave-RZ/G1C single board computer
*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a77470.dtsi"
/ {
model = "iWave iW-RainboW-G23S single board computer based on RZ/G1C";
compatible = "iwave,g23s", "renesas,r8a77470";
aliases {
ethernet0 = &avb;
serial1 = &scif1;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial1:115200n8";
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x20000000>;
};
};
&avb {
phy-handle = <&phy3>;
phy-mode = "gmii";
renesas,no-ether-link;
status = "okay";
phy3: ethernet-phy@3 {
reg = <3>;
micrel,led-mode = <1>;
};
};
&extal_clk {
clock-frequency = <20000000>;
};
&scif1 {
status = "okay";
};

336
arch/arm/boot/dts/r8a77470.dtsi Normal file
View File

@ -0,0 +1,336 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the r8a77470 SoC
*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/ {
compatible = "renesas,r8a77470";
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0>;
clock-frequency = <1000000000>;
clocks = <&cpg CPG_CORE 0>;
power-domains = <&sysc 5>;
next-level-cache = <&L2_CA7>;
};
L2_CA7: cache-controller-0 {
compatible = "cache";
cache-unified;
cache-level = <2>;
power-domains = <&sysc 21>;
};
};
/* External root clock */
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
};
/* External SCIF clock */
scif_clk: scif {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
};
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a77470-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
clocks = <&extal_clk>, <&usb_extal_clk>;
clock-names = "extal", "usb_extal";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
};
rst: reset-controller@e6160000 {
compatible = "renesas,r8a77470-rst";
reg = <0 0xe6160000 0 0x100>;
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a77470-sysc";
reg = <0 0xe6180000 0 0x200>;
#power-domain-cells = <1>;
};
irqc: interrupt-controller@e61c0000 {
compatible = "renesas,irqc-r8a77470", "renesas,irqc";
#interrupt-cells = <2>;
interrupt-controller;
reg = <0 0xe61c0000 0 0x200>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 407>;
power-domains = <&sysc 32>;
resets = <&cpg 407>;
};
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
};
icram1: sram@e63c0000 {
compatible = "mmio-sram";
reg = <0 0xe63c0000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0xe63c0000 0x1000>;
smp-sram@0 {
compatible = "renesas,smp-sram";
reg = <0 0x100>;
};
};
icram2: sram@e6300000 {
compatible = "mmio-sram";
reg = <0 0xe6300000 0 0x20000>;
};
dmac0: dma-controller@e6700000 {
compatible = "renesas,dmac-r8a77470",
"renesas,rcar-dmac";
reg = <0 0xe6700000 0 0x20000>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14";
clocks = <&cpg CPG_MOD 219>;
clock-names = "fck";
power-domains = <&sysc 32>;
resets = <&cpg 219>;
#dma-cells = <1>;
dma-channels = <15>;
};
dmac1: dma-controller@e6720000 {
compatible = "renesas,dmac-r8a77470",
"renesas,rcar-dmac";
reg = <0 0xe6720000 0 0x20000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14";
clocks = <&cpg CPG_MOD 218>;
clock-names = "fck";
power-domains = <&sysc 32>;
resets = <&cpg 218>;
#dma-cells = <1>;
dma-channels = <15>;
};
avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a77470",
"renesas,etheravb-rcar-gen2";
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc 32>;
resets = <&cpg 812>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
scif0: serial@e6e60000 {
compatible = "renesas,scif-r8a77470",
"renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6e60000 0 0x40>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 721>,
<&cpg CPG_CORE 5>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
<&dmac1 0x29>, <&dmac1 0x2a>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
resets = <&cpg 721>;
status = "disabled";
};
scif1: serial@e6e68000 {
compatible = "renesas,scif-r8a77470",
"renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6e68000 0 0x40>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 720>,
<&cpg CPG_CORE 5>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
<&dmac1 0x2d>, <&dmac1 0x2e>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
resets = <&cpg 720>;
status = "disabled";
};
scif2: serial@e6e58000 {
compatible = "renesas,scif-r8a77470",
"renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6e58000 0 0x40>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 719>,
<&cpg CPG_CORE 5>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
<&dmac1 0x2b>, <&dmac1 0x2c>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
resets = <&cpg 719>;
status = "disabled";
};
scif3: serial@e6ea8000 {
compatible = "renesas,scif-r8a77470",
"renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6ea8000 0 0x40>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 718>,
<&cpg CPG_CORE 5>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
<&dmac1 0x2f>, <&dmac1 0x30>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
resets = <&cpg 718>;
status = "disabled";
};
scif4: serial@e6ee0000 {
compatible = "renesas,scif-r8a77470",
"renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6ee0000 0 0x40>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 715>,
<&cpg CPG_CORE 5>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
<&dmac1 0xfb>, <&dmac1 0xfc>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
resets = <&cpg 715>;
status = "disabled";
};
scif5: serial@e6ee8000 {
compatible = "renesas,scif-r8a77470",
"renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6ee8000 0 0x40>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 714>,
<&cpg CPG_CORE 5>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
<&dmac1 0xfd>, <&dmac1 0xfe>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
resets = <&cpg 714>;
status = "disabled";
};
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc 32>;
resets = <&cpg 408>;
};
prr: chipid@ff000044 {
compatible = "renesas,prr";
reg = <0 0xff000044 0 4>;
};
};
timer {
compatible = "arm,armv7-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
/* External USB clock - can be overridden by the board */
usb_extal_clk: usb_extal {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
};

8
arch/arm/boot/dts/r8a7790-lager.dts
View File

@ -890,9 +890,6 @@ &vin1 {
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
vin1ep0: endpoint {
remote-endpoint = <&adv7180>;
bus-width = <8>;
@ -917,6 +914,11 @@ dai0 {
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&ssi1 {
shared-pin;
};

67
arch/arm/boot/dts/r8a7790.dtsi
View File

@ -202,6 +202,24 @@ pcie_bus_clk: pcie_bus {
clock-frequency = <0>;
};
pmu-0 {
compatible = "arm,cortex-a15-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
pmu-1 {
compatible = "arm,cortex-a7-pmu";
interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
};
/* External SCIF clock */
scif_clk: scif {
compatible = "fixed-clock";
@ -218,6 +236,16 @@ soc {
#size-cells = <2>;
ranges;
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a7790-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 402>;
status = "disabled";
};
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7790",
"renesas,rcar-gen2-gpio";
@ -443,7 +471,7 @@ icram1: sram@e63c0000 {
smp-sram@0 {
compatible = "renesas,smp-sram";
reg = <0 0x10>;
reg = <0 0x100>;
};
};
@ -1544,7 +1572,7 @@ gic: interrupt-controller@f1001000 {
interrupt-controller;
reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
@ -1615,6 +1643,33 @@ vsp@fe938000 {
resets = <&cpg 127>;
};
fdp1@fe940000 {
compatible = "renesas,fdp1";
reg = <0 0xfe940000 0 0x2400>;
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 119>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 119>;
};
fdp1@fe944000 {
compatible = "renesas,fdp1";
reg = <0 0xfe944000 0 0x2400>;
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 118>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 118>;
};
fdp1@fe948000 {
compatible = "renesas,fdp1";
reg = <0 0xfe948000 0 0x2400>;
interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 117>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 117>;
};
jpu: jpeg-codec@fe980000 {
compatible = "renesas,jpu-r8a7790",
"renesas,rcar-gen2-jpu";
@ -1724,10 +1779,10 @@ cooling-maps {
timer {
compatible = "arm,armv7-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
/* External USB clock - can be overridden by the board */

11
arch/arm/boot/dts/r8a7791-koelsch.dts
View File

@ -637,6 +637,11 @@ &cmt0 {
status = "okay";
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&sata0 {
status = "okay";
};
@ -844,9 +849,6 @@ &vin0 {
pinctrl-names = "default";
port {
#address-cells = <1>;
#size-cells = <0>;
vin0ep2: endpoint {
remote-endpoint = <&adv7612_out>;
bus-width = <24>;
@ -865,9 +867,6 @@ &vin1 {
pinctrl-names = "default";
port {
#address-cells = <1>;
#size-cells = <0>;
vin1ep: endpoint {
remote-endpoint = <&adv7180>;
bus-width = <8>;

8
arch/arm/boot/dts/r8a7791-porter.dts
View File

@ -386,9 +386,6 @@ &vin0 {
pinctrl-names = "default";
port {
#address-cells = <1>;
#size-cells = <0>;
vin0ep: endpoint {
remote-endpoint = <&adv7180>;
bus-width = <8>;
@ -471,6 +468,11 @@ dai0 {
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&ssi1 {
shared-pin;
};

37
arch/arm/boot/dts/r8a7791.dtsi
View File

@ -126,6 +126,13 @@ pcie_bus_clk: pcie_bus {
clock-frequency = <0>;
};
pmu {
compatible = "arm,cortex-a15-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
/* External SCIF clock */
scif_clk: scif {
compatible = "fixed-clock";
@ -142,6 +149,16 @@ soc {
#size-cells = <2>;
ranges;
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a7791-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
resets = <&cpg 402>;
status = "disabled";
};
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7791",
"renesas,rcar-gen2-gpio";
@ -407,7 +424,7 @@ icram1: sram@e63c0000 {
smp-sram@0 {
compatible = "renesas,smp-sram";
reg = <0 0x10>;
reg = <0 0x100>;
};
};
@ -1621,6 +1638,24 @@ vsp@fe938000 {
resets = <&cpg 127>;
};
fdp1@fe940000 {
compatible = "renesas,fdp1";
reg = <0 0xfe940000 0 0x2400>;
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 119>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
resets = <&cpg 119>;
};
fdp1@fe944000 {
compatible = "renesas,fdp1";
reg = <0 0xfe944000 0 0x2400>;
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 118>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
resets = <&cpg 118>;
};
jpu: jpeg-codec@fe980000 {
compatible = "renesas,jpu-r8a7791",
"renesas,rcar-gen2-jpu";

5
arch/arm/boot/dts/r8a7792-blanche.dts
View File

@ -239,6 +239,11 @@ du1_pins: du1 {
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";

16
arch/arm/boot/dts/r8a7792-wheat.dts
View File

@ -168,6 +168,11 @@ du1_pins: du1 {
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
@ -240,9 +245,15 @@ &i2c4 {
status = "okay";
clock-frequency = <400000>;
/*
* The adv75xx resets its addresses to defaults during low power mode.
* Because we have two ADV7513 devices on the same bus, we must change
* both of them away from the defaults so that they do not conflict.
*/
hdmi@3d {
compatible = "adi,adv7513";
reg = <0x3d>;
reg = <0x3d>, <0x2d>, <0x4d>, <0x5d>;
reg-names = "main", "cec", "edid", "packet";
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
@ -272,7 +283,8 @@ adv7513_0_out: endpoint {
hdmi@39 {
compatible = "adi,adv7513";
reg = <0x39>;
reg = <0x39>, <0x29>, <0x49>, <0x59>;
reg-names = "main", "cec", "edid", "packet";
adi,input-depth = <8>;
adi,input-colorspace = "rgb";

19
arch/arm/boot/dts/r8a7792.dtsi
View File

@ -85,6 +85,13 @@ extal_clk: extal {
clock-frequency = <0>;
};
pmu {
compatible = "arm,cortex-a15-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
/* External SCIF clock */
scif_clk: scif {
compatible = "fixed-clock";
@ -101,6 +108,16 @@ soc {
#size-cells = <2>;
ranges;
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a7792-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 402>;
status = "disabled";
};
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7792",
"renesas,rcar-gen2-gpio";
@ -341,7 +358,7 @@ icram1: sram@e63c0000 {
smp-sram@0 {
compatible = "renesas,smp-sram";
reg = <0 0x10>;
reg = <0 0x100>;
};
};

11
arch/arm/boot/dts/r8a7793-gose.dts
View File

@ -595,6 +595,11 @@ &cmt0 {
status = "okay";
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
@ -754,9 +759,6 @@ &vin0 {
pinctrl-names = "default";
port {
#address-cells = <1>;
#size-cells = <0>;
vin0ep2: endpoint {
remote-endpoint = <&adv7612_out>;
bus-width = <24>;
@ -776,9 +778,6 @@ &vin1 {
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
vin1ep: endpoint {
remote-endpoint = <&adv7180_out>;
bus-width = <8>;

37
arch/arm/boot/dts/r8a7793.dtsi
View File

@ -110,6 +110,13 @@ extal_clk: extal {
clock-frequency = <0>;
};
pmu {
compatible = "arm,cortex-a15-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
/* External SCIF clock */
scif_clk: scif {
compatible = "fixed-clock";
@ -126,6 +133,16 @@ soc {
#size-cells = <2>;
ranges;
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a7793-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
resets = <&cpg 402>;
status = "disabled";
};
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7793",
"renesas,rcar-gen2-gpio";
@ -392,7 +409,7 @@ icram1: sram@e63c0000 {
smp-sram@0 {
compatible = "renesas,smp-sram";
reg = <0 0x10>;
reg = <0 0x100>;
};
};
@ -1290,6 +1307,24 @@ gic: interrupt-controller@f1001000 {
resets = <&cpg 408>;
};
fdp1@fe940000 {
compatible = "renesas,fdp1";
reg = <0 0xfe940000 0 0x2400>;
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 119>;
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
resets = <&cpg 119>;
};
fdp1@fe944000 {
compatible = "renesas,fdp1";
reg = <0 0xfe944000 0 0x2400>;
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 118>;
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
resets = <&cpg 118>;
};
du: display@feb00000 {
compatible = "renesas,du-r8a7793";
reg = <0 0xfeb00000 0 0x40000>,

14
arch/arm/boot/dts/r8a7794-alt.dts
View File

@ -181,6 +181,12 @@ adv7180: endpoint {
};
};
};
eeprom@50 {
compatible = "renesas,r1ex24002", "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
};
/*
@ -330,6 +336,11 @@ &mmcif0 {
status = "okay";
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
@ -375,9 +386,6 @@ &vin0 {
pinctrl-names = "default";
port {
#address-cells = <1>;
#size-cells = <0>;
vin0ep: endpoint {
remote-endpoint = <&adv7180>;
bus-width = <8>;

8
arch/arm/boot/dts/r8a7794-silk.dts
View File

@ -475,9 +475,6 @@ &vin0 {
pinctrl-names = "default";
port {
#address-cells = <1>;
#size-cells = <0>;
vin0ep: endpoint {
remote-endpoint = <&adv7180>;
bus-width = <8>;
@ -540,6 +537,11 @@ dai0 {
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&ssi1 {
shared-pin;
};

28
arch/arm/boot/dts/r8a7794.dtsi
View File

@ -103,6 +103,13 @@ extal_clk: extal {
clock-frequency = <0>;
};
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
/* External SCIF clock */
scif_clk: scif {
compatible = "fixed-clock";
@ -119,6 +126,16 @@ soc {
#size-cells = <2>;
ranges;
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a7794-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
resets = <&cpg 402>;
status = "disabled";
};
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7794",
"renesas,rcar-gen2-gpio";
@ -348,7 +365,7 @@ icram1: sram@e63c0000 {
smp-sram@0 {
compatible = "renesas,smp-sram";
reg = <0 0x10>;
reg = <0 0x100>;
};
};
@ -1323,6 +1340,15 @@ vsp@fe930000 {
resets = <&cpg 128>;
};
fdp1@fe940000 {
compatible = "renesas,fdp1";
reg = <0 0xfe940000 0 0x2400>;
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 119>;
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
resets = <&cpg 119>;
};
du: display@feb00000 {
compatible = "renesas,du-r8a7794";
reg = <0 0xfeb00000 0 0x40000>;

9
arch/arm/boot/dts/sh73a0.dtsi
View File

@ -22,7 +22,7 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
@ -31,7 +31,7 @@ cpu@0 {
power-domains = <&pd_a2sl>;
next-level-cache = <&L2>;
};
cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
@ -91,6 +91,7 @@ pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
cmt1: timer@e6138000 {
@ -336,7 +337,7 @@ sdhi1: sd@ee120000 {
GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
power-domains = <&pd_a3sp>;
toshiba,mmc-wrprotect-disable;
disable-wp;
cap-sd-highspeed;
status = "disabled";
};
@ -348,7 +349,7 @@ sdhi2: sd@ee140000 {
GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
power-domains = <&pd_a3sp>;
toshiba,mmc-wrprotect-disable;
disable-wp;
cap-sd-highspeed;
status = "disabled";
};