mirror of https://gitee.com/openkylin/linux.git
ARMv8 Juno/Vexpress updates/cleanups for v4.18
1. Add the missing connections to the STM output port as all endpoint
connections must be bidirectional.
2. Replace all the custom OF graph endpoint node names with the standard
'endpoint'
3. Cleanup to replace all underscores('_') with hyphens('-') in the
device node names
4. Syntactic restructuring of motherboard include file so that it can be
included at the top of any other DTS file as it should be rather than
existing include in the middle of the file at a specific location
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABCAAGBQJa+av7AAoJEABBurwxfuKYF7IQALj10J8sxdG9Os9AqvzsLO/+
CFziHD9oY+PjZnp9txMDCTtdFBqq5TS1vXvYB6E+gxH7LAfl76rnNH6UZeYPooVD
P2rBdK4n46/VfS3F4Z+PQFYgme8XmDyx/pK2uZbgxukGU0VhNPLlzP64tqF1Ky4J
iq8nkFeXJEq6e5J7qwAMM8oKnEaZh7Z93LN7FsHgeEQiocB9OHBNnB/FtCGQWk8Z
mc7OuoBjUMGSPQ4ucma0oWp7NdnBf4eXyP3UzxHusOdWR0cU++c9FLa1Y2qKnX7T
3HL6GVamOBKUP54nKiHB7Aj0kASWjYam2YdwSvlc3jIbCyRoh/Tgk6+UN9OdSiCf
vt0MaVigMhC9lw/BCA2LB0n0fyw45Yg1LQBLLc3NENlngAGJYM0E6waOpcmKsFu6
keo3vS9XxLkuy0qmzUUyzDdRuNQZNeAS4gbnTKsWdFmIv3sxxOqIrHNno4jDf1bL
P0gmxcQjZ0olbpGWzVALqvYgr2axyIM9QCEZa7HlDfemN70jYAaNapw/An2l10P6
Wfi6YT5/+jEwCiiPCtWe8+XX4yn+vgv6JCHI28tbglKIcFyOp14pIDHQhvw4FIEf
nRbjgN/ntn0cYElgCpekfN3ahbVjkYi0n+2WGlW6yitEi8ZH10lw7YXV4d6KqyOC
UL30JZ6H1zPLxQi0sGKs
=D/b9
-----END PGP SIGNATURE-----
Merge tag 'juno-updates-4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt
ARMv8 Juno/Vexpress updates/cleanups for v4.18
1. Add the missing connections to the STM output port as all endpoint
connections must be bidirectional.
2. Replace all the custom OF graph endpoint node names with the standard
'endpoint'
3. Cleanup to replace all underscores('_') with hyphens('-') in the
device node names
4. Syntactic restructuring of motherboard include file so that it can be
included at the top of any other DTS file as it should be rather than
existing include in the middle of the file at a specific location
* tag 'juno-updates-4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: juno/rtsm: re-structure motherboard includes
arm64: dts: juno: replace '_' with '-' in node names
arm64: dts: juno: Fix "debounce-interval" property misspelling
arm64: dts: juno: fix OF graph endpoint node names
arm64: dts: juno: fix missing Coresight STM graph connection
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
171b118534
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@ -1,5 +1,6 @@
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|||
// SPDX-License-Identifier: GPL-2.0
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#include "juno-clocks.dtsi"
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#include "juno-motherboard.dtsi"
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/ {
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/*
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@ -572,14 +573,14 @@ soc {
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thermal-sensors = <&scpi_sensors0 3>;
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};
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big_cluster_thermal_zone: big_cluster {
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big_cluster_thermal_zone: big-cluster {
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polling-delay = <1000>;
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polling-delay-passive = <100>;
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thermal-sensors = <&scpi_sensors0 21>;
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status = "disabled";
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};
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little_cluster_thermal_zone: little_cluster {
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little_cluster_thermal_zone: little-cluster {
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polling-delay = <1000>;
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polling-delay-passive = <100>;
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thermal-sensors = <&scpi_sensors0 22>;
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@ -677,7 +678,7 @@ hdlcd@7ff50000 {
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clock-names = "pxlclk";
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port {
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hdlcd1_output: hdlcd1-endpoint {
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hdlcd1_output: endpoint {
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remote-endpoint = <&tda998x_1_input>;
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};
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};
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@ -692,7 +693,7 @@ hdlcd@7ff60000 {
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clock-names = "pxlclk";
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port {
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hdlcd0_output: hdlcd0-endpoint {
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hdlcd0_output: endpoint {
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remote-endpoint = <&tda998x_0_input>;
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};
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};
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@ -720,7 +721,7 @@ hdmi-transmitter@70 {
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compatible = "nxp,tda998x";
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reg = <0x70>;
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port {
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tda998x_0_input: tda998x-0-endpoint {
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tda998x_0_input: endpoint {
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remote-endpoint = <&hdlcd0_output>;
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};
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};
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@ -730,7 +731,7 @@ hdmi-transmitter@71 {
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compatible = "nxp,tda998x";
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reg = <0x71>;
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port {
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tda998x_1_input: tda998x-1-endpoint {
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tda998x_1_input: endpoint {
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remote-endpoint = <&hdlcd1_output>;
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};
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};
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@ -795,8 +796,6 @@ smb@8000000 {
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<0 0 10 &gic 0 0 0 167 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 11 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 12 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>;
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/include/ "juno-motherboard.dtsi"
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};
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site2: tlx@60000000 {
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|
|
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|||
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@ -7,6 +7,8 @@
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*
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*/
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/ {
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smb@8000000 {
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mb_clk24mhz: clk24mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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|
|
@ -54,46 +56,46 @@ mb_fixed_3v3: mcc-sb-3v3 {
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regulator-always-on;
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};
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gpio_keys {
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gpio-keys {
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compatible = "gpio-keys";
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power-button {
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debounce_interval = <50>;
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debounce-interval = <50>;
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wakeup-source;
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linux,code = <116>;
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label = "POWER";
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gpios = <&iofpga_gpio0 0 0x4>;
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};
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home-button {
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debounce_interval = <50>;
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debounce-interval = <50>;
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wakeup-source;
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linux,code = <102>;
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label = "HOME";
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gpios = <&iofpga_gpio0 1 0x4>;
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};
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rlock-button {
|
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debounce_interval = <50>;
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debounce-interval = <50>;
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wakeup-source;
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linux,code = <152>;
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label = "RLOCK";
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gpios = <&iofpga_gpio0 2 0x4>;
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};
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||||
vol-up-button {
|
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debounce_interval = <50>;
|
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debounce-interval = <50>;
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wakeup-source;
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linux,code = <115>;
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label = "VOL+";
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gpios = <&iofpga_gpio0 3 0x4>;
|
||||
};
|
||||
vol-down-button {
|
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debounce_interval = <50>;
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debounce-interval = <50>;
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wakeup-source;
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linux,code = <114>;
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label = "VOL-";
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gpios = <&iofpga_gpio0 4 0x4>;
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};
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nmi-button {
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debounce_interval = <50>;
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debounce-interval = <50>;
|
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wakeup-source;
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linux,code = <99>;
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label = "NMI";
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||||
|
|
@ -287,3 +289,5 @@ iofpga_gpio0: gpio@1d0000 {
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|||
};
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};
|
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};
|
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};
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};
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|
|
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|||
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@ -201,7 +201,7 @@ A53_L2: l2-cache1 {
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|||
};
|
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};
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pmu_a57 {
|
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pmu-a57 {
|
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compatible = "arm,cortex-a57-pmu";
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interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
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@ -209,7 +209,7 @@ pmu_a57 {
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<&A57_1>;
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};
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pmu_a53 {
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pmu-a53 {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
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||||
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@ -278,6 +278,10 @@ &replicator_in_port0 {
|
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remote-endpoint = <&csys2_funnel_out_port>;
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||||
};
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&csys1_funnel_in_port0 {
|
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remote-endpoint = <&stm_out_port>;
|
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};
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&stm_out_port {
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remote-endpoint = <&csys1_funnel_in_port0>;
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};
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|
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|||
|
|
@ -201,7 +201,7 @@ A53_L2: l2-cache1 {
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|||
};
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||||
};
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||||
|
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pmu_a72 {
|
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pmu-a72 {
|
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compatible = "arm,cortex-a72-pmu";
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interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
|
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<GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
|
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|
|
@ -209,7 +209,7 @@ pmu_a72 {
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<&A72_1>;
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};
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pmu_a53 {
|
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pmu-a53 {
|
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
|
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<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
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||||
|
|
@ -278,6 +278,10 @@ &replicator_in_port0 {
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|||
remote-endpoint = <&csys2_funnel_out_port>;
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||||
};
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&csys1_funnel_in_port0 {
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remote-endpoint = <&stm_out_port>;
|
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};
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&stm_out_port {
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remote-endpoint = <&csys1_funnel_in_port0>;
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};
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|
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|||
|
|
@ -200,7 +200,7 @@ A53_L2: l2-cache1 {
|
|||
};
|
||||
};
|
||||
|
||||
pmu_a57 {
|
||||
pmu-a57 {
|
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compatible = "arm,cortex-a57-pmu";
|
||||
interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
|
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<GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
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|
@ -208,7 +208,7 @@ pmu_a57 {
|
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<&A57_1>;
|
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};
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pmu_a53 {
|
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pmu-a53 {
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compatible = "arm,cortex-a53-pmu";
|
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
|
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<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
|
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|
|
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|||
|
|
@ -12,6 +12,8 @@
|
|||
|
||||
/memreserve/ 0x80000000 0x00010000;
|
||||
|
||||
#include "rtsm_ve-motherboard.dtsi"
|
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|
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/ {
|
||||
model = "RTSM_VE_AEMv8A";
|
||||
compatible = "arm,rtsm_ve,aemv8a", "arm,vexpress";
|
||||
|
|
@ -162,7 +164,5 @@ smb@8000000 {
|
|||
<0 0 40 &gic 0 40 4>,
|
||||
<0 0 41 &gic 0 41 4>,
|
||||
<0 0 42 &gic 0 42 4>;
|
||||
|
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/include/ "rtsm_ve-motherboard.dtsi"
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -7,270 +7,273 @@
|
|||
*
|
||||
* VEMotherBoard.lisa
|
||||
*/
|
||||
|
||||
motherboard {
|
||||
arm,v2m-memory-map = "rs1";
|
||||
compatible = "arm,vexpress,v2m-p1", "simple-bus";
|
||||
#address-cells = <2>; /* SMB chipselect number and offset */
|
||||
#size-cells = <1>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
|
||||
flash@0,00000000 {
|
||||
compatible = "arm,vexpress-flash", "cfi-flash";
|
||||
reg = <0 0x00000000 0x04000000>,
|
||||
<4 0x00000000 0x04000000>;
|
||||
bank-width = <4>;
|
||||
};
|
||||
|
||||
v2m_video_ram: vram@2,00000000 {
|
||||
compatible = "arm,vexpress-vram";
|
||||
reg = <2 0x00000000 0x00800000>;
|
||||
};
|
||||
|
||||
ethernet@2,02000000 {
|
||||
compatible = "smsc,lan91c111";
|
||||
reg = <2 0x02000000 0x10000>;
|
||||
interrupts = <15>;
|
||||
};
|
||||
|
||||
v2m_clk24mhz: clk24mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "v2m:clk24mhz";
|
||||
};
|
||||
|
||||
v2m_refclk1mhz: refclk1mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <1000000>;
|
||||
clock-output-names = "v2m:refclk1mhz";
|
||||
};
|
||||
|
||||
v2m_refclk32khz: refclk32khz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "v2m:refclk32khz";
|
||||
};
|
||||
|
||||
iofpga@3,00000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
/ {
|
||||
smb@8000000 {
|
||||
motherboard {
|
||||
arm,v2m-memory-map = "rs1";
|
||||
compatible = "arm,vexpress,v2m-p1", "simple-bus";
|
||||
#address-cells = <2>; /* SMB chipselect number and offset */
|
||||
#size-cells = <1>;
|
||||
ranges = <0 3 0 0x200000>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
|
||||
v2m_sysreg: sysreg@10000 {
|
||||
compatible = "arm,vexpress-sysreg";
|
||||
reg = <0x010000 0x1000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
flash@0,00000000 {
|
||||
compatible = "arm,vexpress-flash", "cfi-flash";
|
||||
reg = <0 0x00000000 0x04000000>,
|
||||
<4 0x00000000 0x04000000>;
|
||||
bank-width = <4>;
|
||||
};
|
||||
|
||||
v2m_sysctl: sysctl@20000 {
|
||||
compatible = "arm,sp810", "arm,primecell";
|
||||
reg = <0x020000 0x1000>;
|
||||
clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
|
||||
clock-names = "refclk", "timclk", "apb_pclk";
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
|
||||
assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
|
||||
assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
|
||||
v2m_video_ram: vram@2,00000000 {
|
||||
compatible = "arm,vexpress-vram";
|
||||
reg = <2 0x00000000 0x00800000>;
|
||||
};
|
||||
|
||||
aaci@40000 {
|
||||
compatible = "arm,pl041", "arm,primecell";
|
||||
reg = <0x040000 0x1000>;
|
||||
interrupts = <11>;
|
||||
clocks = <&v2m_clk24mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
ethernet@2,02000000 {
|
||||
compatible = "smsc,lan91c111";
|
||||
reg = <2 0x02000000 0x10000>;
|
||||
interrupts = <15>;
|
||||
};
|
||||
|
||||
mmci@50000 {
|
||||
compatible = "arm,pl180", "arm,primecell";
|
||||
reg = <0x050000 0x1000>;
|
||||
interrupts = <9 10>;
|
||||
cd-gpios = <&v2m_sysreg 0 0>;
|
||||
wp-gpios = <&v2m_sysreg 1 0>;
|
||||
max-frequency = <12000000>;
|
||||
vmmc-supply = <&v2m_fixed_3v3>;
|
||||
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
|
||||
clock-names = "mclk", "apb_pclk";
|
||||
v2m_clk24mhz: clk24mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "v2m:clk24mhz";
|
||||
};
|
||||
|
||||
kmi@60000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
reg = <0x060000 0x1000>;
|
||||
interrupts = <12>;
|
||||
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
v2m_refclk1mhz: refclk1mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <1000000>;
|
||||
clock-output-names = "v2m:refclk1mhz";
|
||||
};
|
||||
|
||||
kmi@70000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
reg = <0x070000 0x1000>;
|
||||
interrupts = <13>;
|
||||
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
v2m_refclk32khz: refclk32khz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "v2m:refclk32khz";
|
||||
};
|
||||
|
||||
v2m_serial0: uart@90000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x090000 0x1000>;
|
||||
interrupts = <5>;
|
||||
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
iofpga@3,00000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 3 0 0x200000>;
|
||||
|
||||
v2m_serial1: uart@a0000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x0a0000 0x1000>;
|
||||
interrupts = <6>;
|
||||
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_serial2: uart@b0000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x0b0000 0x1000>;
|
||||
interrupts = <7>;
|
||||
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_serial3: uart@c0000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x0c0000 0x1000>;
|
||||
interrupts = <8>;
|
||||
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
wdt@f0000 {
|
||||
compatible = "arm,sp805", "arm,primecell";
|
||||
reg = <0x0f0000 0x1000>;
|
||||
interrupts = <0>;
|
||||
clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
|
||||
clock-names = "wdogclk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_timer01: timer@110000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x110000 0x1000>;
|
||||
interrupts = <2>;
|
||||
clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
|
||||
clock-names = "timclken1", "timclken2", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_timer23: timer@120000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x120000 0x1000>;
|
||||
interrupts = <3>;
|
||||
clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
|
||||
clock-names = "timclken1", "timclken2", "apb_pclk";
|
||||
};
|
||||
|
||||
rtc@170000 {
|
||||
compatible = "arm,pl031", "arm,primecell";
|
||||
reg = <0x170000 0x1000>;
|
||||
interrupts = <4>;
|
||||
clocks = <&v2m_clk24mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
clcd@1f0000 {
|
||||
compatible = "arm,pl111", "arm,primecell";
|
||||
reg = <0x1f0000 0x1000>;
|
||||
interrupt-names = "combined";
|
||||
interrupts = <14>;
|
||||
clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
|
||||
clock-names = "clcdclk", "apb_pclk";
|
||||
arm,pl11x,framebuffer = <0x18000000 0x00180000>;
|
||||
memory-region = <&v2m_video_ram>;
|
||||
max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */
|
||||
|
||||
port {
|
||||
v2m_clcd_pads: endpoint {
|
||||
remote-endpoint = <&v2m_clcd_panel>;
|
||||
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
|
||||
};
|
||||
v2m_sysreg: sysreg@10000 {
|
||||
compatible = "arm,vexpress-sysreg";
|
||||
reg = <0x010000 0x1000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
panel {
|
||||
compatible = "panel-dpi";
|
||||
v2m_sysctl: sysctl@20000 {
|
||||
compatible = "arm,sp810", "arm,primecell";
|
||||
reg = <0x020000 0x1000>;
|
||||
clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
|
||||
clock-names = "refclk", "timclk", "apb_pclk";
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
|
||||
assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
|
||||
assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
|
||||
};
|
||||
|
||||
aaci@40000 {
|
||||
compatible = "arm,pl041", "arm,primecell";
|
||||
reg = <0x040000 0x1000>;
|
||||
interrupts = <11>;
|
||||
clocks = <&v2m_clk24mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
mmci@50000 {
|
||||
compatible = "arm,pl180", "arm,primecell";
|
||||
reg = <0x050000 0x1000>;
|
||||
interrupts = <9 10>;
|
||||
cd-gpios = <&v2m_sysreg 0 0>;
|
||||
wp-gpios = <&v2m_sysreg 1 0>;
|
||||
max-frequency = <12000000>;
|
||||
vmmc-supply = <&v2m_fixed_3v3>;
|
||||
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
|
||||
clock-names = "mclk", "apb_pclk";
|
||||
};
|
||||
|
||||
kmi@60000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
reg = <0x060000 0x1000>;
|
||||
interrupts = <12>;
|
||||
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
kmi@70000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
reg = <0x070000 0x1000>;
|
||||
interrupts = <13>;
|
||||
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_serial0: uart@90000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x090000 0x1000>;
|
||||
interrupts = <5>;
|
||||
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_serial1: uart@a0000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x0a0000 0x1000>;
|
||||
interrupts = <6>;
|
||||
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_serial2: uart@b0000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x0b0000 0x1000>;
|
||||
interrupts = <7>;
|
||||
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_serial3: uart@c0000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x0c0000 0x1000>;
|
||||
interrupts = <8>;
|
||||
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
wdt@f0000 {
|
||||
compatible = "arm,sp805", "arm,primecell";
|
||||
reg = <0x0f0000 0x1000>;
|
||||
interrupts = <0>;
|
||||
clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
|
||||
clock-names = "wdogclk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_timer01: timer@110000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x110000 0x1000>;
|
||||
interrupts = <2>;
|
||||
clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
|
||||
clock-names = "timclken1", "timclken2", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_timer23: timer@120000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x120000 0x1000>;
|
||||
interrupts = <3>;
|
||||
clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
|
||||
clock-names = "timclken1", "timclken2", "apb_pclk";
|
||||
};
|
||||
|
||||
rtc@170000 {
|
||||
compatible = "arm,pl031", "arm,primecell";
|
||||
reg = <0x170000 0x1000>;
|
||||
interrupts = <4>;
|
||||
clocks = <&v2m_clk24mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
clcd@1f0000 {
|
||||
compatible = "arm,pl111", "arm,primecell";
|
||||
reg = <0x1f0000 0x1000>;
|
||||
interrupt-names = "combined";
|
||||
interrupts = <14>;
|
||||
clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
|
||||
clock-names = "clcdclk", "apb_pclk";
|
||||
arm,pl11x,framebuffer = <0x18000000 0x00180000>;
|
||||
memory-region = <&v2m_video_ram>;
|
||||
max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */
|
||||
|
||||
port {
|
||||
v2m_clcd_panel: endpoint {
|
||||
remote-endpoint = <&v2m_clcd_pads>;
|
||||
v2m_clcd_pads: endpoint {
|
||||
remote-endpoint = <&v2m_clcd_panel>;
|
||||
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
|
||||
};
|
||||
};
|
||||
|
||||
panel-timing {
|
||||
clock-frequency = <63500127>;
|
||||
hactive = <1024>;
|
||||
hback-porch = <152>;
|
||||
hfront-porch = <48>;
|
||||
hsync-len = <104>;
|
||||
vactive = <768>;
|
||||
vback-porch = <23>;
|
||||
vfront-porch = <3>;
|
||||
vsync-len = <4>;
|
||||
panel {
|
||||
compatible = "panel-dpi";
|
||||
|
||||
port {
|
||||
v2m_clcd_panel: endpoint {
|
||||
remote-endpoint = <&v2m_clcd_pads>;
|
||||
};
|
||||
};
|
||||
|
||||
panel-timing {
|
||||
clock-frequency = <63500127>;
|
||||
hactive = <1024>;
|
||||
hback-porch = <152>;
|
||||
hfront-porch = <48>;
|
||||
hsync-len = <104>;
|
||||
vactive = <768>;
|
||||
vback-porch = <23>;
|
||||
vfront-porch = <3>;
|
||||
vsync-len = <4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
virtio-block@130000 {
|
||||
compatible = "virtio,mmio";
|
||||
reg = <0x130000 0x200>;
|
||||
interrupts = <42>;
|
||||
};
|
||||
};
|
||||
|
||||
virtio-block@130000 {
|
||||
compatible = "virtio,mmio";
|
||||
reg = <0x130000 0x200>;
|
||||
interrupts = <42>;
|
||||
};
|
||||
};
|
||||
|
||||
v2m_fixed_3v3: v2m-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
mcc {
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
||||
|
||||
v2m_oscclk1: oscclk1 {
|
||||
/* CLCD clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 1>;
|
||||
freq-range = <23750000 63500000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "v2m:oscclk1";
|
||||
v2m_fixed_3v3: v2m-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reset {
|
||||
compatible = "arm,vexpress-reset";
|
||||
arm,vexpress-sysreg,func = <5 0>;
|
||||
};
|
||||
mcc {
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
||||
|
||||
muxfpga {
|
||||
compatible = "arm,vexpress-muxfpga";
|
||||
arm,vexpress-sysreg,func = <7 0>;
|
||||
};
|
||||
v2m_oscclk1: oscclk1 {
|
||||
/* CLCD clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 1>;
|
||||
freq-range = <23750000 63500000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "v2m:oscclk1";
|
||||
};
|
||||
|
||||
shutdown {
|
||||
compatible = "arm,vexpress-shutdown";
|
||||
arm,vexpress-sysreg,func = <8 0>;
|
||||
};
|
||||
reset {
|
||||
compatible = "arm,vexpress-reset";
|
||||
arm,vexpress-sysreg,func = <5 0>;
|
||||
};
|
||||
|
||||
reboot {
|
||||
compatible = "arm,vexpress-reboot";
|
||||
arm,vexpress-sysreg,func = <9 0>;
|
||||
};
|
||||
muxfpga {
|
||||
compatible = "arm,vexpress-muxfpga";
|
||||
arm,vexpress-sysreg,func = <7 0>;
|
||||
};
|
||||
|
||||
dvimode {
|
||||
compatible = "arm,vexpress-dvimode";
|
||||
arm,vexpress-sysreg,func = <11 0>;
|
||||
shutdown {
|
||||
compatible = "arm,vexpress-shutdown";
|
||||
arm,vexpress-sysreg,func = <8 0>;
|
||||
};
|
||||
|
||||
reboot {
|
||||
compatible = "arm,vexpress-reboot";
|
||||
arm,vexpress-sysreg,func = <9 0>;
|
||||
};
|
||||
|
||||
dvimode {
|
||||
compatible = "arm,vexpress-dvimode";
|
||||
arm,vexpress-sysreg,func = <11 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue