mirror of https://gitee.com/openkylin/linux.git
Merge tag 'sunxi-clk-3.14-for-maxime' of https://bitbucket.org/emiliolopez/linux into sunxi/dt-for-3.14
Allwinner sunXi SoCs DT changes for clocks This contains the DT parts of the "[PATCH v3 00/13] clk: sunxi: add PLL5 and PLL6 support" series. It adds DT nodes for PLL4/5/6 and mod0 clocks on most sunxi platforms.
This commit is contained in:
commit
2c6b473bfa
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@ -70,6 +70,29 @@ pll1: pll1@01c20000 {
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clocks = <&osc24M>;
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};
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pll4: pll4@01c20018 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-pll1-clk";
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reg = <0x01c20018 0x4>;
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clocks = <&osc24M>;
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};
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pll5: pll5@01c20020 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-pll5-clk";
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reg = <0x01c20020 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll5_ddr", "pll5_other";
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};
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pll6: pll6@01c20028 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-pll6-clk";
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reg = <0x01c20028 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll6_sata", "pll6_other", "pll6";
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};
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/* dummy is 200M */
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cpu: cpu@01c20054 {
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#clock-cells = <0>;
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@ -135,12 +158,11 @@ apb0_gates: apb0_gates@01c20068 {
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"apb0_ir1", "apb0_keypad";
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};
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/* dummy is pll62 */
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apb1_mux: apb1_mux@01c20058 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-apb1-mux-clk";
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reg = <0x01c20058 0x4>;
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clocks = <&osc24M>, <&dummy>, <&osc32k>;
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clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
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};
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apb1: apb1@01c20058 {
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@ -162,6 +184,126 @@ apb1_gates: apb1_gates@01c2006c {
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"apb1_uart4", "apb1_uart5", "apb1_uart6",
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"apb1_uart7";
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};
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nand_clk: clk@01c20080 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c20080 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "nand";
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};
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ms_clk: clk@01c20084 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c20084 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "ms";
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};
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mmc0_clk: clk@01c20088 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c20088 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc0";
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};
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mmc1_clk: clk@01c2008c {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c2008c 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc1";
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};
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mmc2_clk: clk@01c20090 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c20090 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc2";
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};
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mmc3_clk: clk@01c20094 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c20094 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc3";
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};
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ts_clk: clk@01c20098 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c20098 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "ts";
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};
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ss_clk: clk@01c2009c {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c2009c 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "ss";
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};
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spi0_clk: clk@01c200a0 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c200a0 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "spi0";
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};
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spi1_clk: clk@01c200a4 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c200a4 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "spi1";
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};
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spi2_clk: clk@01c200a8 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c200a8 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "spi2";
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};
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pata_clk: clk@01c200ac {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c200ac 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "pata";
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};
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ir0_clk: clk@01c200b0 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c200b0 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "ir0";
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};
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ir1_clk: clk@01c200b4 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c200b4 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "ir1";
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};
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spi3_clk: clk@01c200d4 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c200d4 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "spi3";
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};
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};
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soc@01c00000 {
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@ -67,6 +67,29 @@ pll1: pll1@01c20000 {
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clocks = <&osc24M>;
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};
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pll4: pll4@01c20018 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-pll1-clk";
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reg = <0x01c20018 0x4>;
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clocks = <&osc24M>;
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};
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pll5: pll5@01c20020 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-pll5-clk";
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reg = <0x01c20020 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll5_ddr", "pll5_other";
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};
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pll6: pll6@01c20028 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-pll6-clk";
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reg = <0x01c20028 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll6_sata", "pll6_other", "pll6";
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};
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/* dummy is 200M */
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cpu: cpu@01c20054 {
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#clock-cells = <0>;
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@ -127,12 +150,11 @@ apb0_gates: apb0_gates@01c20068 {
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"apb0_ir", "apb0_keypad";
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};
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/* dummy is pll62 */
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apb1_mux: apb1_mux@01c20058 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-apb1-mux-clk";
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reg = <0x01c20058 0x4>;
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clocks = <&osc24M>, <&dummy>, <&osc32k>;
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clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
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};
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apb1: apb1@01c20058 {
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@ -151,6 +173,102 @@ apb1_gates: apb1_gates@01c2006c {
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"apb1_i2c2", "apb1_uart0", "apb1_uart1",
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"apb1_uart2", "apb1_uart3";
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};
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nand_clk: clk@01c20080 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c20080 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "nand";
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};
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ms_clk: clk@01c20084 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c20084 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "ms";
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};
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mmc0_clk: clk@01c20088 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c20088 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc0";
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};
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mmc1_clk: clk@01c2008c {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c2008c 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc1";
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};
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mmc2_clk: clk@01c20090 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c20090 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc2";
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};
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ts_clk: clk@01c20098 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c20098 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "ts";
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};
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ss_clk: clk@01c2009c {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c2009c 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "ss";
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};
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spi0_clk: clk@01c200a0 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c200a0 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "spi0";
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};
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spi1_clk: clk@01c200a4 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c200a4 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "spi1";
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};
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spi2_clk: clk@01c200a8 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c200a8 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "spi2";
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};
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ir0_clk: clk@01c200b0 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c200b0 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "ir0";
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};
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mbus_clk: clk@01c2015c {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c2015c 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mbus";
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||||
};
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||||
};
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||||
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||||
soc@01c00000 {
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||||
|
|
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@ -67,6 +67,29 @@ pll1: pll1@01c20000 {
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|||
clocks = <&osc24M>;
|
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};
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||||
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||||
pll4: pll4@01c20018 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-pll1-clk";
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reg = <0x01c20018 0x4>;
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clocks = <&osc24M>;
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};
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||||
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pll5: pll5@01c20020 {
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#clock-cells = <1>;
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||||
compatible = "allwinner,sun4i-pll5-clk";
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reg = <0x01c20020 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "pll5_ddr", "pll5_other";
|
||||
};
|
||||
|
||||
pll6: pll6@01c20028 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-pll6-clk";
|
||||
reg = <0x01c20028 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "pll6_sata", "pll6_other", "pll6";
|
||||
};
|
||||
|
||||
/* dummy is 200M */
|
||||
cpu: cpu@01c20054 {
|
||||
#clock-cells = <0>;
|
||||
|
@ -125,12 +148,11 @@ apb0_gates: apb0_gates@01c20068 {
|
|||
clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
|
||||
};
|
||||
|
||||
/* dummy is pll6 */
|
||||
apb1_mux: apb1_mux@01c20058 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-apb1-mux-clk";
|
||||
reg = <0x01c20058 0x4>;
|
||||
clocks = <&osc24M>, <&dummy>, <&osc32k>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
|
||||
};
|
||||
|
||||
apb1: apb1@01c20058 {
|
||||
|
@ -148,6 +170,102 @@ apb1_gates: apb1_gates@01c2006c {
|
|||
clock-output-names = "apb1_i2c0", "apb1_i2c1",
|
||||
"apb1_i2c2", "apb1_uart1", "apb1_uart3";
|
||||
};
|
||||
|
||||
nand_clk: clk@01c20080 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
reg = <0x01c20080 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "nand";
|
||||
};
|
||||
|
||||
ms_clk: clk@01c20084 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
reg = <0x01c20084 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "ms";
|
||||
};
|
||||
|
||||
mmc0_clk: clk@01c20088 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
reg = <0x01c20088 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mmc0";
|
||||
};
|
||||
|
||||
mmc1_clk: clk@01c2008c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
reg = <0x01c2008c 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mmc1";
|
||||
};
|
||||
|
||||
mmc2_clk: clk@01c20090 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
reg = <0x01c20090 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mmc2";
|
||||
};
|
||||
|
||||
ts_clk: clk@01c20098 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
reg = <0x01c20098 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "ts";
|
||||
};
|
||||
|
||||
ss_clk: clk@01c2009c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
reg = <0x01c2009c 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "ss";
|
||||
};
|
||||
|
||||
spi0_clk: clk@01c200a0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
reg = <0x01c200a0 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "spi0";
|
||||
};
|
||||
|
||||
spi1_clk: clk@01c200a4 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
reg = <0x01c200a4 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "spi1";
|
||||
};
|
||||
|
||||
spi2_clk: clk@01c200a8 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
reg = <0x01c200a8 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "spi2";
|
||||
};
|
||||
|
||||
ir0_clk: clk@01c200b0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
reg = <0x01c200b0 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "ir0";
|
||||
};
|
||||
|
||||
mbus_clk: clk@01c2015c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
reg = <0x01c2015c 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mbus";
|
||||
};
|
||||
};
|
||||
|
||||
soc@01c00000 {
|
||||
|
|
|
@ -66,23 +66,34 @@ pll1: pll1@01c20000 {
|
|||
clocks = <&osc24M>;
|
||||
};
|
||||
|
||||
/*
|
||||
* This is a dummy clock, to be used as placeholder on
|
||||
* other mux clocks when a specific parent clock is not
|
||||
* yet implemented. It should be dropped when the driver
|
||||
* is complete.
|
||||
*/
|
||||
pll6: pll6 {
|
||||
pll4: pll4@01c20018 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <0>;
|
||||
compatible = "allwinner,sun4i-pll1-clk";
|
||||
reg = <0x01c20018 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
};
|
||||
|
||||
pll5: pll5@01c20020 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-pll5-clk";
|
||||
reg = <0x01c20020 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "pll5_ddr", "pll5_other";
|
||||
};
|
||||
|
||||
pll6: pll6@01c20028 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-pll6-clk";
|
||||
reg = <0x01c20028 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "pll6_sata", "pll6_other", "pll6";
|
||||
};
|
||||
|
||||
cpu: cpu@01c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-cpu-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>;
|
||||
clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
|
||||
};
|
||||
|
||||
axi: axi@01c20054 {
|
||||
|
@ -141,7 +152,7 @@ apb1_mux: apb1_mux@01c20058 {
|
|||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-apb1-mux-clk";
|
||||
reg = <0x01c20058 0x4>;
|
||||
clocks = <&osc24M>, <&pll6>, <&osc32k>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
|
||||
};
|
||||
|
||||
apb1: apb1@01c20058 {
|
||||
|
@ -163,6 +174,134 @@ apb1_gates: apb1_gates@01c2006c {
|
|||
"apb1_uart2", "apb1_uart3", "apb1_uart4",
|
||||
"apb1_uart5", "apb1_uart6", "apb1_uart7";
|
||||
};
|
||||
|
||||
nand_clk: clk@01c20080 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
reg = <0x01c20080 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "nand";
|
||||
};
|
||||
|
||||
ms_clk: clk@01c20084 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
reg = <0x01c20084 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "ms";
|
||||
};
|
||||
|
||||
mmc0_clk: clk@01c20088 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
reg = <0x01c20088 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mmc0";
|
||||
};
|
||||
|
||||
mmc1_clk: clk@01c2008c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
reg = <0x01c2008c 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mmc1";
|
||||
};
|
||||
|
||||
mmc2_clk: clk@01c20090 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
reg = <0x01c20090 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mmc2";
|
||||
};
|
||||
|
||||
mmc3_clk: clk@01c20094 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
reg = <0x01c20094 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mmc3";
|
||||
};
|
||||
|
||||
ts_clk: clk@01c20098 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
reg = <0x01c20098 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "ts";
|
||||
};
|
||||
|
||||
ss_clk: clk@01c2009c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
reg = <0x01c2009c 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "ss";
|
||||
};
|
||||
|
||||
spi0_clk: clk@01c200a0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
reg = <0x01c200a0 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "spi0";
|
||||
};
|
||||
|
||||
spi1_clk: clk@01c200a4 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
reg = <0x01c200a4 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "spi1";
|
||||
};
|
||||
|
||||
spi2_clk: clk@01c200a8 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
reg = <0x01c200a8 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "spi2";
|
||||
};
|
||||
|
||||
pata_clk: clk@01c200ac {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
reg = <0x01c200ac 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "pata";
|
||||
};
|
||||
|
||||
ir0_clk: clk@01c200b0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
reg = <0x01c200b0 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "ir0";
|
||||
};
|
||||
|
||||
ir1_clk: clk@01c200b4 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
reg = <0x01c200b4 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "ir1";
|
||||
};
|
||||
|
||||
spi3_clk: clk@01c200d4 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
reg = <0x01c200d4 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "spi3";
|
||||
};
|
||||
|
||||
mbus_clk: clk@01c2015c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
reg = <0x01c2015c 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
|
||||
clock-output-names = "mbus";
|
||||
};
|
||||
};
|
||||
|
||||
soc@01c00000 {
|
||||
|
|
Loading…
Reference in New Issue