mirror of https://gitee.com/openkylin/linux.git
mvebu dt64 for 4.13 (part 1)
- Improve the mcbin support (Armada 8040 based board): add sdhci and the second 1G port - Improve crypro nodes description on Aramda 7K/8K - Use new binding for ap806 clocks - Improve mdio nodes and add xmdio on Aramda 7K/8K - Add second SGCI node on Armada 37xx - Improve the description of the Armada 3720 DB board -----BEGIN PGP SIGNATURE----- iIEEABECAEEWIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCWUTPlSMcZ3JlZ29yeS5j bGVtZW50QGZyZWUtZWxlY3Ryb25zLmNvbQAKCRALBhiOFHI71VOLAJoC5+faPv4o ob78Tena5JEbNcQtlQCeKrl7v3V4DP3BMhlBa9eguRn4RRQ= =LHta -----END PGP SIGNATURE----- Merge tag 'mvebu-dt64-4.13-1' of git://git.infradead.org/linux-mvebu into next/dt64 mvebu dt64 for 4.13 (part 1) - Improve the mcbin support (Armada 8040 based board): add sdhci and the second 1G port - Improve crypro nodes description on Aramda 7K/8K - Use new binding for ap806 clocks - Improve mdio nodes and add xmdio on Aramda 7K/8K - Add second SGCI node on Armada 37xx - Improve the description of the Armada 3720 DB board * tag 'mvebu-dt64-4.13-1' of git://git.infradead.org/linux-mvebu: arm64: dts: marvell: add xmdio nodes for 7k/8k arm64: dts: marvell: add a comment on the cp110 slave node status arm64: dts: marvell: remove cpm crypto nodes from dts files arm64: dts: marvell: cp110: enable the crypto engine at the SoC level arm64: dts: marvell: armada-3720-db: Add vqmmc regulator for SD slot arm64: dts: marvell: Enable second SDHCI controller in Armada 37xx arm64: dts: marvell: armada-37xx: Use angle bracket for each register set arm64: dts: marvell: armada-37xx: Align the compatible string arm64: dts: marvell: armada-3720-db: Add information about the V2 board arm64: dts: marvell: armada-3720-db: Sort the dts node alphabetically arm64: dts: marvell: disable the mdio nodes by default arm64: dts: marvell: explicitly enable the mdio nodes for 7k/8k DB arm64: dts: marvell: add dma-mask in crypto nodes for 7k/8k arm64: dts: marvell: 8040-mcbin: Enable 1GB Ethernet arm64: dts: marvell: cp110: add required clocks for mdio interface arm64: dts: marvell: use new binding for the system controller on ap806 arm64: dts: marvell: remove clock-output-names on ap806 arm64: dts: marvell: add second 1G port on the Armada 8040 DB arm64: dts: marvell: mcbin: add sdhci arm64: dts: marvell: add clocks for Armada AP806 XOR engines Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
commit
4623e69d1c
|
@ -42,6 +42,10 @@
|
|||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* This file is compatible with the version 1.4 and the version 2.0 of
|
||||
* the board, however the CON numbers are different between the 2
|
||||
* version
|
||||
*/
|
||||
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||||
/dts-v1/;
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||||
|
@ -76,6 +80,36 @@ usb3_phy: usb3-phy {
|
|||
compatible = "usb-nop-xceiv";
|
||||
vcc-supply = <&exp_usb3_vbus>;
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||||
};
|
||||
|
||||
vcc_sd_reg1: regulator {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "vcc_sd1";
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||||
regulator-min-microvolt = <1800000>;
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||||
regulator-max-microvolt = <3300000>;
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||||
regulator-boot-on;
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||||
|
||||
gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
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||||
gpios-states = <0>;
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||||
states = <1800000 0x1
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||||
3300000 0x0>;
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||||
enable-active-high;
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||||
};
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||||
};
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||||
|
||||
/* Gigabit module on CON19(V2.0)/CON21(V1.4) */
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||||
ð0 {
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||||
pinctrl-names = "default";
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||||
pinctrl-0 = <&rgmii_pins>;
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||||
phy-mode = "rgmii-id";
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||||
phy = <&phy0>;
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||||
status = "okay";
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||||
};
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||||
|
||||
/* Gigabit module on CON18(V2.0)/CON20(V1.4) */
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||||
ð1 {
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||||
phy-mode = "sgmii";
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||||
phy = <&phy1>;
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||||
status = "okay";
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||||
};
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||||
|
||||
&i2c0 {
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||||
|
@ -108,11 +142,46 @@ rtc@68 {
|
|||
};
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||||
};
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||||
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||||
&mdio {
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||||
status = "okay";
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||||
phy0: ethernet-phy@0 {
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||||
reg = <0>;
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||||
};
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||||
|
||||
phy1: ethernet-phy@1 {
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||||
reg = <1>;
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||||
};
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||||
};
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||||
|
||||
/* CON15(V2.0)/CON17(V1.4) : PCIe / CON15(V2.0)/CON12(V1.4) :mini-PCIe */
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&pcie0 {
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||||
status = "okay";
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||||
};
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||||
|
||||
/* CON3 */
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||||
&sata {
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status = "okay";
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||||
};
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||||
|
||||
&sdhci0 {
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||||
non-removable;
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||||
bus-width = <8>;
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||||
mmc-ddr-1_8v;
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mmc-hs400-1_8v;
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||||
marvell,pad-type = "fixed-1-8v";
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||||
status = "okay";
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||||
};
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||||
|
||||
/* SD slot module on CON14(V2.0)/CON15(V1.4) */
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&sdhci1 {
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wp-inverted;
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cd-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
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bus-width = <4>;
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||||
marvell,pad-type = "sd";
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||||
vqmmc-supply = <&vcc_sd_reg1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi0 {
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||||
status = "okay";
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pinctrl-names = "default";
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||||
|
@ -145,60 +214,23 @@ partition@210000 {
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|||
};
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};
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|
||||
/* Exported on the micro USB connector CON32 through an FTDI */
|
||||
/*
|
||||
* Exported on the micro USB connector CON30(V2.0)/CON32(V1.4) through
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||||
* an FTDI
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||||
*/
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||||
&uart0 {
|
||||
pinctrl-names = "default";
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||||
pinctrl-0 = <&uart1_pins>;
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||||
status = "okay";
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||||
};
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||||
|
||||
&sdhci0 {
|
||||
non-removable;
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||||
bus-width = <8>;
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||||
mmc-ddr-1_8v;
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||||
mmc-hs400-1_8v;
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||||
marvell,pad-type = "fixed-1-8v";
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status = "okay";
|
||||
};
|
||||
|
||||
/* CON31 */
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&usb3 {
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||||
status = "okay";
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||||
usb-phy = <&usb3_phy>;
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||||
};
|
||||
|
||||
/* CON17 (PCIe) / CON12 (mini-PCIe) */
|
||||
&pcie0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* CON27 */
|
||||
/* CON27(V2.0)/CON29(V1.4) */
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||||
&usb2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
&mdio {
|
||||
status = "okay";
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
ð0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmii_pins>;
|
||||
phy-mode = "rgmii-id";
|
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phy = <&phy0>;
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||||
status = "okay";
|
||||
};
|
||||
|
||||
ð1 {
|
||||
phy-mode = "sgmii";
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||||
phy = <&phy1>;
|
||||
/* CON29(V2.0)/CON31(V1.4) */
|
||||
&usb3 {
|
||||
status = "okay";
|
||||
usb-phy = <&usb3_phy>;
|
||||
};
|
||||
|
|
|
@ -163,7 +163,7 @@ tbg: tbg@13200 {
|
|||
|
||||
pinctrl_nb: pinctrl@13800 {
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compatible = "marvell,armada3710-nb-pinctrl",
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"syscon", "simple-mfd";
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||||
"syscon", "simple-mfd";
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||||
reg = <0x13800 0x100>, <0x13C00 0x20>;
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gpionb: gpio {
|
||||
#gpio-cells = <2>;
|
||||
|
@ -219,7 +219,7 @@ uart2_pins: uart2-pins {
|
|||
|
||||
pinctrl_sb: pinctrl@18800 {
|
||||
compatible = "marvell,armada3710-sb-pinctrl",
|
||||
"syscon", "simple-mfd";
|
||||
"syscon", "simple-mfd";
|
||||
reg = <0x18800 0x100>, <0x18C00 0x20>;
|
||||
gpiosb: gpio {
|
||||
#gpio-cells = <2>;
|
||||
|
@ -281,8 +281,8 @@ usb2: usb@5e000 {
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|||
|
||||
xor@60900 {
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||||
compatible = "marvell,armada-3700-xor";
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||||
reg = <0x60900 0x100
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||||
0x60b00 0x100>;
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||||
reg = <0x60900 0x100>,
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<0x60b00 0x100>;
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||||
|
||||
xor10 {
|
||||
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
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||||
|
@ -292,11 +292,22 @@ xor11 {
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|||
};
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||||
};
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||||
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||||
sdhci1: sdhci@d0000 {
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||||
compatible = "marvell,armada-3700-sdhci",
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"marvell,sdhci-xenon";
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||||
reg = <0xd0000 0x300>,
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||||
<0x1e808 0x4>;
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&nb_periph_clk 0>;
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||||
clock-names = "core";
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||||
status = "disabled";
|
||||
};
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||||
|
||||
sdhci0: sdhci@d8000 {
|
||||
compatible = "marvell,armada-3700-sdhci",
|
||||
"marvell,sdhci-xenon";
|
||||
reg = <0xd8000 0x300
|
||||
0x17808 0x4>;
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||||
"marvell,sdhci-xenon";
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||||
reg = <0xd8000 0x300>,
|
||||
<0x17808 0x4>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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||||
clocks = <&nb_periph_clk 0>;
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||||
clock-names = "core";
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||||
|
|
|
@ -162,6 +162,8 @@ &cpm_sdhci0 {
|
|||
};
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||||
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||||
&cpm_mdio {
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
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||||
reg = <0>;
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||||
};
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|
@ -185,7 +187,3 @@ &cpm_eth2 {
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|||
phy = <&phy1>;
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||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
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||||
&cpm_crypto {
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||||
status = "okay";
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||||
};
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||||
|
|
|
@ -125,6 +125,8 @@ &cpm_usb3_1 {
|
|||
};
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||||
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||||
&cpm_mdio {
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||||
status = "okay";
|
||||
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||||
phy1: ethernet-phy@1 {
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||||
reg = <1>;
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||||
};
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||||
|
@ -140,10 +142,6 @@ &cpm_eth2 {
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|||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
&cpm_crypto {
|
||||
status = "okay";
|
||||
};
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||||
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||||
/* CON5 on CP1 expansion */
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||||
&cps_pcie2 {
|
||||
status = "okay";
|
||||
|
@ -169,6 +167,24 @@ &cps_usb3_1 {
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|||
status = "okay";
|
||||
};
|
||||
|
||||
&cps_mdio {
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&cps_ethernet {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cps_eth1 {
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
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||||
|
||||
&ap_sdhci0 {
|
||||
status = "okay";
|
||||
bus-width = <4>;
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||||
|
|
|
@ -95,16 +95,45 @@ &uart0 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&ap_sdhci0 {
|
||||
bus-width = <8>;
|
||||
/*
|
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* Not stable in HS modes - phy needs "more calibration", so add
|
||||
* the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.
|
||||
*/
|
||||
marvell,xenon-phy-slow-mode;
|
||||
no-1-8-v;
|
||||
no-sd;
|
||||
no-sdio;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
vqmmc-supply = <&v_vddo_h>;
|
||||
};
|
||||
|
||||
&cpm_i2c0 {
|
||||
clock-frequency = <100000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpm_mdio {
|
||||
ge_phy: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpm_sata0 {
|
||||
/* CPM Lane 0 - U29 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpm_sdhci0 {
|
||||
/* U6 */
|
||||
broken-cd;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
vqmmc-supply = <&v_3_3>;
|
||||
};
|
||||
|
||||
&cpm_usb3_0 {
|
||||
/* J38? - USB2.0 only */
|
||||
status = "okay";
|
||||
|
@ -115,6 +144,17 @@ &cpm_usb3_1 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&cps_ethernet {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cps_eth1 {
|
||||
/* CPS Lane 0 - J5 (Gigabit RJ45) */
|
||||
status = "okay";
|
||||
phy = <&ge_phy>;
|
||||
phy-mode = "sgmii";
|
||||
};
|
||||
|
||||
&cps_sata0 {
|
||||
/* CPS Lane 1 - U32 */
|
||||
/* CPS Lane 3 - U31 */
|
||||
|
|
|
@ -159,6 +159,7 @@ xor@400000 {
|
|||
reg = <0x400000 0x1000>,
|
||||
<0x410000 0x1000>;
|
||||
msi-parent = <&gic_v2m0>;
|
||||
clocks = <&ap_syscon 3>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
|
@ -167,6 +168,7 @@ xor@420000 {
|
|||
reg = <0x420000 0x1000>,
|
||||
<0x430000 0x1000>;
|
||||
msi-parent = <&gic_v2m0>;
|
||||
clocks = <&ap_syscon 3>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
|
@ -175,6 +177,7 @@ xor@440000 {
|
|||
reg = <0x440000 0x1000>,
|
||||
<0x450000 0x1000>;
|
||||
msi-parent = <&gic_v2m0>;
|
||||
clocks = <&ap_syscon 3>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
|
@ -183,6 +186,7 @@ xor@460000 {
|
|||
reg = <0x460000 0x1000>,
|
||||
<0x470000 0x1000>;
|
||||
msi-parent = <&gic_v2m0>;
|
||||
clocks = <&ap_syscon 3>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
|
@ -193,7 +197,7 @@ spi0: spi@510600 {
|
|||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ap_syscon 3>;
|
||||
clocks = <&ap_clk 3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -204,7 +208,7 @@ i2c0: i2c@511000 {
|
|||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
timeout-ms = <1000>;
|
||||
clocks = <&ap_syscon 3>;
|
||||
clocks = <&ap_clk 3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -214,7 +218,7 @@ uart0: serial@512000 {
|
|||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&ap_syscon 3>;
|
||||
clocks = <&ap_clk 3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -224,7 +228,7 @@ uart1: serial@512100 {
|
|||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&ap_syscon 3>;
|
||||
clocks = <&ap_clk 3>;
|
||||
status = "disabled";
|
||||
|
||||
};
|
||||
|
@ -234,21 +238,20 @@ ap_sdhci0: sdhci@6e0000 {
|
|||
reg = <0x6e0000 0x300>;
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "core";
|
||||
clocks = <&ap_syscon 4>;
|
||||
clocks = <&ap_clk 4>;
|
||||
dma-coherent;
|
||||
marvell,xenon-phy-slow-mode;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ap_syscon: system-controller@6f4000 {
|
||||
compatible = "marvell,ap806-system-controller",
|
||||
"syscon";
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "ap-cpu-cluster-0",
|
||||
"ap-cpu-cluster-1",
|
||||
"ap-fixed", "ap-mss",
|
||||
"ap-emmc";
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x6f4000 0x1000>;
|
||||
|
||||
ap_clk: clock {
|
||||
compatible = "marvell,ap806-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -94,6 +94,16 @@ cpm_mdio: mdio@12a200 {
|
|||
#size-cells = <0>;
|
||||
compatible = "marvell,orion-mdio";
|
||||
reg = <0x12a200 0x10>;
|
||||
clocks = <&cpm_syscon0 1 9>, <&cpm_syscon0 1 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cpm_xmdio: mdio@12a600 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "marvell,xmdio";
|
||||
reg = <0x12a600 0x10>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cpm_syscon0: system-controller@440000 {
|
||||
|
@ -241,7 +251,7 @@ cpm_crypto: crypto@800000 {
|
|||
interrupt-names = "mem", "ring0", "ring1",
|
||||
"ring2", "ring3", "eip";
|
||||
clocks = <&cpm_syscon0 1 26>;
|
||||
status = "disabled";
|
||||
dma-mask = <0xff 0xffffffff>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
@ -101,6 +101,16 @@ cps_mdio: mdio@12a200 {
|
|||
#size-cells = <0>;
|
||||
compatible = "marvell,orion-mdio";
|
||||
reg = <0x12a200 0x10>;
|
||||
clocks = <&cps_syscon0 1 9>, <&cps_syscon0 1 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cps_xmdio: mdio@12a600 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "marvell,xmdio";
|
||||
reg = <0x12a600 0x10>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cps_syscon0: system-controller@440000 {
|
||||
|
@ -231,6 +241,14 @@ cps_crypto: crypto@800000 {
|
|||
interrupt-names = "mem", "ring0", "ring1",
|
||||
"ring2", "ring3", "eip";
|
||||
clocks = <&cps_syscon0 1 26>;
|
||||
dma-mask = <0xff 0xffffffff>;
|
||||
/*
|
||||
* The cryptographic engine found on the cp110
|
||||
* master is enabled by default at the SoC
|
||||
* level. Because it is not possible as of now
|
||||
* to enable two cryptographic engines in
|
||||
* parallel, disable this one by default.
|
||||
*/
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
Loading…
Reference in New Issue