mirror of https://gitee.com/openkylin/linux.git
sh-pfc: sh7722: Remove unused input_pd and input_pu ranges
The PFC SH7722 SoC data contains input_pd and input_pu ranges used to configure pull-down and pull-up resistors using the legacy non-pinconf API. That API has been removed from the driver, the ranges are thus not used anymore. Remove them. If required, configuring pull-down and pull-up resistors for the SH7722 can be implemented using the pinconf API, as done for the SH-Mobile, R-Mobile and R-Car platforms. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
This commit is contained in:
Laurent Pinchart
parent
7f975b3f1e
commit
48b888b17f
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@ -77,39 +77,6 @@ enum {
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PTZ5_IN, PTZ4_IN, PTZ3_IN, PTZ2_IN, PTZ1_IN,
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PINMUX_INPUT_END,
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PINMUX_INPUT_PULLDOWN_BEGIN,
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PTA7_IN_PD, PTA6_IN_PD, PTA5_IN_PD, PTA4_IN_PD,
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PTA3_IN_PD, PTA2_IN_PD, PTA1_IN_PD, PTA0_IN_PD,
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PTE7_IN_PD, PTE6_IN_PD, PTE5_IN_PD, PTE4_IN_PD, PTE1_IN_PD, PTE0_IN_PD,
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PTF6_IN_PD, PTF5_IN_PD, PTF4_IN_PD, PTF3_IN_PD, PTF2_IN_PD, PTF1_IN_PD,
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PTH6_IN_PD, PTH5_IN_PD, PTH1_IN_PD, PTH0_IN_PD,
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PTK6_IN_PD, PTK5_IN_PD, PTK4_IN_PD, PTK3_IN_PD, PTK2_IN_PD, PTK0_IN_PD,
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PTL7_IN_PD, PTL6_IN_PD, PTL5_IN_PD, PTL4_IN_PD,
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PTL3_IN_PD, PTL2_IN_PD, PTL1_IN_PD, PTL0_IN_PD,
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PTM7_IN_PD, PTM6_IN_PD, PTM5_IN_PD, PTM4_IN_PD,
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PTM3_IN_PD, PTM2_IN_PD, PTM1_IN_PD, PTM0_IN_PD,
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PTQ5_IN_PD, PTQ4_IN_PD, PTQ3_IN_PD, PTQ2_IN_PD,
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PTS4_IN_PD, PTS2_IN_PD, PTS1_IN_PD,
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PTT4_IN_PD, PTT3_IN_PD, PTT2_IN_PD, PTT1_IN_PD,
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PTU4_IN_PD, PTU3_IN_PD, PTU2_IN_PD, PTU1_IN_PD, PTU0_IN_PD,
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PTV4_IN_PD, PTV3_IN_PD, PTV2_IN_PD, PTV1_IN_PD, PTV0_IN_PD,
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PTW6_IN_PD, PTW4_IN_PD, PTW3_IN_PD, PTW2_IN_PD, PTW1_IN_PD, PTW0_IN_PD,
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PTX6_IN_PD, PTX5_IN_PD, PTX4_IN_PD,
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PTX3_IN_PD, PTX2_IN_PD, PTX1_IN_PD, PTX0_IN_PD,
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PINMUX_INPUT_PULLDOWN_END,
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PINMUX_INPUT_PULLUP_BEGIN,
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PTC7_IN_PU, PTC5_IN_PU,
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PTD7_IN_PU, PTD6_IN_PU, PTD5_IN_PU, PTD4_IN_PU,
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PTD3_IN_PU, PTD2_IN_PU, PTD1_IN_PU,
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PTJ1_IN_PU, PTJ0_IN_PU,
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PTQ0_IN_PU,
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PTR2_IN_PU,
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PTX6_IN_PU,
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PTY5_IN_PU, PTY4_IN_PU, PTY3_IN_PU, PTY2_IN_PU, PTY0_IN_PU,
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PTZ5_IN_PU, PTZ4_IN_PU, PTZ3_IN_PU, PTZ2_IN_PU, PTZ1_IN_PU,
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PINMUX_INPUT_PULLUP_END,
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PINMUX_OUTPUT_BEGIN,
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PTA7_OUT, PTA5_OUT,
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PTB7_OUT, PTB6_OUT, PTB5_OUT, PTB4_OUT,
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@ -298,14 +265,14 @@ enum {
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static const pinmux_enum_t pinmux_data[] = {
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/* PTA */
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PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_IN_PD, PTA7_OUT),
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PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_IN_PD),
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PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_IN_PD, PTA5_OUT),
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PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_IN_PD),
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PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_IN_PD),
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PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_IN_PD),
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PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_IN_PD),
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PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_IN_PD),
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PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT),
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PINMUX_DATA(PTA6_DATA, PTA6_IN),
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PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT),
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PINMUX_DATA(PTA4_DATA, PTA4_IN),
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PINMUX_DATA(PTA3_DATA, PTA3_IN),
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PINMUX_DATA(PTA2_DATA, PTA2_IN),
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PINMUX_DATA(PTA1_DATA, PTA1_IN),
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PINMUX_DATA(PTA0_DATA, PTA0_IN),
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/* PTB */
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PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT),
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@ -318,38 +285,38 @@ static const pinmux_enum_t pinmux_data[] = {
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PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT),
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/* PTC */
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PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_IN_PU),
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PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_IN_PU),
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PINMUX_DATA(PTC7_DATA, PTC7_IN),
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PINMUX_DATA(PTC5_DATA, PTC5_IN),
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PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT),
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PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT),
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PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT),
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PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT),
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/* PTD */
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PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_IN_PU),
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PINMUX_DATA(PTD6_DATA, PTD6_OUT, PTD6_IN, PTD6_IN_PU),
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PINMUX_DATA(PTD5_DATA, PTD5_OUT, PTD5_IN, PTD5_IN_PU),
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PINMUX_DATA(PTD4_DATA, PTD4_OUT, PTD4_IN, PTD4_IN_PU),
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PINMUX_DATA(PTD3_DATA, PTD3_OUT, PTD3_IN, PTD3_IN_PU),
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PINMUX_DATA(PTD2_DATA, PTD2_OUT, PTD2_IN, PTD2_IN_PU),
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PINMUX_DATA(PTD1_DATA, PTD1_OUT, PTD1_IN, PTD1_IN_PU),
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PINMUX_DATA(PTD7_DATA, PTD7_IN),
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PINMUX_DATA(PTD6_DATA, PTD6_OUT, PTD6_IN),
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PINMUX_DATA(PTD5_DATA, PTD5_OUT, PTD5_IN),
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PINMUX_DATA(PTD4_DATA, PTD4_OUT, PTD4_IN),
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PINMUX_DATA(PTD3_DATA, PTD3_OUT, PTD3_IN),
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PINMUX_DATA(PTD2_DATA, PTD2_OUT, PTD2_IN),
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PINMUX_DATA(PTD1_DATA, PTD1_OUT, PTD1_IN),
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PINMUX_DATA(PTD0_DATA, PTD0_OUT),
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/* PTE */
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PINMUX_DATA(PTE7_DATA, PTE7_OUT, PTE7_IN, PTE7_IN_PD),
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PINMUX_DATA(PTE6_DATA, PTE6_OUT, PTE6_IN, PTE6_IN_PD),
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PINMUX_DATA(PTE5_DATA, PTE5_OUT, PTE5_IN, PTE5_IN_PD),
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PINMUX_DATA(PTE4_DATA, PTE4_OUT, PTE4_IN, PTE4_IN_PD),
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PINMUX_DATA(PTE1_DATA, PTE1_OUT, PTE1_IN, PTE1_IN_PD),
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PINMUX_DATA(PTE0_DATA, PTE0_OUT, PTE0_IN, PTE0_IN_PD),
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PINMUX_DATA(PTE7_DATA, PTE7_OUT, PTE7_IN),
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PINMUX_DATA(PTE6_DATA, PTE6_OUT, PTE6_IN),
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PINMUX_DATA(PTE5_DATA, PTE5_OUT, PTE5_IN),
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PINMUX_DATA(PTE4_DATA, PTE4_OUT, PTE4_IN),
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PINMUX_DATA(PTE1_DATA, PTE1_OUT, PTE1_IN),
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PINMUX_DATA(PTE0_DATA, PTE0_OUT, PTE0_IN),
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/* PTF */
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PINMUX_DATA(PTF6_DATA, PTF6_OUT, PTF6_IN, PTF6_IN_PD),
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PINMUX_DATA(PTF5_DATA, PTF5_OUT, PTF5_IN, PTF5_IN_PD),
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PINMUX_DATA(PTF4_DATA, PTF4_OUT, PTF4_IN, PTF4_IN_PD),
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PINMUX_DATA(PTF3_DATA, PTF3_OUT, PTF3_IN, PTF3_IN_PD),
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PINMUX_DATA(PTF2_DATA, PTF2_OUT, PTF2_IN, PTF2_IN_PD),
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PINMUX_DATA(PTF1_DATA, PTF1_IN, PTF1_IN_PD),
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PINMUX_DATA(PTF6_DATA, PTF6_OUT, PTF6_IN),
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PINMUX_DATA(PTF5_DATA, PTF5_OUT, PTF5_IN),
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PINMUX_DATA(PTF4_DATA, PTF4_OUT, PTF4_IN),
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PINMUX_DATA(PTF3_DATA, PTF3_OUT, PTF3_IN),
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PINMUX_DATA(PTF2_DATA, PTF2_OUT, PTF2_IN),
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PINMUX_DATA(PTF1_DATA, PTF1_IN),
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PINMUX_DATA(PTF0_DATA, PTF0_OUT),
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/* PTG */
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@ -361,49 +328,49 @@ static const pinmux_enum_t pinmux_data[] = {
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/* PTH */
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PINMUX_DATA(PTH7_DATA, PTH7_OUT),
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PINMUX_DATA(PTH6_DATA, PTH6_OUT, PTH6_IN, PTH6_IN_PD),
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PINMUX_DATA(PTH5_DATA, PTH5_OUT, PTH5_IN, PTH5_IN_PD),
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PINMUX_DATA(PTH6_DATA, PTH6_OUT, PTH6_IN),
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PINMUX_DATA(PTH5_DATA, PTH5_OUT, PTH5_IN),
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PINMUX_DATA(PTH4_DATA, PTH4_OUT),
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PINMUX_DATA(PTH3_DATA, PTH3_OUT),
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PINMUX_DATA(PTH2_DATA, PTH2_OUT),
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PINMUX_DATA(PTH1_DATA, PTH1_OUT, PTH1_IN, PTH1_IN_PD),
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PINMUX_DATA(PTH0_DATA, PTH0_OUT, PTH0_IN, PTH0_IN_PD),
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PINMUX_DATA(PTH1_DATA, PTH1_OUT, PTH1_IN),
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PINMUX_DATA(PTH0_DATA, PTH0_OUT, PTH0_IN),
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/* PTJ */
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PINMUX_DATA(PTJ7_DATA, PTJ7_OUT),
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PINMUX_DATA(PTJ6_DATA, PTJ6_OUT),
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PINMUX_DATA(PTJ5_DATA, PTJ5_OUT),
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PINMUX_DATA(PTJ1_DATA, PTJ1_OUT, PTJ1_IN, PTJ1_IN_PU),
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PINMUX_DATA(PTJ0_DATA, PTJ0_OUT, PTJ0_IN, PTJ0_IN_PU),
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PINMUX_DATA(PTJ1_DATA, PTJ1_OUT, PTJ1_IN),
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PINMUX_DATA(PTJ0_DATA, PTJ0_OUT, PTJ0_IN),
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/* PTK */
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PINMUX_DATA(PTK6_DATA, PTK6_OUT, PTK6_IN, PTK6_IN_PD),
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PINMUX_DATA(PTK5_DATA, PTK5_OUT, PTK5_IN, PTK5_IN_PD),
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PINMUX_DATA(PTK4_DATA, PTK4_OUT, PTK4_IN, PTK4_IN_PD),
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PINMUX_DATA(PTK3_DATA, PTK3_OUT, PTK3_IN, PTK3_IN_PD),
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PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_IN_PD),
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PINMUX_DATA(PTK6_DATA, PTK6_OUT, PTK6_IN),
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PINMUX_DATA(PTK5_DATA, PTK5_OUT, PTK5_IN),
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PINMUX_DATA(PTK4_DATA, PTK4_OUT, PTK4_IN),
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PINMUX_DATA(PTK3_DATA, PTK3_OUT, PTK3_IN),
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PINMUX_DATA(PTK2_DATA, PTK2_IN),
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PINMUX_DATA(PTK1_DATA, PTK1_OUT),
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PINMUX_DATA(PTK0_DATA, PTK0_OUT, PTK0_IN, PTK0_IN_PD),
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PINMUX_DATA(PTK0_DATA, PTK0_OUT, PTK0_IN),
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/* PTL */
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PINMUX_DATA(PTL7_DATA, PTL7_OUT, PTL7_IN, PTL7_IN_PD),
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PINMUX_DATA(PTL6_DATA, PTL6_OUT, PTL6_IN, PTL6_IN_PD),
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PINMUX_DATA(PTL5_DATA, PTL5_OUT, PTL5_IN, PTL5_IN_PD),
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PINMUX_DATA(PTL4_DATA, PTL4_OUT, PTL4_IN, PTL4_IN_PD),
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PINMUX_DATA(PTL3_DATA, PTL3_OUT, PTL3_IN, PTL3_IN_PD),
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PINMUX_DATA(PTL2_DATA, PTL2_OUT, PTL2_IN, PTL2_IN_PD),
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PINMUX_DATA(PTL1_DATA, PTL1_OUT, PTL1_IN, PTL1_IN_PD),
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PINMUX_DATA(PTL0_DATA, PTL0_OUT, PTL0_IN, PTL0_IN_PD),
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PINMUX_DATA(PTL7_DATA, PTL7_OUT, PTL7_IN),
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PINMUX_DATA(PTL6_DATA, PTL6_OUT, PTL6_IN),
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PINMUX_DATA(PTL5_DATA, PTL5_OUT, PTL5_IN),
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PINMUX_DATA(PTL4_DATA, PTL4_OUT, PTL4_IN),
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PINMUX_DATA(PTL3_DATA, PTL3_OUT, PTL3_IN),
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PINMUX_DATA(PTL2_DATA, PTL2_OUT, PTL2_IN),
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PINMUX_DATA(PTL1_DATA, PTL1_OUT, PTL1_IN),
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PINMUX_DATA(PTL0_DATA, PTL0_OUT, PTL0_IN),
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/* PTM */
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PINMUX_DATA(PTM7_DATA, PTM7_OUT, PTM7_IN, PTM7_IN_PD),
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PINMUX_DATA(PTM6_DATA, PTM6_OUT, PTM6_IN, PTM6_IN_PD),
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PINMUX_DATA(PTM5_DATA, PTM5_OUT, PTM5_IN, PTM5_IN_PD),
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PINMUX_DATA(PTM4_DATA, PTM4_OUT, PTM4_IN, PTM4_IN_PD),
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PINMUX_DATA(PTM3_DATA, PTM3_OUT, PTM3_IN, PTM3_IN_PD),
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PINMUX_DATA(PTM2_DATA, PTM2_OUT, PTM2_IN, PTM2_IN_PD),
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PINMUX_DATA(PTM1_DATA, PTM1_OUT, PTM1_IN, PTM1_IN_PD),
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PINMUX_DATA(PTM0_DATA, PTM0_OUT, PTM0_IN, PTM0_IN_PD),
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PINMUX_DATA(PTM7_DATA, PTM7_OUT, PTM7_IN),
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PINMUX_DATA(PTM6_DATA, PTM6_OUT, PTM6_IN),
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PINMUX_DATA(PTM5_DATA, PTM5_OUT, PTM5_IN),
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PINMUX_DATA(PTM4_DATA, PTM4_OUT, PTM4_IN),
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PINMUX_DATA(PTM3_DATA, PTM3_OUT, PTM3_IN),
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PINMUX_DATA(PTM2_DATA, PTM2_OUT, PTM2_IN),
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PINMUX_DATA(PTM1_DATA, PTM1_OUT, PTM1_IN),
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PINMUX_DATA(PTM0_DATA, PTM0_OUT, PTM0_IN),
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/* PTN */
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PINMUX_DATA(PTN7_DATA, PTN7_OUT, PTN7_IN),
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@ -417,80 +384,80 @@ static const pinmux_enum_t pinmux_data[] = {
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/* PTQ */
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PINMUX_DATA(PTQ6_DATA, PTQ6_OUT),
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PINMUX_DATA(PTQ5_DATA, PTQ5_OUT, PTQ5_IN, PTQ5_IN_PD),
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PINMUX_DATA(PTQ4_DATA, PTQ4_OUT, PTQ4_IN, PTQ4_IN_PD),
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PINMUX_DATA(PTQ3_DATA, PTQ3_OUT, PTQ3_IN, PTQ3_IN_PD),
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PINMUX_DATA(PTQ2_DATA, PTQ2_IN, PTQ2_IN_PD),
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PINMUX_DATA(PTQ5_DATA, PTQ5_OUT, PTQ5_IN),
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PINMUX_DATA(PTQ4_DATA, PTQ4_OUT, PTQ4_IN),
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PINMUX_DATA(PTQ3_DATA, PTQ3_OUT, PTQ3_IN),
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PINMUX_DATA(PTQ2_DATA, PTQ2_IN),
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PINMUX_DATA(PTQ1_DATA, PTQ1_OUT),
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PINMUX_DATA(PTQ0_DATA, PTQ0_OUT, PTQ0_IN, PTQ0_IN_PU),
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PINMUX_DATA(PTQ0_DATA, PTQ0_OUT, PTQ0_IN),
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/* PTR */
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PINMUX_DATA(PTR4_DATA, PTR4_OUT),
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PINMUX_DATA(PTR3_DATA, PTR3_OUT),
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PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_IN_PU),
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PINMUX_DATA(PTR2_DATA, PTR2_IN),
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PINMUX_DATA(PTR1_DATA, PTR1_OUT),
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PINMUX_DATA(PTR0_DATA, PTR0_OUT),
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/* PTS */
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PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_IN_PD),
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PINMUX_DATA(PTS4_DATA, PTS4_IN),
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PINMUX_DATA(PTS3_DATA, PTS3_OUT),
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PINMUX_DATA(PTS2_DATA, PTS2_OUT, PTS2_IN, PTS2_IN_PD),
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PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_IN_PD),
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PINMUX_DATA(PTS2_DATA, PTS2_OUT, PTS2_IN),
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PINMUX_DATA(PTS1_DATA, PTS1_IN),
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PINMUX_DATA(PTS0_DATA, PTS0_OUT),
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/* PTT */
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PINMUX_DATA(PTT4_DATA, PTT4_OUT, PTT4_IN, PTT4_IN_PD),
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PINMUX_DATA(PTT3_DATA, PTT3_OUT, PTT3_IN, PTT3_IN_PD),
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PINMUX_DATA(PTT2_DATA, PTT2_OUT, PTT2_IN, PTT2_IN_PD),
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PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_IN_PD),
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PINMUX_DATA(PTT4_DATA, PTT4_OUT, PTT4_IN),
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PINMUX_DATA(PTT3_DATA, PTT3_OUT, PTT3_IN),
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PINMUX_DATA(PTT2_DATA, PTT2_OUT, PTT2_IN),
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PINMUX_DATA(PTT1_DATA, PTT1_IN),
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PINMUX_DATA(PTT0_DATA, PTT0_OUT),
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/* PTU */
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PINMUX_DATA(PTU4_DATA, PTU4_OUT, PTU4_IN, PTU4_IN_PD),
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PINMUX_DATA(PTU3_DATA, PTU3_OUT, PTU3_IN, PTU3_IN_PD),
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PINMUX_DATA(PTU2_DATA, PTU2_OUT, PTU2_IN, PTU2_IN_PD),
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PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_IN_PD),
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PINMUX_DATA(PTU0_DATA, PTU0_OUT, PTU0_IN, PTU0_IN_PD),
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PINMUX_DATA(PTU4_DATA, PTU4_OUT, PTU4_IN),
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PINMUX_DATA(PTU3_DATA, PTU3_OUT, PTU3_IN),
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PINMUX_DATA(PTU2_DATA, PTU2_OUT, PTU2_IN),
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PINMUX_DATA(PTU1_DATA, PTU1_IN),
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PINMUX_DATA(PTU0_DATA, PTU0_OUT, PTU0_IN),
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/* PTV */
|
||||
PINMUX_DATA(PTV4_DATA, PTV4_OUT, PTV4_IN, PTV4_IN_PD),
|
||||
PINMUX_DATA(PTV3_DATA, PTV3_OUT, PTV3_IN, PTV3_IN_PD),
|
||||
PINMUX_DATA(PTV2_DATA, PTV2_OUT, PTV2_IN, PTV2_IN_PD),
|
||||
PINMUX_DATA(PTV1_DATA, PTV1_OUT, PTV1_IN, PTV1_IN_PD),
|
||||
PINMUX_DATA(PTV0_DATA, PTV0_OUT, PTV0_IN, PTV0_IN_PD),
|
||||
PINMUX_DATA(PTV4_DATA, PTV4_OUT, PTV4_IN),
|
||||
PINMUX_DATA(PTV3_DATA, PTV3_OUT, PTV3_IN),
|
||||
PINMUX_DATA(PTV2_DATA, PTV2_OUT, PTV2_IN),
|
||||
PINMUX_DATA(PTV1_DATA, PTV1_OUT, PTV1_IN),
|
||||
PINMUX_DATA(PTV0_DATA, PTV0_OUT, PTV0_IN),
|
||||
|
||||
/* PTW */
|
||||
PINMUX_DATA(PTW6_DATA, PTW6_IN, PTW6_IN_PD),
|
||||
PINMUX_DATA(PTW6_DATA, PTW6_IN),
|
||||
PINMUX_DATA(PTW5_DATA, PTW5_OUT),
|
||||
PINMUX_DATA(PTW4_DATA, PTW4_OUT, PTW4_IN, PTW4_IN_PD),
|
||||
PINMUX_DATA(PTW3_DATA, PTW3_OUT, PTW3_IN, PTW3_IN_PD),
|
||||
PINMUX_DATA(PTW2_DATA, PTW2_OUT, PTW2_IN, PTW2_IN_PD),
|
||||
PINMUX_DATA(PTW1_DATA, PTW1_OUT, PTW1_IN, PTW1_IN_PD),
|
||||
PINMUX_DATA(PTW0_DATA, PTW0_OUT, PTW0_IN, PTW0_IN_PD),
|
||||
PINMUX_DATA(PTW4_DATA, PTW4_OUT, PTW4_IN),
|
||||
PINMUX_DATA(PTW3_DATA, PTW3_OUT, PTW3_IN),
|
||||
PINMUX_DATA(PTW2_DATA, PTW2_OUT, PTW2_IN),
|
||||
PINMUX_DATA(PTW1_DATA, PTW1_OUT, PTW1_IN),
|
||||
PINMUX_DATA(PTW0_DATA, PTW0_OUT, PTW0_IN),
|
||||
|
||||
/* PTX */
|
||||
PINMUX_DATA(PTX6_DATA, PTX6_OUT, PTX6_IN, PTX6_IN_PD),
|
||||
PINMUX_DATA(PTX5_DATA, PTX5_OUT, PTX5_IN, PTX5_IN_PD),
|
||||
PINMUX_DATA(PTX4_DATA, PTX4_OUT, PTX4_IN, PTX4_IN_PD),
|
||||
PINMUX_DATA(PTX3_DATA, PTX3_OUT, PTX3_IN, PTX3_IN_PD),
|
||||
PINMUX_DATA(PTX2_DATA, PTX2_OUT, PTX2_IN, PTX2_IN_PD),
|
||||
PINMUX_DATA(PTX1_DATA, PTX1_OUT, PTX1_IN, PTX1_IN_PD),
|
||||
PINMUX_DATA(PTX0_DATA, PTX0_OUT, PTX0_IN, PTX0_IN_PD),
|
||||
PINMUX_DATA(PTX6_DATA, PTX6_OUT, PTX6_IN),
|
||||
PINMUX_DATA(PTX5_DATA, PTX5_OUT, PTX5_IN),
|
||||
PINMUX_DATA(PTX4_DATA, PTX4_OUT, PTX4_IN),
|
||||
PINMUX_DATA(PTX3_DATA, PTX3_OUT, PTX3_IN),
|
||||
PINMUX_DATA(PTX2_DATA, PTX2_OUT, PTX2_IN),
|
||||
PINMUX_DATA(PTX1_DATA, PTX1_OUT, PTX1_IN),
|
||||
PINMUX_DATA(PTX0_DATA, PTX0_OUT, PTX0_IN),
|
||||
|
||||
/* PTY */
|
||||
PINMUX_DATA(PTY5_DATA, PTY5_OUT, PTY5_IN, PTY5_IN_PU),
|
||||
PINMUX_DATA(PTY4_DATA, PTY4_OUT, PTY4_IN, PTY4_IN_PU),
|
||||
PINMUX_DATA(PTY3_DATA, PTY3_OUT, PTY3_IN, PTY3_IN_PU),
|
||||
PINMUX_DATA(PTY2_DATA, PTY2_OUT, PTY2_IN, PTY2_IN_PU),
|
||||
PINMUX_DATA(PTY5_DATA, PTY5_OUT, PTY5_IN),
|
||||
PINMUX_DATA(PTY4_DATA, PTY4_OUT, PTY4_IN),
|
||||
PINMUX_DATA(PTY3_DATA, PTY3_OUT, PTY3_IN),
|
||||
PINMUX_DATA(PTY2_DATA, PTY2_OUT, PTY2_IN),
|
||||
PINMUX_DATA(PTY1_DATA, PTY1_OUT),
|
||||
PINMUX_DATA(PTY0_DATA, PTY0_OUT, PTY0_IN, PTY0_IN_PU),
|
||||
PINMUX_DATA(PTY0_DATA, PTY0_OUT, PTY0_IN),
|
||||
|
||||
/* PTZ */
|
||||
PINMUX_DATA(PTZ5_DATA, PTZ5_IN, PTZ5_IN_PU),
|
||||
PINMUX_DATA(PTZ4_DATA, PTZ4_IN, PTZ4_IN_PU),
|
||||
PINMUX_DATA(PTZ3_DATA, PTZ3_IN, PTZ3_IN_PU),
|
||||
PINMUX_DATA(PTZ2_DATA, PTZ2_IN, PTZ2_IN_PU),
|
||||
PINMUX_DATA(PTZ1_DATA, PTZ1_IN, PTZ1_IN_PU),
|
||||
PINMUX_DATA(PTZ5_DATA, PTZ5_IN),
|
||||
PINMUX_DATA(PTZ4_DATA, PTZ4_IN),
|
||||
PINMUX_DATA(PTZ3_DATA, PTZ3_IN),
|
||||
PINMUX_DATA(PTZ2_DATA, PTZ2_IN),
|
||||
PINMUX_DATA(PTZ1_DATA, PTZ1_IN),
|
||||
|
||||
/* SCIF0 */
|
||||
PINMUX_DATA(SCIF0_TXD_MARK, SCIF0_TXD),
|
||||
|
|
@ -1270,14 +1237,14 @@ static const struct pinmux_func pinmux_func_gpios[] = {
|
|||
|
||||
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
{ PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
|
||||
VIO_D7_SCIF1_SCK, PTA7_OUT, PTA7_IN_PD, PTA7_IN,
|
||||
VIO_D6_SCIF1_RXD, 0, PTA6_IN_PD, PTA6_IN,
|
||||
VIO_D5_SCIF1_TXD, PTA5_OUT, PTA5_IN_PD, PTA5_IN,
|
||||
VIO_D4, 0, PTA4_IN_PD, PTA4_IN,
|
||||
VIO_D3, 0, PTA3_IN_PD, PTA3_IN,
|
||||
VIO_D2, 0, PTA2_IN_PD, PTA2_IN,
|
||||
VIO_D1, 0, PTA1_IN_PD, PTA1_IN,
|
||||
VIO_D0_LCDLCLK, 0, PTA0_IN_PD, PTA0_IN }
|
||||
VIO_D7_SCIF1_SCK, PTA7_OUT, 0, PTA7_IN,
|
||||
VIO_D6_SCIF1_RXD, 0, 0, PTA6_IN,
|
||||
VIO_D5_SCIF1_TXD, PTA5_OUT, 0, PTA5_IN,
|
||||
VIO_D4, 0, 0, PTA4_IN,
|
||||
VIO_D3, 0, 0, PTA3_IN,
|
||||
VIO_D2, 0, 0, PTA2_IN,
|
||||
VIO_D1, 0, 0, PTA1_IN,
|
||||
VIO_D0_LCDLCLK, 0, 0, PTA0_IN }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) {
|
||||
HPD55, PTB7_OUT, 0, PTB7_IN,
|
||||
|
|
@ -1290,9 +1257,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
HPD48, PTB0_OUT, 0, PTB0_IN }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) {
|
||||
0, 0, PTC7_IN_PU, PTC7_IN,
|
||||
0, 0, 0, PTC7_IN,
|
||||
0, 0, 0, 0,
|
||||
IOIS16, 0, PTC5_IN_PU, PTC5_IN,
|
||||
IOIS16, 0, 0, PTC5_IN,
|
||||
HPDQM7, PTC4_OUT, 0, PTC4_IN,
|
||||
HPDQM6, PTC3_OUT, 0, PTC3_IN,
|
||||
HPDQM5, PTC2_OUT, 0, PTC2_IN,
|
||||
|
|
@ -1300,33 +1267,33 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
HPDQM4, PTC0_OUT, 0, PTC0_IN }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) {
|
||||
SDHICD, 0, PTD7_IN_PU, PTD7_IN,
|
||||
SDHIWP, PTD6_OUT, PTD6_IN_PU, PTD6_IN,
|
||||
SDHID3, PTD5_OUT, PTD5_IN_PU, PTD5_IN,
|
||||
IRQ2_SDHID2, PTD4_OUT, PTD4_IN_PU, PTD4_IN,
|
||||
SDHID1, PTD3_OUT, PTD3_IN_PU, PTD3_IN,
|
||||
SDHID0, PTD2_OUT, PTD2_IN_PU, PTD2_IN,
|
||||
SDHICMD, PTD1_OUT, PTD1_IN_PU, PTD1_IN,
|
||||
SDHICD, 0, 0, PTD7_IN,
|
||||
SDHIWP, PTD6_OUT, 0, PTD6_IN,
|
||||
SDHID3, PTD5_OUT, 0, PTD5_IN,
|
||||
IRQ2_SDHID2, PTD4_OUT, 0, PTD4_IN,
|
||||
SDHID1, PTD3_OUT, 0, PTD3_IN,
|
||||
SDHID0, PTD2_OUT, 0, PTD2_IN,
|
||||
SDHICMD, PTD1_OUT, 0, PTD1_IN,
|
||||
SDHICLK, PTD0_OUT, 0, 0 }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) {
|
||||
A25, PTE7_OUT, PTE7_IN_PD, PTE7_IN,
|
||||
A24, PTE6_OUT, PTE6_IN_PD, PTE6_IN,
|
||||
A23, PTE5_OUT, PTE5_IN_PD, PTE5_IN,
|
||||
A22, PTE4_OUT, PTE4_IN_PD, PTE4_IN,
|
||||
A25, PTE7_OUT, 0, PTE7_IN,
|
||||
A24, PTE6_OUT, 0, PTE6_IN,
|
||||
A23, PTE5_OUT, 0, PTE5_IN,
|
||||
A22, PTE4_OUT, 0, PTE4_IN,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
IRQ5, PTE1_OUT, PTE1_IN_PD, PTE1_IN,
|
||||
IRQ4_BS, PTE0_OUT, PTE0_IN_PD, PTE0_IN }
|
||||
IRQ5, PTE1_OUT, 0, PTE1_IN,
|
||||
IRQ4_BS, PTE0_OUT, 0, PTE0_IN }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) {
|
||||
0, 0, 0, 0,
|
||||
PTF6, PTF6_OUT, PTF6_IN_PD, PTF6_IN,
|
||||
SIOSCK_SIUBOBT, PTF5_OUT, PTF5_IN_PD, PTF5_IN,
|
||||
SIOSTRB1_SIUBOLR, PTF4_OUT, PTF4_IN_PD, PTF4_IN,
|
||||
SIOSTRB0_SIUBIBT, PTF3_OUT, PTF3_IN_PD, PTF3_IN,
|
||||
SIOD_SIUBILR, PTF2_OUT, PTF2_IN_PD, PTF2_IN,
|
||||
SIORXD_SIUBISLD, 0, PTF1_IN_PD, PTF1_IN,
|
||||
PTF6, PTF6_OUT, 0, PTF6_IN,
|
||||
SIOSCK_SIUBOBT, PTF5_OUT, 0, PTF5_IN,
|
||||
SIOSTRB1_SIUBOLR, PTF4_OUT, 0, PTF4_IN,
|
||||
SIOSTRB0_SIUBIBT, PTF3_OUT, 0, PTF3_IN,
|
||||
SIOD_SIUBILR, PTF2_OUT, 0, PTF2_IN,
|
||||
SIORXD_SIUBISLD, 0, 0, PTF1_IN,
|
||||
SIOTXD_SIUBOSLD, PTF0_OUT, 0, 0 }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) {
|
||||
|
|
@ -1341,13 +1308,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
},
|
||||
{ PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) {
|
||||
LCDVCPWC_LCDVCPWC2, PTH7_OUT, 0, 0,
|
||||
LCDVSYN2_DACK, PTH6_OUT, PTH6_IN_PD, PTH6_IN,
|
||||
LCDVSYN, PTH5_OUT, PTH5_IN_PD, PTH5_IN,
|
||||
LCDVSYN2_DACK, PTH6_OUT, 0, PTH6_IN,
|
||||
LCDVSYN, PTH5_OUT, 0, PTH5_IN,
|
||||
LCDDISP_LCDRS, PTH4_OUT, 0, 0,
|
||||
LCDHSYN_LCDCS, PTH3_OUT, 0, 0,
|
||||
LCDDON_LCDDON2, PTH2_OUT, 0, 0,
|
||||
LCDD17_DV_HSYNC, PTH1_OUT, PTH1_IN_PD, PTH1_IN,
|
||||
LCDD16_DV_VSYNC, PTH0_OUT, PTH0_IN_PD, PTH0_IN }
|
||||
LCDD17_DV_HSYNC, PTH1_OUT, 0, PTH1_IN,
|
||||
LCDD16_DV_VSYNC, PTH0_OUT, 0, PTH0_IN }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) {
|
||||
STATUS0, PTJ7_OUT, 0, 0,
|
||||
|
|
@ -1356,38 +1323,38 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
IRQ1, PTJ1_OUT, PTJ1_IN_PU, PTJ1_IN,
|
||||
IRQ0, PTJ0_OUT, PTJ0_IN_PU, PTJ0_IN }
|
||||
IRQ1, PTJ1_OUT, 0, PTJ1_IN,
|
||||
IRQ0, PTJ0_OUT, 0, PTJ0_IN }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) {
|
||||
0, 0, 0, 0,
|
||||
SIUAILR_SIOF1_SS2, PTK6_OUT, PTK6_IN_PD, PTK6_IN,
|
||||
SIUAIBT_SIOF1_SS1, PTK5_OUT, PTK5_IN_PD, PTK5_IN,
|
||||
SIUAOLR_SIOF1_SYNC, PTK4_OUT, PTK4_IN_PD, PTK4_IN,
|
||||
SIUAOBT_SIOF1_SCK, PTK3_OUT, PTK3_IN_PD, PTK3_IN,
|
||||
SIUAISLD_SIOF1_RXD, 0, PTK2_IN_PD, PTK2_IN,
|
||||
SIUAILR_SIOF1_SS2, PTK6_OUT, 0, PTK6_IN,
|
||||
SIUAIBT_SIOF1_SS1, PTK5_OUT, 0, PTK5_IN,
|
||||
SIUAOLR_SIOF1_SYNC, PTK4_OUT, 0, PTK4_IN,
|
||||
SIUAOBT_SIOF1_SCK, PTK3_OUT, 0, PTK3_IN,
|
||||
SIUAISLD_SIOF1_RXD, 0, 0, PTK2_IN,
|
||||
SIUAOSLD_SIOF1_TXD, PTK1_OUT, 0, 0,
|
||||
PTK0, PTK0_OUT, PTK0_IN_PD, PTK0_IN }
|
||||
PTK0, PTK0_OUT, 0, PTK0_IN }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) {
|
||||
LCDD15_DV_D15, PTL7_OUT, PTL7_IN_PD, PTL7_IN,
|
||||
LCDD14_DV_D14, PTL6_OUT, PTL6_IN_PD, PTL6_IN,
|
||||
LCDD13_DV_D13, PTL5_OUT, PTL5_IN_PD, PTL5_IN,
|
||||
LCDD12_DV_D12, PTL4_OUT, PTL4_IN_PD, PTL4_IN,
|
||||
LCDD11_DV_D11, PTL3_OUT, PTL3_IN_PD, PTL3_IN,
|
||||
LCDD10_DV_D10, PTL2_OUT, PTL2_IN_PD, PTL2_IN,
|
||||
LCDD9_DV_D9, PTL1_OUT, PTL1_IN_PD, PTL1_IN,
|
||||
LCDD8_DV_D8, PTL0_OUT, PTL0_IN_PD, PTL0_IN }
|
||||
LCDD15_DV_D15, PTL7_OUT, 0, PTL7_IN,
|
||||
LCDD14_DV_D14, PTL6_OUT, 0, PTL6_IN,
|
||||
LCDD13_DV_D13, PTL5_OUT, 0, PTL5_IN,
|
||||
LCDD12_DV_D12, PTL4_OUT, 0, PTL4_IN,
|
||||
LCDD11_DV_D11, PTL3_OUT, 0, PTL3_IN,
|
||||
LCDD10_DV_D10, PTL2_OUT, 0, PTL2_IN,
|
||||
LCDD9_DV_D9, PTL1_OUT, 0, PTL1_IN,
|
||||
LCDD8_DV_D8, PTL0_OUT, 0, PTL0_IN }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) {
|
||||
LCDD7_DV_D7, PTM7_OUT, PTM7_IN_PD, PTM7_IN,
|
||||
LCDD6_DV_D6, PTM6_OUT, PTM6_IN_PD, PTM6_IN,
|
||||
LCDD5_DV_D5, PTM5_OUT, PTM5_IN_PD, PTM5_IN,
|
||||
LCDD4_DV_D4, PTM4_OUT, PTM4_IN_PD, PTM4_IN,
|
||||
LCDD3_DV_D3, PTM3_OUT, PTM3_IN_PD, PTM3_IN,
|
||||
LCDD2_DV_D2, PTM2_OUT, PTM2_IN_PD, PTM2_IN,
|
||||
LCDD1_DV_D1, PTM1_OUT, PTM1_IN_PD, PTM1_IN,
|
||||
LCDD0_DV_D0, PTM0_OUT, PTM0_IN_PD, PTM0_IN }
|
||||
LCDD7_DV_D7, PTM7_OUT, 0, PTM7_IN,
|
||||
LCDD6_DV_D6, PTM6_OUT, 0, PTM6_IN,
|
||||
LCDD5_DV_D5, PTM5_OUT, 0, PTM5_IN,
|
||||
LCDD4_DV_D4, PTM4_OUT, 0, PTM4_IN,
|
||||
LCDD3_DV_D3, PTM3_OUT, 0, PTM3_IN,
|
||||
LCDD2_DV_D2, PTM2_OUT, 0, PTM2_IN,
|
||||
LCDD1_DV_D1, PTM1_OUT, 0, PTM1_IN,
|
||||
LCDD0_DV_D0, PTM0_OUT, 0, PTM0_IN }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2) {
|
||||
HPD63, PTN7_OUT, 0, PTN7_IN,
|
||||
|
|
@ -1402,12 +1369,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
{ PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2) {
|
||||
0, 0, 0, 0,
|
||||
SIOF0_SS2_SIM_RST, PTQ6_OUT, 0, 0,
|
||||
SIOF0_SS1_TS_SPSYNC, PTQ5_OUT, PTQ5_IN_PD, PTQ5_IN,
|
||||
SIOF0_SYNC_TS_SDEN, PTQ4_OUT, PTQ4_IN_PD, PTQ4_IN,
|
||||
SIOF0_SCK_TS_SCK, PTQ3_OUT, PTQ3_IN_PD, PTQ3_IN,
|
||||
PTQ2, 0, PTQ2_IN_PD, PTQ2_IN,
|
||||
SIOF0_SS1_TS_SPSYNC, PTQ5_OUT, 0, PTQ5_IN,
|
||||
SIOF0_SYNC_TS_SDEN, PTQ4_OUT, 0, PTQ4_IN,
|
||||
SIOF0_SCK_TS_SCK, PTQ3_OUT, 0, PTQ3_IN,
|
||||
PTQ2, 0, 0, PTQ2_IN,
|
||||
PTQ1, PTQ1_OUT, 0, 0,
|
||||
PTQ0, PTQ0_OUT, PTQ0_IN_PU, PTQ0_IN }
|
||||
PTQ0, PTQ0_OUT, 0, PTQ0_IN }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2) {
|
||||
0, 0, 0, 0,
|
||||
|
|
@ -1415,7 +1382,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
0, 0, 0, 0,
|
||||
LCDRD, PTR4_OUT, 0, 0,
|
||||
CS6B_CE1B_LCDCS2, PTR3_OUT, 0, 0,
|
||||
WAIT, 0, PTR2_IN_PU, PTR2_IN,
|
||||
WAIT, 0, 0, PTR2_IN,
|
||||
LCDDCK_LCDWR, PTR1_OUT, 0, 0,
|
||||
LCDVEPWC_LCDVEPWC2, PTR0_OUT, 0, 0 }
|
||||
},
|
||||
|
|
@ -1423,80 +1390,80 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
SCIF0_CTS_SIUAISPD, 0, PTS4_IN_PD, PTS4_IN,
|
||||
SCIF0_CTS_SIUAISPD, 0, 0, PTS4_IN,
|
||||
SCIF0_RTS_SIUAOSPD, PTS3_OUT, 0, 0,
|
||||
SCIF0_SCK_TPUTO, PTS2_OUT, PTS2_IN_PD, PTS2_IN,
|
||||
SCIF0_RXD, 0, PTS1_IN_PD, PTS1_IN,
|
||||
SCIF0_SCK_TPUTO, PTS2_OUT, 0, PTS2_IN,
|
||||
SCIF0_RXD, 0, 0, PTS1_IN,
|
||||
SCIF0_TXD, PTS0_OUT, 0, 0 }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2) {
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
FOE_VIO_VD2, PTT4_OUT, PTT4_IN_PD, PTT4_IN,
|
||||
FWE, PTT3_OUT, PTT3_IN_PD, PTT3_IN,
|
||||
FSC, PTT2_OUT, PTT2_IN_PD, PTT2_IN,
|
||||
DREQ0, 0, PTT1_IN_PD, PTT1_IN,
|
||||
FOE_VIO_VD2, PTT4_OUT, 0, PTT4_IN,
|
||||
FWE, PTT3_OUT, 0, PTT3_IN,
|
||||
FSC, PTT2_OUT, 0, PTT2_IN,
|
||||
DREQ0, 0, 0, PTT1_IN,
|
||||
FCDE, PTT0_OUT, 0, 0 }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2) {
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
NAF2_VIO_D10, PTU4_OUT, PTU4_IN_PD, PTU4_IN,
|
||||
NAF1_VIO_D9, PTU3_OUT, PTU3_IN_PD, PTU3_IN,
|
||||
NAF0_VIO_D8, PTU2_OUT, PTU2_IN_PD, PTU2_IN,
|
||||
FRB_VIO_CLK2, 0, PTU1_IN_PD, PTU1_IN,
|
||||
FCE_VIO_HD2, PTU0_OUT, PTU0_IN_PD, PTU0_IN }
|
||||
NAF2_VIO_D10, PTU4_OUT, 0, PTU4_IN,
|
||||
NAF1_VIO_D9, PTU3_OUT, 0, PTU3_IN,
|
||||
NAF0_VIO_D8, PTU2_OUT, 0, PTU2_IN,
|
||||
FRB_VIO_CLK2, 0, 0, PTU1_IN,
|
||||
FCE_VIO_HD2, PTU0_OUT, 0, PTU0_IN }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2) {
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
NAF7_VIO_D15, PTV4_OUT, PTV4_IN_PD, PTV4_IN,
|
||||
NAF6_VIO_D14, PTV3_OUT, PTV3_IN_PD, PTV3_IN,
|
||||
NAF5_VIO_D13, PTV2_OUT, PTV2_IN_PD, PTV2_IN,
|
||||
NAF4_VIO_D12, PTV1_OUT, PTV1_IN_PD, PTV1_IN,
|
||||
NAF3_VIO_D11, PTV0_OUT, PTV0_IN_PD, PTV0_IN }
|
||||
NAF7_VIO_D15, PTV4_OUT, 0, PTV4_IN,
|
||||
NAF6_VIO_D14, PTV3_OUT, 0, PTV3_IN,
|
||||
NAF5_VIO_D13, PTV2_OUT, 0, PTV2_IN,
|
||||
NAF4_VIO_D12, PTV1_OUT, 0, PTV1_IN,
|
||||
NAF3_VIO_D11, PTV0_OUT, 0, PTV0_IN }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2) {
|
||||
0, 0, 0, 0,
|
||||
VIO_FLD_SCIF2_CTS, 0, PTW6_IN_PD, PTW6_IN,
|
||||
VIO_FLD_SCIF2_CTS, 0, 0, PTW6_IN,
|
||||
VIO_CKO_SCIF2_RTS, PTW5_OUT, 0, 0,
|
||||
VIO_STEX_SCIF2_SCK, PTW4_OUT, PTW4_IN_PD, PTW4_IN,
|
||||
VIO_STEM_SCIF2_TXD, PTW3_OUT, PTW3_IN_PD, PTW3_IN,
|
||||
VIO_HD_SCIF2_RXD, PTW2_OUT, PTW2_IN_PD, PTW2_IN,
|
||||
VIO_VD_SCIF1_CTS, PTW1_OUT, PTW1_IN_PD, PTW1_IN,
|
||||
VIO_CLK_SCIF1_RTS, PTW0_OUT, PTW0_IN_PD, PTW0_IN }
|
||||
VIO_STEX_SCIF2_SCK, PTW4_OUT, 0, PTW4_IN,
|
||||
VIO_STEM_SCIF2_TXD, PTW3_OUT, 0, PTW3_IN,
|
||||
VIO_HD_SCIF2_RXD, PTW2_OUT, 0, PTW2_IN,
|
||||
VIO_VD_SCIF1_CTS, PTW1_OUT, 0, PTW1_IN,
|
||||
VIO_CLK_SCIF1_RTS, PTW0_OUT, 0, PTW0_IN }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2) {
|
||||
0, 0, 0, 0,
|
||||
CS6A_CE2B, PTX6_OUT, PTX6_IN_PU, PTX6_IN,
|
||||
LCDD23, PTX5_OUT, PTX5_IN_PD, PTX5_IN,
|
||||
LCDD22, PTX4_OUT, PTX4_IN_PD, PTX4_IN,
|
||||
LCDD21, PTX3_OUT, PTX3_IN_PD, PTX3_IN,
|
||||
LCDD20, PTX2_OUT, PTX2_IN_PD, PTX2_IN,
|
||||
LCDD19_DV_CLKI, PTX1_OUT, PTX1_IN_PD, PTX1_IN,
|
||||
LCDD18_DV_CLK, PTX0_OUT, PTX0_IN_PD, PTX0_IN }
|
||||
CS6A_CE2B, PTX6_OUT, 0, PTX6_IN,
|
||||
LCDD23, PTX5_OUT, 0, PTX5_IN,
|
||||
LCDD22, PTX4_OUT, 0, PTX4_IN,
|
||||
LCDD21, PTX3_OUT, 0, PTX3_IN,
|
||||
LCDD20, PTX2_OUT, 0, PTX2_IN,
|
||||
LCDD19_DV_CLKI, PTX1_OUT, 0, PTX1_IN,
|
||||
LCDD18_DV_CLK, PTX0_OUT, 0, PTX0_IN }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2) {
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
KEYOUT5_IN5, PTY5_OUT, PTY5_IN_PU, PTY5_IN,
|
||||
KEYOUT4_IN6, PTY4_OUT, PTY4_IN_PU, PTY4_IN,
|
||||
KEYOUT3, PTY3_OUT, PTY3_IN_PU, PTY3_IN,
|
||||
KEYOUT2, PTY2_OUT, PTY2_IN_PU, PTY2_IN,
|
||||
KEYOUT5_IN5, PTY5_OUT, 0, PTY5_IN,
|
||||
KEYOUT4_IN6, PTY4_OUT, 0, PTY4_IN,
|
||||
KEYOUT3, PTY3_OUT, 0, PTY3_IN,
|
||||
KEYOUT2, PTY2_OUT, 0, PTY2_IN,
|
||||
KEYOUT1, PTY1_OUT, 0, 0,
|
||||
KEYOUT0, PTY0_OUT, PTY0_IN_PU, PTY0_IN }
|
||||
KEYOUT0, PTY0_OUT, 0, PTY0_IN }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2) {
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
KEYIN4_IRQ7, 0, PTZ5_IN_PU, PTZ5_IN,
|
||||
KEYIN3, 0, PTZ4_IN_PU, PTZ4_IN,
|
||||
KEYIN2, 0, PTZ3_IN_PU, PTZ3_IN,
|
||||
KEYIN1, 0, PTZ2_IN_PU, PTZ2_IN,
|
||||
KEYIN0_IRQ6, 0, PTZ1_IN_PU, PTZ1_IN,
|
||||
KEYIN4_IRQ7, 0, 0, PTZ5_IN,
|
||||
KEYIN3, 0, 0, PTZ4_IN,
|
||||
KEYIN2, 0, 0, PTZ3_IN,
|
||||
KEYIN1, 0, 0, PTZ2_IN,
|
||||
KEYIN0_IRQ6, 0, 0, PTZ1_IN,
|
||||
0, 0, 0, 0 }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 1) {
|
||||
|
|
@ -1763,8 +1730,6 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
|
|||
const struct sh_pfc_soc_info sh7722_pinmux_info = {
|
||||
.name = "sh7722_pfc",
|
||||
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
|
||||
.input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
|
||||
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
|
||||
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue