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x86/bugs: Add AMD's SPEC_CTRL MSR usage
The AMD document outlining the SSBD handling 124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf mentions that if CPUID 8000_0008.EBX[24] is set we should be using the SPEC_CTRL MSR (0x48) over the VIRT SPEC_CTRL MSR (0xC001_011f) for speculative store bypass disable. This in effect means we should clear the X86_FEATURE_VIRT_SSBD flag so that we would prefer the SPEC_CTRL MSR. See the document titled: 124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf A copy of this document is available at https://bugzilla.kernel.org/show_bug.cgi?id=199889 Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com> Cc: kvm@vger.kernel.org Cc: KarimAllah Ahmed <karahmed@amazon.de> Cc: andrew.cooper3@citrix.com Cc: Joerg Roedel <joro@8bytes.org> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Borislav Petkov <bp@suse.de> Cc: David Woodhouse <dwmw@amazon.co.uk> Cc: Kees Cook <keescook@chromium.org> Link: https://lkml.kernel.org/r/20180601145921.9500-3-konrad.wilk@oracle.com
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2480986001
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arch/x86
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@ -282,6 +282,7 @@
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#define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier */
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#define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */
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#define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect Branch Predictors */
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#define X86_FEATURE_AMD_SSBD (13*32+24) /* "" Speculative Store Bypass Disable */
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#define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */
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#define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */
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@ -529,18 +529,20 @@ static enum ssb_mitigation __init __ssb_select_mitigation(void)
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if (mode == SPEC_STORE_BYPASS_DISABLE) {
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setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
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/*
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* Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD uses
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* a completely different MSR and bit dependent on family.
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* Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
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* use a completely different MSR and bit dependent on family.
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*/
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switch (boot_cpu_data.x86_vendor) {
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case X86_VENDOR_INTEL:
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case X86_VENDOR_AMD:
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if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
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x86_amd_ssb_disable();
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break;
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}
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x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
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x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
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wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
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break;
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case X86_VENDOR_AMD:
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x86_amd_ssb_disable();
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break;
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}
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}
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@ -803,6 +803,12 @@ static void init_speculation_control(struct cpuinfo_x86 *c)
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set_cpu_cap(c, X86_FEATURE_STIBP);
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set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
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}
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if (cpu_has(c, X86_FEATURE_AMD_SSBD)) {
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set_cpu_cap(c, X86_FEATURE_SSBD);
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set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
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clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD);
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}
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}
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void get_cpu_cap(struct cpuinfo_x86 *c)
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@ -379,7 +379,8 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
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/* cpuid 0x80000008.ebx */
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const u32 kvm_cpuid_8000_0008_ebx_x86_features =
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F(AMD_IBPB) | F(AMD_IBRS) | F(VIRT_SSBD) | F(AMD_SSB_NO);
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F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) |
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F(AMD_SSB_NO);
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/* cpuid 0xC0000001.edx */
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const u32 kvm_cpuid_C000_0001_edx_x86_features =
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@ -664,7 +665,12 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
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entry->ebx |= F(VIRT_SSBD);
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entry->ebx &= kvm_cpuid_8000_0008_ebx_x86_features;
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cpuid_mask(&entry->ebx, CPUID_8000_0008_EBX);
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if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
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/*
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* The preference is to use SPEC CTRL MSR instead of the
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* VIRT_SPEC MSR.
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*/
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if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
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!boot_cpu_has(X86_FEATURE_AMD_SSBD))
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entry->ebx |= F(VIRT_SSBD);
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break;
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}
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@ -4115,7 +4115,8 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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break;
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case MSR_IA32_SPEC_CTRL:
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if (!msr_info->host_initiated &&
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!guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS))
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!guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
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!guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
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return 1;
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msr_info->data = svm->spec_ctrl;
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@ -4217,11 +4218,12 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
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break;
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case MSR_IA32_SPEC_CTRL:
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if (!msr->host_initiated &&
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!guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS))
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!guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
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!guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
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return 1;
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/* The STIBP bit doesn't fault even if it's not advertised */
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if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP))
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if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
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return 1;
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svm->spec_ctrl = data;
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