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drm/sun4i: dotclock: Allow divider = 127 

The dot clock divider is 7 bits wide, and the divider range is 1 ~ 127,
or 6 ~ 127 if phase offsets are used. The 0 register value also
represents a divider of 1 or bypass.

Make the end condition of the for loop inclusive of 127 in the
round_rate callback.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit is contained in:
Chen-Yu Tsai 2016-09-15 23:14:01 +08:00 committed by Maxime Ripard
parent e996e2089f
commit 7e81bda23a
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/sun4i/sun4i_dotclock.c
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@ -77,7 +77,7 @@ static long sun4i_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
u8 best_div = 1;
int i;
for (i = 6; i < 127; i++) {
for (i = 6; i <= 127; i++) {
unsigned long ideal = rate * i;
unsigned long rounded;