mirror of https://gitee.com/openkylin/linux.git
drm/i915/dp: switch to kernel types
Mixed C99 and kernel types use is getting ugly. Prefer kernel types. sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g' Minor checkpatch/whitespace fixes sprinkled on top of the changed lines. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/3c030a12b4313eec512ce2b7a953cff439d8af67.1547629303.git.jani.nikula@intel.com
This commit is contained in:
Jani Nikula
parent
990290d124
commit
830de4220a
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@ -429,7 +429,7 @@ static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
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}
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static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
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uint8_t lane_count)
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u8 lane_count)
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{
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/*
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* FIXME: we need to synchronize the current link parameters with
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@ -449,7 +449,7 @@ static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
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static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
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int link_rate,
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uint8_t lane_count)
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u8 lane_count)
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{
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const struct drm_display_mode *fixed_mode =
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intel_dp->attached_connector->panel.fixed_mode;
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@ -464,7 +464,7 @@ static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
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}
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int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
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int link_rate, uint8_t lane_count)
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int link_rate, u8 lane_count)
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{
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int index;
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@ -572,19 +572,19 @@ intel_dp_mode_valid(struct drm_connector *connector,
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return MODE_OK;
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}
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uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
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u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
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{
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int i;
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uint32_t v = 0;
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int i;
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u32 v = 0;
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if (src_bytes > 4)
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src_bytes = 4;
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for (i = 0; i < src_bytes; i++)
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v |= ((uint32_t) src[i]) << ((3-i) * 8);
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v |= ((u32)src[i]) << ((3 - i) * 8);
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return v;
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}
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static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
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static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
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{
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int i;
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if (dst_bytes > 4)
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@ -643,7 +643,7 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
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bool pll_enabled, release_cl_override = false;
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enum dpio_phy phy = DPIO_PHY(pipe);
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enum dpio_channel ch = vlv_pipe_to_channel(pipe);
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uint32_t DP;
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u32 DP;
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if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
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"skipping pipe %c power sequencer kick due to port %c being active\n",
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@ -1051,12 +1051,12 @@ intel_dp_check_edp(struct intel_dp *intel_dp)
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}
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}
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static uint32_t
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static u32
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intel_dp_aux_wait_done(struct intel_dp *intel_dp)
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{
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struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
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i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
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uint32_t status;
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u32 status;
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bool done;
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#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
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@ -1069,7 +1069,7 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp)
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return status;
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}
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static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
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static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
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{
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struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
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@ -1083,7 +1083,7 @@ static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
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return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
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}
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static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
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static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
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{
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struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
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struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
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@ -1102,7 +1102,7 @@ static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
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return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
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}
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static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
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static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
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{
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struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
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struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
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@ -1119,7 +1119,7 @@ static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
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return ilk_get_aux_clock_divider(intel_dp, index);
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}
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static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
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static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
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{
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/*
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* SKL doesn't need us to program the AUX clock divider (Hardware will
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@ -1129,14 +1129,14 @@ static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
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return index ? 0 : 1;
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}
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static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
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int send_bytes,
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uint32_t aux_clock_divider)
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static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
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int send_bytes,
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u32 aux_clock_divider)
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{
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struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
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struct drm_i915_private *dev_priv =
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to_i915(intel_dig_port->base.base.dev);
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uint32_t precharge, timeout;
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u32 precharge, timeout;
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if (IS_GEN(dev_priv, 6))
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precharge = 3;
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@ -1159,12 +1159,12 @@ static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
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(aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
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}
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static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
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int send_bytes,
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uint32_t unused)
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static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
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int send_bytes,
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u32 unused)
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{
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struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
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uint32_t ret;
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u32 ret;
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ret = DP_AUX_CH_CTL_SEND_BUSY |
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DP_AUX_CH_CTL_DONE |
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@ -1184,19 +1184,19 @@ static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
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static int
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intel_dp_aux_xfer(struct intel_dp *intel_dp,
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const uint8_t *send, int send_bytes,
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uint8_t *recv, int recv_size,
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const u8 *send, int send_bytes,
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u8 *recv, int recv_size,
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u32 aux_send_ctl_flags)
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{
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struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
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struct drm_i915_private *dev_priv =
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to_i915(intel_dig_port->base.base.dev);
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i915_reg_t ch_ctl, ch_data[5];
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uint32_t aux_clock_divider;
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u32 aux_clock_divider;
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intel_wakeref_t wakeref;
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int i, ret, recv_bytes;
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int try, clock = 0;
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uint32_t status;
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u32 status;
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bool vdd;
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ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
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@ -1369,7 +1369,7 @@ static ssize_t
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intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
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{
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struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
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uint8_t txbuf[20], rxbuf[20];
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u8 txbuf[20], rxbuf[20];
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size_t txsize, rxsize;
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int ret;
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@ -1702,7 +1702,7 @@ int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
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}
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void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
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uint8_t *link_bw, uint8_t *rate_select)
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u8 *link_bw, u8 *rate_select)
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{
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/* eDP 1.4 rate select method. */
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if (intel_dp->use_rate_select) {
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@ -2217,7 +2217,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
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}
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void intel_dp_set_link_params(struct intel_dp *intel_dp,
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int link_rate, uint8_t lane_count,
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int link_rate, u8 lane_count,
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bool link_mst)
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{
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intel_dp->link_trained = false;
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@ -3177,20 +3177,20 @@ static void chv_post_disable_dp(struct intel_encoder *encoder,
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static void
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_intel_dp_set_link_train(struct intel_dp *intel_dp,
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uint32_t *DP,
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uint8_t dp_train_pat)
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u32 *DP,
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u8 dp_train_pat)
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{
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struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
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struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
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enum port port = intel_dig_port->base.port;
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uint8_t train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
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u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
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if (dp_train_pat & train_pat_mask)
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DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
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dp_train_pat & train_pat_mask);
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if (HAS_DDI(dev_priv)) {
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uint32_t temp = I915_READ(DP_TP_CTL(port));
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u32 temp = I915_READ(DP_TP_CTL(port));
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if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
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temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
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@ -3289,7 +3289,7 @@ static void intel_enable_dp(struct intel_encoder *encoder,
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
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struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
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uint32_t dp_reg = I915_READ(intel_dp->output_reg);
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u32 dp_reg = I915_READ(intel_dp->output_reg);
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enum pipe pipe = crtc->pipe;
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intel_wakeref_t wakeref;
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@ -3508,14 +3508,14 @@ static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
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* link status information
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*/
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bool
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intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
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intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE])
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{
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return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
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DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
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}
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/* These are source-specific values. */
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uint8_t
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u8
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intel_dp_voltage_max(struct intel_dp *intel_dp)
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{
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struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
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@ -3534,8 +3534,8 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
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return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
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}
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uint8_t
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intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
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u8
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intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing)
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{
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struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
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struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
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@ -3580,12 +3580,12 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
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}
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}
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static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
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static u32 vlv_signal_levels(struct intel_dp *intel_dp)
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{
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struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
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unsigned long demph_reg_value, preemph_reg_value,
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uniqtranscale_reg_value;
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uint8_t train_set = intel_dp->train_set[0];
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u8 train_set = intel_dp->train_set[0];
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switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
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case DP_TRAIN_PRE_EMPH_LEVEL_0:
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@ -3666,12 +3666,12 @@ static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
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return 0;
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}
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static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
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static u32 chv_signal_levels(struct intel_dp *intel_dp)
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{
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struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
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u32 deemph_reg_value, margin_reg_value;
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bool uniq_trans_scale = false;
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uint8_t train_set = intel_dp->train_set[0];
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u8 train_set = intel_dp->train_set[0];
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switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
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case DP_TRAIN_PRE_EMPH_LEVEL_0:
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@ -3749,10 +3749,10 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
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return 0;
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}
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static uint32_t
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g4x_signal_levels(uint8_t train_set)
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static u32
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g4x_signal_levels(u8 train_set)
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{
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uint32_t signal_levels = 0;
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u32 signal_levels = 0;
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switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
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case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
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@ -3788,8 +3788,8 @@ g4x_signal_levels(uint8_t train_set)
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}
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/* SNB CPU eDP voltage swing and pre-emphasis control */
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static uint32_t
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snb_cpu_edp_signal_levels(uint8_t train_set)
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static u32
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snb_cpu_edp_signal_levels(u8 train_set)
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{
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int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
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DP_TRAIN_PRE_EMPHASIS_MASK);
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@ -3816,8 +3816,8 @@ snb_cpu_edp_signal_levels(uint8_t train_set)
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}
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/* IVB CPU eDP voltage swing and pre-emphasis control */
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static uint32_t
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ivb_cpu_edp_signal_levels(uint8_t train_set)
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static u32
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ivb_cpu_edp_signal_levels(u8 train_set)
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{
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int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
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DP_TRAIN_PRE_EMPHASIS_MASK);
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@ -3852,8 +3852,8 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
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struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
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struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
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enum port port = intel_dig_port->base.port;
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uint32_t signal_levels, mask = 0;
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uint8_t train_set = intel_dp->train_set[0];
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u32 signal_levels, mask = 0;
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u8 train_set = intel_dp->train_set[0];
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if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
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signal_levels = bxt_signal_levels(intel_dp);
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@ -3892,7 +3892,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
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void
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intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
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uint8_t dp_train_pat)
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u8 dp_train_pat)
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{
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struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
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struct drm_i915_private *dev_priv =
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@ -3909,7 +3909,7 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
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struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
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struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
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enum port port = intel_dig_port->base.port;
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uint32_t val;
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u32 val;
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if (!HAS_DDI(dev_priv))
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return;
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@ -3944,7 +3944,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
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struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
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struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
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enum port port = encoder->port;
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uint32_t DP = intel_dp->DP;
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u32 DP = intel_dp->DP;
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if (WARN_ON(HAS_DDI(dev_priv)))
|
||||
return;
|
||||
|
|
@ -4285,7 +4285,7 @@ intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
|
|||
DP_DPRX_ESI_LEN;
|
||||
}
|
||||
|
||||
u16 intel_dp_dsc_get_output_bpp(int link_clock, uint8_t lane_count,
|
||||
u16 intel_dp_dsc_get_output_bpp(int link_clock, u8 lane_count,
|
||||
int mode_clock, int mode_hdisplay)
|
||||
{
|
||||
u16 bits_per_pixel, max_bpp_small_joiner_ram;
|
||||
|
|
@ -4352,7 +4352,7 @@ u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
|
|||
return 0;
|
||||
}
|
||||
/* Also take into account max slice width */
|
||||
min_slice_count = min_t(uint8_t, min_slice_count,
|
||||
min_slice_count = min_t(u8, min_slice_count,
|
||||
DIV_ROUND_UP(mode_hdisplay,
|
||||
max_slice_width));
|
||||
|
||||
|
|
@ -4370,11 +4370,11 @@ u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
|
||||
static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
|
||||
{
|
||||
int status = 0;
|
||||
int test_link_rate;
|
||||
uint8_t test_lane_count, test_link_bw;
|
||||
u8 test_lane_count, test_link_bw;
|
||||
/* (DP CTS 1.2)
|
||||
* 4.3.1.11
|
||||
*/
|
||||
|
|
@ -4407,10 +4407,10 @@ static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
|
|||
return DP_TEST_ACK;
|
||||
}
|
||||
|
||||
static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
|
||||
static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
|
||||
{
|
||||
uint8_t test_pattern;
|
||||
uint8_t test_misc;
|
||||
u8 test_pattern;
|
||||
u8 test_misc;
|
||||
__be16 h_width, v_height;
|
||||
int status = 0;
|
||||
|
||||
|
|
@ -4468,9 +4468,9 @@ static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
|
|||
return DP_TEST_ACK;
|
||||
}
|
||||
|
||||
static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
|
||||
static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
|
||||
{
|
||||
uint8_t test_result = DP_TEST_ACK;
|
||||
u8 test_result = DP_TEST_ACK;
|
||||
struct intel_connector *intel_connector = intel_dp->attached_connector;
|
||||
struct drm_connector *connector = &intel_connector->base;
|
||||
|
||||
|
|
@ -4512,16 +4512,16 @@ static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
|
|||
return test_result;
|
||||
}
|
||||
|
||||
static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
|
||||
static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
|
||||
{
|
||||
uint8_t test_result = DP_TEST_NAK;
|
||||
u8 test_result = DP_TEST_NAK;
|
||||
return test_result;
|
||||
}
|
||||
|
||||
static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
|
||||
{
|
||||
uint8_t response = DP_TEST_NAK;
|
||||
uint8_t request = 0;
|
||||
u8 response = DP_TEST_NAK;
|
||||
u8 request = 0;
|
||||
int status;
|
||||
|
||||
status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
|
||||
|
|
@ -4847,8 +4847,8 @@ static enum drm_connector_status
|
|||
intel_dp_detect_dpcd(struct intel_dp *intel_dp)
|
||||
{
|
||||
struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
|
||||
uint8_t *dpcd = intel_dp->dpcd;
|
||||
uint8_t type;
|
||||
u8 *dpcd = intel_dp->dpcd;
|
||||
u8 type;
|
||||
|
||||
if (lspcon->active)
|
||||
lspcon_resume(lspcon);
|
||||
|
|
@ -5630,7 +5630,7 @@ int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
|
|||
.address = DP_AUX_HDCP_AKSV,
|
||||
.size = DRM_HDCP_KSV_LEN,
|
||||
};
|
||||
uint8_t txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
|
||||
u8 txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
|
||||
ssize_t dpcd_ret;
|
||||
int ret;
|
||||
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
#include "intel_drv.h"
|
||||
|
||||
static void
|
||||
intel_dp_dump_link_status(const uint8_t link_status[DP_LINK_STATUS_SIZE])
|
||||
intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
|
||||
{
|
||||
|
||||
DRM_DEBUG_KMS("ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x",
|
||||
|
|
@ -34,17 +34,17 @@ intel_dp_dump_link_status(const uint8_t link_status[DP_LINK_STATUS_SIZE])
|
|||
|
||||
static void
|
||||
intel_get_adjust_train(struct intel_dp *intel_dp,
|
||||
const uint8_t link_status[DP_LINK_STATUS_SIZE])
|
||||
const u8 link_status[DP_LINK_STATUS_SIZE])
|
||||
{
|
||||
uint8_t v = 0;
|
||||
uint8_t p = 0;
|
||||
u8 v = 0;
|
||||
u8 p = 0;
|
||||
int lane;
|
||||
uint8_t voltage_max;
|
||||
uint8_t preemph_max;
|
||||
u8 voltage_max;
|
||||
u8 preemph_max;
|
||||
|
||||
for (lane = 0; lane < intel_dp->lane_count; lane++) {
|
||||
uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
|
||||
uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
|
||||
u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
|
||||
u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
|
||||
|
||||
if (this_v > v)
|
||||
v = this_v;
|
||||
|
|
@ -66,9 +66,9 @@ intel_get_adjust_train(struct intel_dp *intel_dp,
|
|||
|
||||
static bool
|
||||
intel_dp_set_link_train(struct intel_dp *intel_dp,
|
||||
uint8_t dp_train_pat)
|
||||
u8 dp_train_pat)
|
||||
{
|
||||
uint8_t buf[sizeof(intel_dp->train_set) + 1];
|
||||
u8 buf[sizeof(intel_dp->train_set) + 1];
|
||||
int ret, len;
|
||||
|
||||
intel_dp_program_link_training_pattern(intel_dp, dp_train_pat);
|
||||
|
|
@ -92,7 +92,7 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
|
|||
|
||||
static bool
|
||||
intel_dp_reset_link_train(struct intel_dp *intel_dp,
|
||||
uint8_t dp_train_pat)
|
||||
u8 dp_train_pat)
|
||||
{
|
||||
memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
|
||||
intel_dp_set_signal_levels(intel_dp);
|
||||
|
|
@ -128,11 +128,11 @@ static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp)
|
|||
static bool
|
||||
intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
|
||||
{
|
||||
uint8_t voltage;
|
||||
u8 voltage;
|
||||
int voltage_tries, cr_tries, max_cr_tries;
|
||||
bool max_vswing_reached = false;
|
||||
uint8_t link_config[2];
|
||||
uint8_t link_bw, rate_select;
|
||||
u8 link_config[2];
|
||||
u8 link_bw, rate_select;
|
||||
|
||||
if (intel_dp->prepare_link_retrain)
|
||||
intel_dp->prepare_link_retrain(intel_dp);
|
||||
|
|
@ -186,7 +186,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
|
|||
|
||||
voltage_tries = 1;
|
||||
for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) {
|
||||
uint8_t link_status[DP_LINK_STATUS_SIZE];
|
||||
u8 link_status[DP_LINK_STATUS_SIZE];
|
||||
|
||||
drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
|
||||
|
||||
|
|
@ -282,7 +282,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
|
|||
{
|
||||
int tries;
|
||||
u32 training_pattern;
|
||||
uint8_t link_status[DP_LINK_STATUS_SIZE];
|
||||
u8 link_status[DP_LINK_STATUS_SIZE];
|
||||
bool channel_eq = false;
|
||||
|
||||
training_pattern = intel_dp_training_pattern(intel_dp);
|
||||
|
|
|
|||
Loading…
Reference in New Issue