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arm64: dts: renesas: ebisu, draak: Limit EtherAVB to 100Mbps 

* According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of
  August 24, 2018, the TX clock internal delay mode isn't supported
  on R-Car E3 (r8a77990) and D3 (r8a77995).

* TX clock internal delay mode is required for reliable 1Gbps communication
  using the KSZ9031RNX phy present on the Ebisu and Draak boards.

Thus, the E3 based Ebisu and D3 based Draak boards can not reliably
use 1Gbps and the speed should be limited to 100Mbps.

Based on work by Kazuya Mizuguchi.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Simon Horman 2019-07-29 10:03:56 +02:00 committed by Geert Uytterhoeven
parent e77ad88d0c
commit 8703ba77ec
2 changed files with 16 additions and 0 deletions
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8
arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
View File

@ -271,6 +271,14 @@ phy0: ethernet-phy@0 {
interrupt-parent = <&gpio2>;
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
/*
* TX clock internal delay mode is required for reliable
* 1Gbps communication using the KSZ9031RNX phy present on
* the Ebisu board, however, TX clock internal delay mode
* isn't supported on r8a77990. Thus, limit speed to
* 100Mbps for reliable communication.
*/
max-speed = <100>;
};
};

8
arch/arm64/boot/dts/renesas/r8a77995-draak.dts
View File

@ -175,6 +175,14 @@ phy0: ethernet-phy@0 {
reg = <0>;
interrupt-parent = <&gpio5>;
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
/*
* TX clock internal delay mode is required for reliable
* 1Gbps communication using the KSZ9031RNX phy present on
* the Draak board, however, TX clock internal delay mode
* isn't supported on r8a77995. Thus, limit speed to
* 100Mbps for reliable communication.
*/
max-speed = <100>;
};
};