mirror of https://gitee.com/openkylin/linux.git
OMAP2PLUS: DSS2: Make members of dss_clk_source generic
The enum members of 'dss_clk_source' have clock source names specific to OMAP2/3. Change the names to more generic terms such that they now describe where the clocks come from and what they are used for. Also, change the enum member names to have "DSS_CLK_SRC" instead of "DSS_SRC" for more clarity. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
parent
819d807c59
commit
88134fa138
|
@ -2334,7 +2334,7 @@ unsigned long dispc_fclk_rate(void)
|
|||
{
|
||||
unsigned long r = 0;
|
||||
|
||||
if (dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK)
|
||||
if (dss_get_dispc_clk_source() == DSS_CLK_SRC_FCK)
|
||||
r = dss_clk_get_rate(DSS_CLK_FCK);
|
||||
else
|
||||
#ifdef CONFIG_OMAP2_DSS_DSI
|
||||
|
@ -2385,7 +2385,7 @@ void dispc_dump_clocks(struct seq_file *s)
|
|||
seq_printf(s, "- DISPC -\n");
|
||||
|
||||
seq_printf(s, "dispc fclk source = %s\n",
|
||||
dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
|
||||
dss_get_dispc_clk_source() == DSS_CLK_SRC_FCK ?
|
||||
"dss1_alwon_fclk" : "dsi1_pll_fclk");
|
||||
|
||||
seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
|
||||
|
|
|
@ -57,7 +57,7 @@ static int dpi_set_dsi_clk(struct omap_dss_device *dssdev, bool is_tft,
|
|||
if (r)
|
||||
return r;
|
||||
|
||||
dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK);
|
||||
dss_select_dispc_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC);
|
||||
|
||||
r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
|
||||
if (r)
|
||||
|
@ -217,7 +217,7 @@ void omapdss_dpi_display_disable(struct omap_dss_device *dssdev)
|
|||
dssdev->manager->disable(dssdev->manager);
|
||||
|
||||
#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
|
||||
dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
|
||||
dss_select_dispc_clk_source(DSS_CLK_SRC_FCK);
|
||||
dsi_pll_uninit();
|
||||
dss_clk_disable(DSS_CLK_SYSCK);
|
||||
#endif
|
||||
|
|
|
@ -731,7 +731,7 @@ static unsigned long dsi_fclk_rate(void)
|
|||
{
|
||||
unsigned long r;
|
||||
|
||||
if (dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK) {
|
||||
if (dss_get_dsi_clk_source() == DSS_CLK_SRC_FCK) {
|
||||
/* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */
|
||||
r = dss_clk_get_rate(DSS_CLK_FCK);
|
||||
} else {
|
||||
|
@ -1188,19 +1188,19 @@ void dsi_dump_clocks(struct seq_file *s)
|
|||
seq_printf(s, "dsi1_pll_fck\t%-16luregm3 %u\t(%s)\n",
|
||||
cinfo->dsi1_pll_fclk,
|
||||
cinfo->regm3,
|
||||
dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
|
||||
dss_get_dispc_clk_source() == DSS_CLK_SRC_FCK ?
|
||||
"off" : "on");
|
||||
|
||||
seq_printf(s, "dsi2_pll_fck\t%-16luregm4 %u\t(%s)\n",
|
||||
cinfo->dsi2_pll_fclk,
|
||||
cinfo->regm4,
|
||||
dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
|
||||
dss_get_dsi_clk_source() == DSS_CLK_SRC_FCK ?
|
||||
"off" : "on");
|
||||
|
||||
seq_printf(s, "- DSI -\n");
|
||||
|
||||
seq_printf(s, "dsi fclk source = %s\n",
|
||||
dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
|
||||
dss_get_dsi_clk_source() == DSS_CLK_SRC_FCK ?
|
||||
"dss1_alwon_fclk" : "dsi2_pll_fclk");
|
||||
|
||||
seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate());
|
||||
|
@ -3038,8 +3038,8 @@ static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
|
|||
if (r)
|
||||
goto err1;
|
||||
|
||||
dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK);
|
||||
dss_select_dsi_clk_source(DSS_SRC_DSI2_PLL_FCLK);
|
||||
dss_select_dispc_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC);
|
||||
dss_select_dsi_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI);
|
||||
|
||||
DSSDBG("PLL OK\n");
|
||||
|
||||
|
@ -3075,8 +3075,8 @@ static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
|
|||
err3:
|
||||
dsi_complexio_uninit();
|
||||
err2:
|
||||
dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
|
||||
dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
|
||||
dss_select_dispc_clk_source(DSS_CLK_SRC_FCK);
|
||||
dss_select_dsi_clk_source(DSS_CLK_SRC_FCK);
|
||||
err1:
|
||||
dsi_pll_uninit();
|
||||
err0:
|
||||
|
@ -3092,8 +3092,8 @@ static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev)
|
|||
dsi_vc_enable(2, 0);
|
||||
dsi_vc_enable(3, 0);
|
||||
|
||||
dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
|
||||
dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
|
||||
dss_select_dispc_clk_source(DSS_CLK_SRC_FCK);
|
||||
dss_select_dsi_clk_source(DSS_CLK_SRC_FCK);
|
||||
dsi_complexio_uninit();
|
||||
dsi_pll_uninit();
|
||||
}
|
||||
|
|
|
@ -278,12 +278,12 @@ void dss_select_dispc_clk_source(enum dss_clk_source clk_src)
|
|||
{
|
||||
int b;
|
||||
|
||||
BUG_ON(clk_src != DSS_SRC_DSI1_PLL_FCLK &&
|
||||
clk_src != DSS_SRC_DSS1_ALWON_FCLK);
|
||||
BUG_ON(clk_src != DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC &&
|
||||
clk_src != DSS_CLK_SRC_FCK);
|
||||
|
||||
b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1;
|
||||
b = clk_src == DSS_CLK_SRC_FCK ? 0 : 1;
|
||||
|
||||
if (clk_src == DSS_SRC_DSI1_PLL_FCLK)
|
||||
if (clk_src == DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC)
|
||||
dsi_wait_dsi1_pll_active();
|
||||
|
||||
REG_FLD_MOD(DSS_CONTROL, b, 0, 0); /* DISPC_CLK_SWITCH */
|
||||
|
@ -295,12 +295,12 @@ void dss_select_dsi_clk_source(enum dss_clk_source clk_src)
|
|||
{
|
||||
int b;
|
||||
|
||||
BUG_ON(clk_src != DSS_SRC_DSI2_PLL_FCLK &&
|
||||
clk_src != DSS_SRC_DSS1_ALWON_FCLK);
|
||||
BUG_ON(clk_src != DSS_CLK_SRC_DSI_PLL_HSDIV_DSI &&
|
||||
clk_src != DSS_CLK_SRC_FCK);
|
||||
|
||||
b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1;
|
||||
b = clk_src == DSS_CLK_SRC_FCK ? 0 : 1;
|
||||
|
||||
if (clk_src == DSS_SRC_DSI2_PLL_FCLK)
|
||||
if (clk_src == DSS_CLK_SRC_DSI_PLL_HSDIV_DSI)
|
||||
dsi_wait_dsi2_pll_active();
|
||||
|
||||
REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */
|
||||
|
@ -601,8 +601,8 @@ static int dss_init(bool skip_init)
|
|||
}
|
||||
}
|
||||
|
||||
dss.dsi_clk_source = DSS_SRC_DSS1_ALWON_FCLK;
|
||||
dss.dispc_clk_source = DSS_SRC_DSS1_ALWON_FCLK;
|
||||
dss.dsi_clk_source = DSS_CLK_SRC_FCK;
|
||||
dss.dispc_clk_source = DSS_CLK_SRC_FCK;
|
||||
|
||||
dss_save_context();
|
||||
|
||||
|
|
|
@ -118,9 +118,9 @@ enum dss_clock {
|
|||
};
|
||||
|
||||
enum dss_clk_source {
|
||||
DSS_SRC_DSI1_PLL_FCLK,
|
||||
DSS_SRC_DSI2_PLL_FCLK,
|
||||
DSS_SRC_DSS1_ALWON_FCLK,
|
||||
DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* DSI1_PLL_FCLK */
|
||||
DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* DSI2_PLL_FCLK */
|
||||
DSS_CLK_SRC_FCK, /* DSS1_ALWON_FCLK */
|
||||
};
|
||||
|
||||
struct dss_clock_info {
|
||||
|
|
Loading…
Reference in New Issue