mlx5-fixes-2017-08-30

-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJZpwI7AAoJEEg/ir3gV/o+9BUH+gJJb5D7kzkc+KH4vKr/TS9D
 VMI/oDqhe44Eeag5d0gUjRF9You8708YRpCu6j3sHtnlfi9Ii21cjwd9P3QbshAn
 vLt0EjL1fzrvqYjeBLYvbNxdK8qYViTWC6yigBYLKFWhQXdatVrqWhikqgtUw3/n
 IP3IO5KUwUGDfGEMtbtdECNDrVM8NZIi9K/XFbkTHSIMzbi1qogiP8Ufdy2p1ORP
 qq5mEorxHrGiMUqPAA8VLXsLDrnLRKnETokexUt/1dR0fJ32152mgeUniNxQvbs/
 qnHdmMvnKaPofrFUrNqRCXtjOoxYhV0iv8eGyEv0Iz/hm3pitqr2M5rp1ZMffII=
 =Rr1v
 -----END PGP SIGNATURE-----

Merge tag 'mlx5-fixes-2017-08-30' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux

Saeed Mahameed says:

====================
Mellanox, mlx5 fixes 2017-08-30

This series contains some misc fixes to the mlx5 driver.

Please pull and let me know if there's any problem.

For -stable:

Kernels >= 4.12
	net/mlx5e: Fix CQ moderation mode not set properly
	net/mlx5e: Don't override user RSS upon set channels

Kernels >= 4.11
	net/mlx5e: Properly resolve TC offloaded ipv6 vxlan tunnel source address

Kernels >= 4.10
	net/mlx5e: Fix DCB_CAP_ATTR_DCBX capability for DCBNL getcap
	net/mlx5e: Check for qos capability in dcbnl_initialize

Kernels >= 4.9
	net/mlx5e: Fix dangling page pointer on DMA mapping error

Kernels >= 4.8
	net/mlx5e: Fix inline header size for small packets
	net/mlx5: E-Switch, Unload the representors in the correct order
    	net/mlx5: Fix arm SRQ command for ISSI version 0
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2017-08-30 16:39:01 -07:00
commit a1bc54a2e4
11 changed files with 44 additions and 39 deletions

View File

@ -263,6 +263,7 @@ struct mlx5e_dcbx {
/* The only setting that cannot be read from FW */
u8 tc_tsa[IEEE_8021QAZ_MAX_TCS];
u8 cap;
};
#endif

View File

@ -288,13 +288,8 @@ static int mlx5e_dcbnl_ieee_setpfc(struct net_device *dev,
static u8 mlx5e_dcbnl_getdcbx(struct net_device *dev)
{
struct mlx5e_priv *priv = netdev_priv(dev);
struct mlx5e_dcbx *dcbx = &priv->dcbx;
u8 mode = DCB_CAP_DCBX_VER_IEEE | DCB_CAP_DCBX_VER_CEE;
if (dcbx->mode == MLX5E_DCBX_PARAM_VER_OPER_HOST)
mode |= DCB_CAP_DCBX_HOST;
return mode;
return priv->dcbx.cap;
}
static u8 mlx5e_dcbnl_setdcbx(struct net_device *dev, u8 mode)
@ -312,6 +307,7 @@ static u8 mlx5e_dcbnl_setdcbx(struct net_device *dev, u8 mode)
/* set dcbx to fw controlled */
if (!mlx5e_dcbnl_set_dcbx_mode(priv, MLX5E_DCBX_PARAM_VER_OPER_AUTO)) {
dcbx->mode = MLX5E_DCBX_PARAM_VER_OPER_AUTO;
dcbx->cap &= ~DCB_CAP_DCBX_HOST;
return 0;
}
@ -324,6 +320,8 @@ static u8 mlx5e_dcbnl_setdcbx(struct net_device *dev, u8 mode)
if (mlx5e_dcbnl_switch_to_host_mode(netdev_priv(dev)))
return 1;
dcbx->cap = mode;
return 0;
}
@ -628,9 +626,9 @@ static u8 mlx5e_dcbnl_getcap(struct net_device *netdev,
*cap = false;
break;
case DCB_CAP_ATTR_DCBX:
*cap = (DCB_CAP_DCBX_LLD_MANAGED |
DCB_CAP_DCBX_VER_CEE |
DCB_CAP_DCBX_STATIC);
*cap = priv->dcbx.cap |
DCB_CAP_DCBX_VER_CEE |
DCB_CAP_DCBX_VER_IEEE;
break;
default:
*cap = 0;
@ -754,8 +752,16 @@ void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv)
{
struct mlx5e_dcbx *dcbx = &priv->dcbx;
if (!MLX5_CAP_GEN(priv->mdev, qos))
return;
if (MLX5_CAP_GEN(priv->mdev, dcbx))
mlx5e_dcbnl_query_dcbx_mode(priv, &dcbx->mode);
priv->dcbx.cap = DCB_CAP_DCBX_VER_CEE |
DCB_CAP_DCBX_VER_IEEE;
if (priv->dcbx.mode == MLX5E_DCBX_PARAM_VER_OPER_HOST)
priv->dcbx.cap |= DCB_CAP_DCBX_HOST;
mlx5e_ets_init(priv);
}

View File

@ -641,8 +641,10 @@ int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
new_channels.params = priv->channels.params;
new_channels.params.num_channels = count;
mlx5e_build_default_indir_rqt(priv->mdev, new_channels.params.indirection_rqt,
MLX5E_INDIR_RQT_SIZE, count);
if (!netif_is_rxfh_configured(priv->netdev))
mlx5e_build_default_indir_rqt(priv->mdev,
new_channels.params.indirection_rqt,
MLX5E_INDIR_RQT_SIZE, count);
if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
priv->channels.params = new_channels.params;

View File

@ -1969,6 +1969,7 @@ static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
}
mlx5e_build_common_cq_param(priv, param);
param->cq_period_mode = params->rx_cq_period_mode;
}
static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,

View File

@ -222,13 +222,13 @@ static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq,
if (unlikely(!page))
return -ENOMEM;
dma_info->page = page;
dma_info->addr = dma_map_page(rq->pdev, page, 0,
RQ_PAGE_SIZE(rq), rq->buff.map_dir);
if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
put_page(page);
return -ENOMEM;
}
dma_info->page = page;
return 0;
}

View File

@ -1443,12 +1443,10 @@ static int mlx5e_route_lookup_ipv6(struct mlx5e_priv *priv,
struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
int ret;
dst = ip6_route_output(dev_net(mirred_dev), NULL, fl6);
ret = dst->error;
if (ret) {
dst_release(dst);
ret = ipv6_stub->ipv6_dst_lookup(dev_net(mirred_dev), NULL, &dst,
fl6);
if (ret < 0)
return ret;
}
*out_ttl = ip6_dst_hoplimit(dst);

View File

@ -128,10 +128,10 @@ static inline int mlx5e_skb_l3_header_offset(struct sk_buff *skb)
return mlx5e_skb_l2_header_offset(skb);
}
static inline unsigned int mlx5e_calc_min_inline(enum mlx5_inline_modes mode,
struct sk_buff *skb)
static inline u16 mlx5e_calc_min_inline(enum mlx5_inline_modes mode,
struct sk_buff *skb)
{
int hlen;
u16 hlen;
switch (mode) {
case MLX5_INLINE_MODE_NONE:
@ -140,19 +140,22 @@ static inline unsigned int mlx5e_calc_min_inline(enum mlx5_inline_modes mode,
hlen = eth_get_headlen(skb->data, skb_headlen(skb));
if (hlen == ETH_HLEN && !skb_vlan_tag_present(skb))
hlen += VLAN_HLEN;
return hlen;
break;
case MLX5_INLINE_MODE_IP:
/* When transport header is set to zero, it means no transport
* header. When transport header is set to 0xff's, it means
* transport header wasn't set.
*/
if (skb_transport_offset(skb))
return mlx5e_skb_l3_header_offset(skb);
if (skb_transport_offset(skb)) {
hlen = mlx5e_skb_l3_header_offset(skb);
break;
}
/* fall through */
case MLX5_INLINE_MODE_L2:
default:
return mlx5e_skb_l2_header_offset(skb);
hlen = mlx5e_skb_l2_header_offset(skb);
}
return min_t(u16, hlen, skb->len);
}
static inline void mlx5e_tx_skb_pull_inline(unsigned char **skb_data,

View File

@ -815,7 +815,7 @@ void esw_offloads_cleanup(struct mlx5_eswitch *esw, int nvports)
struct mlx5_eswitch_rep *rep;
int vport;
for (vport = 0; vport < nvports; vport++) {
for (vport = nvports - 1; vport >= 0; vport--) {
rep = &esw->offloads.vport_reps[vport];
if (!rep->valid)
continue;

View File

@ -1186,7 +1186,6 @@ static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
}
}
clear_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state);
set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
out:
mutex_unlock(&dev->intf_state_mutex);
@ -1261,7 +1260,7 @@ static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
mlx5_drain_health_recovery(dev);
mutex_lock(&dev->intf_state_mutex);
if (test_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state)) {
if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
__func__);
if (cleanup)
@ -1270,7 +1269,6 @@ static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
}
clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
set_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state);
if (mlx5_device_registered(dev))
mlx5_detach_device(dev);
@ -1565,8 +1563,6 @@ static void shutdown(struct pci_dev *pdev)
int err;
dev_info(&pdev->dev, "Shutdown was called\n");
/* Notify mlx5 clients that the kernel is being shut down */
set_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &dev->intf_state);
err = mlx5_try_fast_unload(dev);
if (err)
mlx5_unload_one(dev, priv, false);

View File

@ -201,13 +201,13 @@ static int destroy_srq_cmd(struct mlx5_core_dev *dev,
static int arm_srq_cmd(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
u16 lwm, int is_srq)
{
/* arm_srq structs missing using identical xrc ones */
u32 srq_in[MLX5_ST_SZ_DW(arm_xrc_srq_in)] = {0};
u32 srq_out[MLX5_ST_SZ_DW(arm_xrc_srq_out)] = {0};
u32 srq_in[MLX5_ST_SZ_DW(arm_rq_in)] = {0};
u32 srq_out[MLX5_ST_SZ_DW(arm_rq_out)] = {0};
MLX5_SET(arm_xrc_srq_in, srq_in, opcode, MLX5_CMD_OP_ARM_XRC_SRQ);
MLX5_SET(arm_xrc_srq_in, srq_in, xrc_srqn, srq->srqn);
MLX5_SET(arm_xrc_srq_in, srq_in, lwm, lwm);
MLX5_SET(arm_rq_in, srq_in, opcode, MLX5_CMD_OP_ARM_RQ);
MLX5_SET(arm_rq_in, srq_in, op_mod, MLX5_ARM_RQ_IN_OP_MOD_SRQ);
MLX5_SET(arm_rq_in, srq_in, srq_number, srq->srqn);
MLX5_SET(arm_rq_in, srq_in, lwm, lwm);
return mlx5_cmd_exec(dev, srq_in, sizeof(srq_in),
srq_out, sizeof(srq_out));

View File

@ -673,9 +673,7 @@ enum mlx5_device_state {
};
enum mlx5_interface_state {
MLX5_INTERFACE_STATE_DOWN = BIT(0),
MLX5_INTERFACE_STATE_UP = BIT(1),
MLX5_INTERFACE_STATE_SHUTDOWN = BIT(2),
MLX5_INTERFACE_STATE_UP = BIT(0),
};
enum mlx5_pci_status {