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ARM: sunxi: add PLL5 and PLL6 support 

This commit adds PLL5 and PLL6 nodes to the sun4i, sun5i and sun7i
device trees.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit is contained in:
Emilio López 2013-12-23 00:32:38 -03:00
parent ec5589f7a3
commit c3e5e66b65
4 changed files with 67 additions and 18 deletions
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19
arch/arm/boot/dts/sun4i-a10.dtsi
View File

@ -73,6 +73,22 @@ pll4: pll4@01c20018 {
clocks = <&osc24M>;
};
pll5: pll5@01c20020 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-pll5-clk";
reg = <0x01c20020 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll5_ddr", "pll5_other";
};
pll6: pll6@01c20028 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-pll6-clk";
reg = <0x01c20028 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll6_sata", "pll6_other", "pll6";
};
/* dummy is 200M */
cpu: cpu@01c20054 {
#clock-cells = <0>;
@ -138,12 +154,11 @@ apb0_gates: apb0_gates@01c20068 {
"apb0_ir1", "apb0_keypad";
};
/* dummy is pll62 */
apb1_mux: apb1_mux@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-apb1-mux-clk";
reg = <0x01c20058 0x4>;
clocks = <&osc24M>, <&dummy>, <&osc32k>;
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
};
apb1: apb1@01c20058 {

19
arch/arm/boot/dts/sun5i-a10s.dtsi
View File

@ -70,6 +70,22 @@ pll4: pll4@01c20018 {
clocks = <&osc24M>;
};
pll5: pll5@01c20020 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-pll5-clk";
reg = <0x01c20020 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll5_ddr", "pll5_other";
};
pll6: pll6@01c20028 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-pll6-clk";
reg = <0x01c20028 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll6_sata", "pll6_other", "pll6";
};
/* dummy is 200M */
cpu: cpu@01c20054 {
#clock-cells = <0>;
@ -130,12 +146,11 @@ apb0_gates: apb0_gates@01c20068 {
"apb0_ir", "apb0_keypad";
};
/* dummy is pll62 */
apb1_mux: apb1_mux@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-apb1-mux-clk";
reg = <0x01c20058 0x4>;
clocks = <&osc24M>, <&dummy>, <&osc32k>;
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
};
apb1: apb1@01c20058 {

19
arch/arm/boot/dts/sun5i-a13.dtsi
View File

@ -74,6 +74,22 @@ pll4: pll4@01c20018 {
clocks = <&osc24M>;
};
pll5: pll5@01c20020 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-pll5-clk";
reg = <0x01c20020 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll5_ddr", "pll5_other";
};
pll6: pll6@01c20028 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-pll6-clk";
reg = <0x01c20028 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll6_sata", "pll6_other", "pll6";
};
/* dummy is 200M */
cpu: cpu@01c20054 {
#clock-cells = <0>;
@ -132,12 +148,11 @@ apb0_gates: apb0_gates@01c20068 {
clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
};
/* dummy is pll6 */
apb1_mux: apb1_mux@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-apb1-mux-clk";
reg = <0x01c20058 0x4>;
clocks = <&osc24M>, <&dummy>, <&osc32k>;
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
};
apb1: apb1@01c20058 {

28
arch/arm/boot/dts/sun7i-a20.dtsi
View File

@ -69,23 +69,27 @@ pll4: pll4@01c20018 {
clocks = <&osc24M>;
};
/*
* This is a dummy clock, to be used as placeholder on
* other mux clocks when a specific parent clock is not
* yet implemented. It should be dropped when the driver
* is complete.
*/
pll6: pll6 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
pll5: pll5@01c20020 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-pll5-clk";
reg = <0x01c20020 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll5_ddr", "pll5_other";
};
pll6: pll6@01c20028 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-pll6-clk";
reg = <0x01c20028 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll6_sata", "pll6_other", "pll6";
};
cpu: cpu@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-cpu-clk";
reg = <0x01c20054 0x4>;
clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>;
clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
};
axi: axi@01c20054 {
@ -144,7 +148,7 @@ apb1_mux: apb1_mux@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-apb1-mux-clk";
reg = <0x01c20058 0x4>;
clocks = <&osc24M>, <&pll6>, <&osc32k>;
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
};
apb1: apb1@01c20058 {