mirror of https://gitee.com/openkylin/linux.git
ARM: new SoC support for v5.9
There are three SoC families newly dded to the 32-bit and
64-bit Arm architecture code in the kernel this time:
- Daniel Palmer adds initial support for two chips made by MStar, a
taiwanese SoC manufacturer that became part of Mediatek in 2012. For
now, the added support is fairly minimal, with just two of its
Cortex-A7 based 32-bit camera chips getting support for a limited
set of on-chip peripherals.
- Lars Povlsen from Microchip adds support for their new Sparx5
family of ethernet switch chips using 64-bit Cortex-A53 cores.
These are descended from earlier VSC7xxx SparX and Ocelot chips
using 32-bit MIPS cores.
- Daniele Alessandrelli from Intel adds support for the new Keem Bay
SoC for computer vision, built around a Movidius VPU with Linux
running on Arm Cortex-A53 cores.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'arm-newsoc-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull new ARM SoC support from Arnd Bergmann:
"There are three SoC families newly dded to the 32-bit and 64-bit Arm
architecture code in the kernel this time:
- Daniel Palmer adds initial support for two chips made by MStar, a
taiwanese SoC manufacturer that became part of Mediatek in 2012.
For now, the added support is fairly minimal, with just two of its
Cortex-A7 based 32-bit camera chips getting support for a limited
set of on-chip peripherals.
- Lars Povlsen from Microchip adds support for their new Sparx5
family of ethernet switch chips using 64-bit Cortex-A53 cores.
These are descended from earlier VSC7xxx SparX and Ocelot chips
using 32-bit MIPS cores.
- Daniele Alessandrelli from Intel adds support for the new Keem Bay
SoC for computer vision, built around a Movidius VPU with Linux
running on Arm Cortex-A53 cores"
* tag 'arm-newsoc-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (38 commits)
ARM: mstar: Correct the compatible string for pmsleep
dt-bindings: arm: mstar: remove the binding description for mstar,pmsleep
dt-bindings: mfd: syscon: add compatible string for mstar,msc313-pmsleep
ARM: mstar: Add reboot support
ARM: mstar: Add "pmsleep" node to base dtsi
ARM: mstar: Add PMU
ARM: mstar: Adjust IMI size for infinity3
ARM: mstar: Adjust IMI size for mercury5
ARM: mstar: Adjust IMI size of infinity
ARM: mstar: Add IMI SRAM region
dt-bindings: arm: mstar: Move existing MStar binding descriptions
dt-bindings: arm: mstar: Add binding details for mstar, pmsleep
ARM: mstar: Fix dts filename for 70mai midrive d08
ARM: mstar: Add dts for 70mai midrive d08
ARM: mstar: Add dts for msc313(e) based BreadBee boards
ARM: mstar: Add mercury5 series dtsis
ARM: mstar: Add infinity/infinity3 family dtsis
ARM: mstar: Add Armv7 base dtsi
ARM: mstar: Add binding details for mstar,l3bridge
ARM: mstar: Add machine for MStar/Sigmastar Armv7 SoCs
...
This commit is contained in:
Linus Torvalds
commit
d4db4e5532
|
|
@ -0,0 +1,19 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/intel,keembay.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Keem Bay platform device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Paul J. Murphy <paul.j.murphy@intel.com>
|
||||
- Daniele Alessandrelli <daniele.alessandrelli@intel.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- intel,keembay-evm
|
||||
- const: intel,keembay
|
||||
...
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/microchip,sparx5.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Microchip Sparx5 Boards Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Lars Povlsen <lars.povlsen@microchip.com>
|
||||
|
||||
description: |+
|
||||
The Microchip Sparx5 SoC is a ARMv8-based used in a family of
|
||||
gigabit TSN-capable gigabit switches.
|
||||
|
||||
The SparX-5 Ethernet switch family provides a rich set of switching
|
||||
features such as advanced TCAM-based VLAN and QoS processing
|
||||
enabling delivery of differentiated services, and security through
|
||||
TCAM-based frame processing using versatile content aware processor
|
||||
(VCAP)
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: The Sparx5 pcb125 board is a modular board,
|
||||
which has both spi-nor and eMMC storage. The modular design
|
||||
allows for connection of different network ports.
|
||||
items:
|
||||
- const: microchip,sparx5-pcb125
|
||||
- const: microchip,sparx5
|
||||
|
||||
- description: The Sparx5 pcb134 is a pizzabox form factor
|
||||
gigabit switch with 20 SFP ports. It features spi-nor and
|
||||
either spi-nand or eMMC storage (mount option).
|
||||
items:
|
||||
- const: microchip,sparx5-pcb134
|
||||
- const: microchip,sparx5
|
||||
|
||||
- description: The Sparx5 pcb135 is a pizzabox form factor
|
||||
gigabit switch with 48+4 Cu ports. It features spi-nor and
|
||||
either spi-nand or eMMC storage (mount option).
|
||||
items:
|
||||
- const: microchip,sparx5-pcb135
|
||||
- const: microchip,sparx5
|
||||
|
||||
axi@600000000:
|
||||
type: object
|
||||
description: the root node in the Sparx5 platforms must contain
|
||||
an axi bus child node. They are always at physical address
|
||||
0x600000000 in all the Sparx5 variants.
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: simple-bus
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- axi@600000000
|
||||
|
||||
...
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
# Copyright 2020 thingy.jp.
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/arm/mstar/mstar,l3bridge.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: MStar/SigmaStar Armv7 SoC l3bridge
|
||||
|
||||
maintainers:
|
||||
- Daniel Palmer <daniel@thingy.jp>
|
||||
|
||||
description: |
|
||||
MStar/SigmaStar's Armv7 SoCs have a pipeline in the interface
|
||||
between the CPU and memory. This means that before DMA capable
|
||||
devices are allowed to run the pipeline must be flushed to ensure
|
||||
everything is in memory.
|
||||
|
||||
The l3bridge region contains registers that allow such a flush
|
||||
to be triggered.
|
||||
|
||||
This node is used by the platform code to find where the registers
|
||||
are and install a barrier that triggers the required pipeline flush.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: mstar,l3bridge
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
l3bridge: l3bridge@1f204400 {
|
||||
compatible = "mstar,l3bridge";
|
||||
reg = <0x1f204400 0x200>;
|
||||
};
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/mstar/mstar.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MStar platforms device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Daniel Palmer <daniel@thingy.jp>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: infinity boards
|
||||
items:
|
||||
- enum:
|
||||
- thingyjp,breadbee-crust # thingy.jp BreadBee Crust
|
||||
- const: mstar,infinity
|
||||
|
||||
- description: infinity3 boards
|
||||
items:
|
||||
- enum:
|
||||
- thingyjp,breadbee # thingy.jp BreadBee
|
||||
- const: mstar,infinity3
|
||||
|
||||
- description: mercury5 boards
|
||||
items:
|
||||
- enum:
|
||||
- 70mai,midrived08 # 70mai midrive d08
|
||||
- const: mstar,mercury5
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Microchip Sparx5 DPLL Clock
|
||||
|
||||
maintainers:
|
||||
- Lars Povlsen <lars.povlsen@microchip.com>
|
||||
|
||||
description: |
|
||||
The Sparx5 DPLL clock controller generates and supplies clock to
|
||||
various peripherals within the SoC.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: microchip,sparx5-dpll
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Clock provider for eMMC:
|
||||
- |
|
||||
lcpll_clk: lcpll-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <2500000000>;
|
||||
};
|
||||
clks: clock-controller@61110000c {
|
||||
compatible = "microchip,sparx5-dpll";
|
||||
#clock-cells = <1>;
|
||||
clocks = <&lcpll_clk>;
|
||||
reg = <0x1110000c 0x24>;
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -38,6 +38,8 @@ properties:
|
|||
- allwinner,sun8i-h3-system-controller
|
||||
- allwinner,sun8i-v3s-system-controller
|
||||
- allwinner,sun50i-a64-system-controller
|
||||
- microchip,sparx5-cpu-syscon
|
||||
- mstar,msc313-pmsleep
|
||||
|
||||
- const: syscon
|
||||
|
||||
|
|
|
|||
|
|
@ -23,6 +23,8 @@ patternProperties:
|
|||
"^(simple-audio-card|simple-graph-card|st-plgpio|st-spics|ts),.*": true
|
||||
|
||||
# Keep list in alphabetical order.
|
||||
"^70mai,.*":
|
||||
description: 70mai Co., Ltd.
|
||||
"^abilis,.*":
|
||||
description: Abilis Systems
|
||||
"^abracon,.*":
|
||||
|
|
@ -682,6 +684,8 @@ patternProperties:
|
|||
description: Microsemi Corporation
|
||||
"^msi,.*":
|
||||
description: Micro-Star International Co. Ltd.
|
||||
"^mstar,.*":
|
||||
description: MStar Semiconductor, Inc. (acquired by MediaTek Inc.)
|
||||
"^mti,.*":
|
||||
description: Imagination Technologies Ltd. (formerly MIPS Technologies Inc.)
|
||||
"^multi-inno,.*":
|
||||
|
|
@ -986,6 +990,8 @@ patternProperties:
|
|||
description: Spreadtrum Communications Inc.
|
||||
"^sst,.*":
|
||||
description: Silicon Storage Technology, Inc.
|
||||
"^sstar,.*":
|
||||
description: Xiamen Xingchen(SigmaStar) Technology Co., Ltd. (formerly part of MStar Semiconductor, Inc.)
|
||||
"^st,.*":
|
||||
description: STMicroelectronics
|
||||
"^starry,.*":
|
||||
|
|
@ -1034,6 +1040,8 @@ patternProperties:
|
|||
description: Three Five Corp
|
||||
"^thine,.*":
|
||||
description: THine Electronics, Inc.
|
||||
"^thingyjp,.*":
|
||||
description: thingy.jp
|
||||
"^ti,.*":
|
||||
description: Texas Instruments
|
||||
"^tianma,.*":
|
||||
|
|
|
|||
28
MAINTAINERS
28
MAINTAINERS
|
|
@ -1966,6 +1966,14 @@ F: drivers/irqchip/irq-ixp4xx.c
|
|||
F: include/linux/irqchip/irq-ixp4xx.h
|
||||
F: include/linux/platform_data/timer-ixp4xx.h
|
||||
|
||||
ARM/INTEL KEEMBAY ARCHITECTURE
|
||||
M: Paul J. Murphy <paul.j.murphy@intel.com>
|
||||
M: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/arm/intel,keembay.yaml
|
||||
F: arch/arm64/boot/dts/intel/keembay-evm.dts
|
||||
F: arch/arm64/boot/dts/intel/keembay-soc.dtsi
|
||||
|
||||
ARM/INTEL RESEARCH IMOTE/STARGATE 2 MACHINE SUPPORT
|
||||
M: Jonathan Cameron <jic23@cam.ac.uk>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
|
|
@ -2123,12 +2131,32 @@ X: drivers/net/wireless/atmel/
|
|||
N: at91
|
||||
N: atmel
|
||||
|
||||
ARM/Microchip Sparx5 SoC support
|
||||
M: Lars Povlsen <lars.povlsen@microchip.com>
|
||||
M: Steen Hegelund <Steen.Hegelund@microchip.com>
|
||||
M: Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Supported
|
||||
F: arch/arm64/boot/dts/microchip/
|
||||
N: sparx5
|
||||
|
||||
ARM/MIOA701 MACHINE SUPPORT
|
||||
M: Robert Jarzmik <robert.jarzmik@free.fr>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: arch/arm/mach-pxa/mioa701.c
|
||||
|
||||
ARM/MStar/Sigmastar Armv7 SoC support
|
||||
M: Daniel Palmer <daniel@thingy.jp>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
W: http://linux-chenxing.org/
|
||||
F: Documentation/devicetree/bindings/arm/mstar/*
|
||||
F: arch/arm/boot/dts/infinity*.dtsi
|
||||
F: arch/arm/boot/dts/mercury*.dtsi
|
||||
F: arch/arm/boot/dts/mstar-v7.dtsi
|
||||
F: arch/arm/mach-mstar/
|
||||
|
||||
ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT
|
||||
M: Michael Petchkovsky <mkpetch@internode.on.net>
|
||||
S: Maintained
|
||||
|
|
|
|||
|
|
@ -668,6 +668,8 @@ source "arch/arm/mach-mmp/Kconfig"
|
|||
|
||||
source "arch/arm/mach-moxart/Kconfig"
|
||||
|
||||
source "arch/arm/mach-mstar/Kconfig"
|
||||
|
||||
source "arch/arm/mach-mv78xx0/Kconfig"
|
||||
|
||||
source "arch/arm/mach-mvebu/Kconfig"
|
||||
|
|
|
|||
|
|
@ -197,6 +197,7 @@ machine-$(CONFIG_ARCH_MXC) += imx
|
|||
machine-$(CONFIG_ARCH_MEDIATEK) += mediatek
|
||||
machine-$(CONFIG_ARCH_MILBEAUT) += milbeaut
|
||||
machine-$(CONFIG_ARCH_MXS) += mxs
|
||||
machine-$(CONFIG_ARCH_MSTARV7) += mstar
|
||||
machine-$(CONFIG_ARCH_NOMADIK) += nomadik
|
||||
machine-$(CONFIG_ARCH_NPCM) += npcm
|
||||
machine-$(CONFIG_ARCH_NSPIRE) += nspire
|
||||
|
|
|
|||
|
|
@ -1355,6 +1355,10 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
|
|||
mt8127-moose.dtb \
|
||||
mt8135-evbp1.dtb
|
||||
dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb
|
||||
dtb-$(CONFIG_ARCH_MSTARV7) += \
|
||||
infinity-msc313-breadbee_crust.dtb \
|
||||
infinity3-msc313e-breadbee.dtb \
|
||||
mercury5-ssc8336n-midrived08.dtb
|
||||
dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
|
||||
dtb-$(CONFIG_ARCH_ASPEED) += \
|
||||
aspeed-ast2500-evb.dtb \
|
||||
|
|
|
|||
|
|
@ -0,0 +1,25 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2019 thingy.jp.
|
||||
* Author: Daniel Palmer <daniel@thingy.jp>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "infinity-msc313.dtsi"
|
||||
|
||||
/ {
|
||||
model = "BreadBee Crust";
|
||||
compatible = "thingyjp,breadbee-crust", "mstar,infinity";
|
||||
|
||||
aliases {
|
||||
serial0 = &pm_uart;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&pm_uart {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (c) 2020 thingy.jp.
|
||||
* Author: Daniel Palmer <daniel@thingy.jp>
|
||||
*/
|
||||
|
||||
#include "infinity.dtsi"
|
||||
|
||||
/ {
|
||||
memory@20000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x20000000 0x4000000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (c) 2020 thingy.jp.
|
||||
* Author: Daniel Palmer <daniel@thingy.jp>
|
||||
*/
|
||||
|
||||
#include "mstar-v7.dtsi"
|
||||
|
||||
&imi {
|
||||
reg = <0xa0000000 0x16000>;
|
||||
};
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2019 thingy.jp.
|
||||
* Author: Daniel Palmer <daniel@thingy.jp>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "infinity3-msc313e.dtsi"
|
||||
|
||||
/ {
|
||||
model = "BreadBee";
|
||||
compatible = "thingyjp,breadbee", "mstar,infinity3";
|
||||
|
||||
aliases {
|
||||
serial0 = &pm_uart;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&pm_uart {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (c) 2020 thingy.jp.
|
||||
* Author: Daniel Palmer <daniel@thingy.jp>
|
||||
*/
|
||||
|
||||
#include "infinity3.dtsi"
|
||||
|
||||
/ {
|
||||
memory@20000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x20000000 0x4000000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (c) 2020 thingy.jp.
|
||||
* Author: Daniel Palmer <daniel@thingy.jp>
|
||||
*/
|
||||
|
||||
#include "infinity.dtsi"
|
||||
|
||||
&imi {
|
||||
reg = <0xa0000000 0x20000>;
|
||||
};
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (c) 2020 thingy.jp.
|
||||
* Author: Daniel Palmer <daniel@thingy.jp>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "mercury5-ssc8336n.dtsi"
|
||||
|
||||
/ {
|
||||
model = "70mai Midrive D08";
|
||||
compatible = "70mai,midrived08", "mstar,mercury5";
|
||||
|
||||
aliases {
|
||||
serial0 = &pm_uart;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&pm_uart {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (c) 2020 thingy.jp.
|
||||
* Author: Daniel Palmer <daniel@thingy.jp>
|
||||
*/
|
||||
|
||||
#include "mercury5.dtsi"
|
||||
|
||||
/ {
|
||||
memory@20000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x20000000 0x4000000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (c) 2020 thingy.jp.
|
||||
* Author: Daniel Palmer <daniel@thingy.jp>
|
||||
*/
|
||||
|
||||
#include "mstar-v7.dtsi"
|
||||
|
||||
&imi {
|
||||
reg = <0xa0000000 0x20000>;
|
||||
};
|
||||
|
|
@ -0,0 +1,107 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (c) 2020 thingy.jp.
|
||||
* Author: Daniel Palmer <daniel@thingy.jp>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
arch_timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2)
|
||||
| IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2)
|
||||
| IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2)
|
||||
| IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2)
|
||||
| IRQ_TYPE_LEVEL_LOW)>;
|
||||
/*
|
||||
* we shouldn't need this but the vendor
|
||||
* u-boot is broken
|
||||
*/
|
||||
clock-frequency = <6000000>;
|
||||
};
|
||||
|
||||
pmu: pmu {
|
||||
compatible = "arm,cortex-a7-pmu";
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&cpu0>;
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x16001000 0x16001000 0x00007000>,
|
||||
<0x1f000000 0x1f000000 0x00400000>,
|
||||
<0xa0000000 0xa0000000 0x20000>;
|
||||
|
||||
gic: interrupt-controller@16001000 {
|
||||
compatible = "arm,cortex-a7-gic";
|
||||
reg = <0x16001000 0x1000>,
|
||||
<0x16002000 0x2000>,
|
||||
<0x16004000 0x2000>,
|
||||
<0x16006000 0x2000>;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2)
|
||||
| IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
riu: bus@1f000000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0x1f000000 0x00400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x1f000000 0x00400000>;
|
||||
|
||||
pmsleep: syscon@1c00 {
|
||||
compatible = "mstar,msc313-pmsleep", "syscon";
|
||||
reg = <0x1c00 0x100>;
|
||||
};
|
||||
|
||||
reboot {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&pmsleep>;
|
||||
offset = <0xb8>;
|
||||
mask = <0x79>;
|
||||
};
|
||||
|
||||
l3bridge: l3bridge@204400 {
|
||||
compatible = "mstar,l3bridge";
|
||||
reg = <0x204400 0x200>;
|
||||
};
|
||||
|
||||
pm_uart: uart@221000 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x221000 0x100>;
|
||||
reg-shift = <3>;
|
||||
clock-frequency = <172000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
imi: sram@a0000000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0xa0000000 0x10000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
menuconfig ARCH_MSTARV7
|
||||
bool "MStar/Sigmastar Armv7 SoC Support"
|
||||
depends on ARCH_MULTI_V7
|
||||
select ARM_GIC
|
||||
select ARM_HEAVY_MB
|
||||
help
|
||||
Support for newer MStar/Sigmastar SoC families that are
|
||||
based on Armv7 cores like the Cortex A7 and share the same
|
||||
basic hardware like the infinity and mercury series.
|
||||
|
||||
if ARCH_MSTARV7
|
||||
|
||||
config MACH_INFINITY
|
||||
bool "MStar/Sigmastar infinity SoC support"
|
||||
default ARCH_MSTARV7
|
||||
help
|
||||
Support for MStar/Sigmastar infinity IP camera SoCs.
|
||||
|
||||
config MACH_MERCURY
|
||||
bool "MStar/Sigmastar mercury SoC support"
|
||||
default ARCH_MSTARV7
|
||||
help
|
||||
Support for MStar/Sigmastar mercury dash camera SoCs.
|
||||
Note that older Mercury2 SoCs are ARM9 based and not supported.
|
||||
|
||||
endif
|
||||
|
|
@ -0,0 +1 @@
|
|||
obj-$(CONFIG_ARCH_MSTARV7) += mstarv7.o
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree support for MStar/Sigmastar Armv7 SoCs
|
||||
*
|
||||
* Copyright (c) 2020 thingy.jp
|
||||
* Author: Daniel Palmer <daniel@thingy.jp>
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
/*
|
||||
* In the u-boot code the area these registers are in is
|
||||
* called "L3 bridge" and there are register descriptions
|
||||
* for something in the same area called "AXI".
|
||||
*
|
||||
* It's not exactly known what this is but the vendor code
|
||||
* for both u-boot and linux share calls to "flush the miu pipe".
|
||||
* This seems to be to force pending CPU writes to memory so that
|
||||
* the state is right before DMA capable devices try to read
|
||||
* descriptors and data the CPU has prepared. Without doing this
|
||||
* ethernet doesn't work reliably for example.
|
||||
*/
|
||||
|
||||
#define MSTARV7_L3BRIDGE_FLUSH 0x14
|
||||
#define MSTARV7_L3BRIDGE_STATUS 0x40
|
||||
#define MSTARV7_L3BRIDGE_FLUSH_TRIGGER BIT(0)
|
||||
#define MSTARV7_L3BRIDGE_STATUS_DONE BIT(12)
|
||||
|
||||
static void __iomem *l3bridge;
|
||||
|
||||
static const char * const mstarv7_board_dt_compat[] __initconst = {
|
||||
"mstar,infinity",
|
||||
"mstar,infinity3",
|
||||
"mstar,mercury5",
|
||||
NULL,
|
||||
};
|
||||
|
||||
/*
|
||||
* This may need locking to deal with situations where an interrupt
|
||||
* happens while we are in here and mb() gets called by the interrupt handler.
|
||||
*
|
||||
* The vendor code did have a spin lock but it doesn't seem to be needed and
|
||||
* removing it hasn't caused any side effects so far.
|
||||
*
|
||||
* [writel|readl]_relaxed have to be used here because otherwise
|
||||
* we'd end up right back in here.
|
||||
*/
|
||||
static void mstarv7_mb(void)
|
||||
{
|
||||
/* toggle the flush miu pipe fire bit */
|
||||
writel_relaxed(0, l3bridge + MSTARV7_L3BRIDGE_FLUSH);
|
||||
writel_relaxed(MSTARV7_L3BRIDGE_FLUSH_TRIGGER, l3bridge
|
||||
+ MSTARV7_L3BRIDGE_FLUSH);
|
||||
while (!(readl_relaxed(l3bridge + MSTARV7_L3BRIDGE_STATUS)
|
||||
& MSTARV7_L3BRIDGE_STATUS_DONE)) {
|
||||
/* wait for flush to complete */
|
||||
}
|
||||
}
|
||||
|
||||
static void __init mstarv7_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "mstar,l3bridge");
|
||||
l3bridge = of_iomap(np, 0);
|
||||
if (l3bridge)
|
||||
soc_mb = mstarv7_mb;
|
||||
else
|
||||
pr_warn("Failed to install memory barrier, DMA will be broken!\n");
|
||||
}
|
||||
|
||||
DT_MACHINE_START(MSTARV7_DT, "MStar/Sigmastar Armv7 (Device Tree)")
|
||||
.dt_compat = mstarv7_board_dt_compat,
|
||||
.init_machine = mstarv7_init,
|
||||
MACHINE_END
|
||||
|
|
@ -89,6 +89,20 @@ config ARCH_EXYNOS
|
|||
help
|
||||
This enables support for ARMv8 based Samsung Exynos SoC family.
|
||||
|
||||
config ARCH_SPARX5
|
||||
bool "ARMv8 based Microchip Sparx5 SoC family"
|
||||
select PINCTRL
|
||||
select DW_APB_TIMER_OF
|
||||
help
|
||||
This enables support for the Microchip Sparx5 ARMv8-based
|
||||
SoC family of TSN-capable gigabit switches.
|
||||
|
||||
The SparX-5 Ethernet switch family provides a rich set of
|
||||
switching features such as advanced TCAM-based VLAN and QoS
|
||||
processing enabling delivery of differentiated services, and
|
||||
security through TCAM-based frame processing using versatile
|
||||
content aware processor (VCAP).
|
||||
|
||||
config ARCH_K3
|
||||
bool "Texas Instruments Inc. K3 multicore SoC architecture"
|
||||
select PM_GENERIC_DOMAINS if PM
|
||||
|
|
@ -122,6 +136,11 @@ config ARCH_HISI
|
|||
help
|
||||
This enables support for Hisilicon ARMv8 SoC family
|
||||
|
||||
config ARCH_KEEMBAY
|
||||
bool "Keem Bay SoC"
|
||||
help
|
||||
This enables support for Intel Movidius SoC code-named Keem Bay.
|
||||
|
||||
config ARCH_MEDIATEK
|
||||
bool "MediaTek SoC Family"
|
||||
select ARM_GIC
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@ subdir-y += intel
|
|||
subdir-y += lg
|
||||
subdir-y += marvell
|
||||
subdir-y += mediatek
|
||||
subdir-y += microchip
|
||||
subdir-y += nvidia
|
||||
subdir-y += qcom
|
||||
subdir-y += realtek
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
dtb-$(CONFIG_ARCH_AGILEX) += socfpga_agilex_socdk.dtb \
|
||||
socfpga_agilex_socdk_nand.dtb
|
||||
dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
|
||||
|
|
|
|||
|
|
@ -0,0 +1,37 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) 2020, Intel Corporation
|
||||
*
|
||||
* Device tree describing Keem Bay EVM board.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "keembay-soc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Keem Bay EVM";
|
||||
compatible = "intel,keembay-evm", "intel,keembay";
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
serial0 = &uart3;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* 2GB of DDR memory. */
|
||||
reg = <0x0 0x80000000 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,123 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) 2020, Intel Corporation.
|
||||
*
|
||||
* Device tree describing Keem Bay SoC.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a53";
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "arm,cortex-a53";
|
||||
device_type = "cpu";
|
||||
reg = <0x1>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu@2 {
|
||||
compatible = "arm,cortex-a53";
|
||||
device_type = "cpu";
|
||||
reg = <0x2>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu@3 {
|
||||
compatible = "arm,cortex-a53";
|
||||
device_type = "cpu";
|
||||
reg = <0x3>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@20500000 {
|
||||
compatible = "arm,gic-v3";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0x0 0x20500000 0x0 0x20000>, /* GICD */
|
||||
<0x0 0x20580000 0x0 0x80000>; /* GICR */
|
||||
/* VGIC maintenance interrupt */
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
/* Secure, non-secure, virtual, and hypervisor */
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupts = <GIC_PPI 0x7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
uart0: serial@20150000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x20150000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <24000000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@20160000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x20160000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <24000000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@20170000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x20170000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <24000000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@20180000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x20180000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <24000000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb125.dtb
|
||||
dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb134.dtb sparx5_pcb134_emmc.dtb
|
||||
dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb135.dtb sparx5_pcb135_emmc.dtb
|
||||
|
|
@ -0,0 +1,213 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
compatible = "microchip,sparx5";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&cpu0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&cpu1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a53";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,cortex-a53";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x1>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
arm-pmu {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&cpu0>, <&cpu1>;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
lcpll_clk: lcpll-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <2500000000>;
|
||||
};
|
||||
|
||||
clks: clock-controller@61110000c {
|
||||
compatible = "microchip,sparx5-dpll";
|
||||
#clock-cells = <1>;
|
||||
clocks = <&lcpll_clk>;
|
||||
reg = <0x6 0x1110000c 0x24>;
|
||||
};
|
||||
|
||||
ahb_clk: ahb-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <250000000>;
|
||||
};
|
||||
|
||||
sys_clk: sys-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <625000000>;
|
||||
};
|
||||
|
||||
axi: axi@600000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
gic: interrupt-controller@600300000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-controller;
|
||||
reg = <0x6 0x00300000 0x10000>, /* GIC Dist */
|
||||
<0x6 0x00340000 0xc0000>, /* GICR */
|
||||
<0x6 0x00200000 0x2000>, /* GICC */
|
||||
<0x6 0x00210000 0x2000>, /* GICV */
|
||||
<0x6 0x00220000 0x2000>; /* GICH */
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
uart0: serial@600100000 {
|
||||
pinctrl-0 = <&uart_pins>;
|
||||
pinctrl-names = "default";
|
||||
compatible = "ns16550a";
|
||||
reg = <0x6 0x00100000 0x20>;
|
||||
clocks = <&ahb_clk>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@600102000 {
|
||||
pinctrl-0 = <&uart2_pins>;
|
||||
pinctrl-names = "default";
|
||||
compatible = "ns16550a";
|
||||
reg = <0x6 0x00102000 0x20>;
|
||||
clocks = <&ahb_clk>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer1: timer@600105000 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0x6 0x00105000 0x1000>;
|
||||
clocks = <&ahb_clk>;
|
||||
clock-names = "timer";
|
||||
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpio: pinctrl@6110101e0 {
|
||||
compatible = "microchip,sparx5-pinctrl";
|
||||
reg = <0x6 0x110101e0 0x90>, <0x6 0x10508010 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&gpio 0 0 64>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
uart_pins: uart-pins {
|
||||
pins = "GPIO_10", "GPIO_11";
|
||||
function = "uart";
|
||||
};
|
||||
|
||||
uart2_pins: uart2-pins {
|
||||
pins = "GPIO_26", "GPIO_27";
|
||||
function = "uart2";
|
||||
};
|
||||
|
||||
i2c_pins: i2c-pins {
|
||||
pins = "GPIO_14", "GPIO_15";
|
||||
function = "twi";
|
||||
};
|
||||
|
||||
i2c2_pins: i2c2-pins {
|
||||
pins = "GPIO_28", "GPIO_29";
|
||||
function = "twi2";
|
||||
};
|
||||
};
|
||||
|
||||
i2c0: i2c@600101000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
status = "disabled";
|
||||
pinctrl-0 = <&i2c_pins>;
|
||||
pinctrl-names = "default";
|
||||
reg = <0x6 0x00101000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-sda-hold-time-ns = <300>;
|
||||
clock-frequency = <100000>;
|
||||
clocks = <&ahb_clk>;
|
||||
};
|
||||
|
||||
i2c1: i2c@600103000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
status = "disabled";
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
pinctrl-names = "default";
|
||||
reg = <0x6 0x00103000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-sda-hold-time-ns = <300>;
|
||||
clock-frequency = <100000>;
|
||||
clocks = <&ahb_clk>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "sparx5_pcb_common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Sparx5 PCB125 Reference Board";
|
||||
compatible = "microchip,sparx5-pcb125", "microchip,sparx5";
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x00000000 0x10000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "sparx5_pcb134_board.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Sparx5 PCB134 Reference Board (NAND)";
|
||||
compatible = "microchip,sparx5-pcb134", "microchip,sparx5";
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x00000000 0x10000000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,252 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "sparx5_pcb_common.dtsi"
|
||||
|
||||
/{
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c100 = &i2c100;
|
||||
i2c101 = &i2c101;
|
||||
i2c102 = &i2c102;
|
||||
i2c103 = &i2c103;
|
||||
i2c104 = &i2c104;
|
||||
i2c105 = &i2c105;
|
||||
i2c106 = &i2c106;
|
||||
i2c107 = &i2c107;
|
||||
i2c108 = &i2c108;
|
||||
i2c109 = &i2c109;
|
||||
i2c110 = &i2c110;
|
||||
i2c111 = &i2c111;
|
||||
i2c112 = &i2c112;
|
||||
i2c113 = &i2c113;
|
||||
i2c114 = &i2c114;
|
||||
i2c115 = &i2c115;
|
||||
i2c116 = &i2c116;
|
||||
i2c117 = &i2c117;
|
||||
i2c118 = &i2c118;
|
||||
i2c119 = &i2c119;
|
||||
};
|
||||
|
||||
gpio-restart {
|
||||
compatible = "gpio-restart";
|
||||
gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
|
||||
priority = <200>;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
i2cmux_pins_i: i2cmux-pins-i {
|
||||
pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19",
|
||||
"GPIO_20", "GPIO_22", "GPIO_36", "GPIO_35",
|
||||
"GPIO_50", "GPIO_51", "GPIO_56", "GPIO_57";
|
||||
function = "twi_scl_m";
|
||||
output-low;
|
||||
};
|
||||
i2cmux_0: i2cmux-0 {
|
||||
pins = "GPIO_16";
|
||||
function = "twi_scl_m";
|
||||
output-high;
|
||||
};
|
||||
i2cmux_1: i2cmux-1 {
|
||||
pins = "GPIO_17";
|
||||
function = "twi_scl_m";
|
||||
output-high;
|
||||
};
|
||||
i2cmux_2: i2cmux-2 {
|
||||
pins = "GPIO_18";
|
||||
function = "twi_scl_m";
|
||||
output-high;
|
||||
};
|
||||
i2cmux_3: i2cmux-3 {
|
||||
pins = "GPIO_19";
|
||||
function = "twi_scl_m";
|
||||
output-high;
|
||||
};
|
||||
i2cmux_4: i2cmux-4 {
|
||||
pins = "GPIO_20";
|
||||
function = "twi_scl_m";
|
||||
output-high;
|
||||
};
|
||||
i2cmux_5: i2cmux-5 {
|
||||
pins = "GPIO_22";
|
||||
function = "twi_scl_m";
|
||||
output-high;
|
||||
};
|
||||
i2cmux_6: i2cmux-6 {
|
||||
pins = "GPIO_36";
|
||||
function = "twi_scl_m";
|
||||
output-high;
|
||||
};
|
||||
i2cmux_7: i2cmux-7 {
|
||||
pins = "GPIO_35";
|
||||
function = "twi_scl_m";
|
||||
output-high;
|
||||
};
|
||||
i2cmux_8: i2cmux-8 {
|
||||
pins = "GPIO_50";
|
||||
function = "twi_scl_m";
|
||||
output-high;
|
||||
};
|
||||
i2cmux_9: i2cmux-9 {
|
||||
pins = "GPIO_51";
|
||||
function = "twi_scl_m";
|
||||
output-high;
|
||||
};
|
||||
i2cmux_10: i2cmux-10 {
|
||||
pins = "GPIO_56";
|
||||
function = "twi_scl_m";
|
||||
output-high;
|
||||
};
|
||||
i2cmux_11: i2cmux-11 {
|
||||
pins = "GPIO_57";
|
||||
function = "twi_scl_m";
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
&axi {
|
||||
i2c0_imux: i2c0-imux@0 {
|
||||
compatible = "i2c-mux-pinctrl";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
i2c-parent = <&i2c0>;
|
||||
};
|
||||
i2c0_emux: i2c0-emux@0 {
|
||||
compatible = "i2c-mux-gpio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
i2c-parent = <&i2c0>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0_imux {
|
||||
pinctrl-names =
|
||||
"i2c100", "i2c101", "i2c102", "i2c103",
|
||||
"i2c104", "i2c105", "i2c106", "i2c107",
|
||||
"i2c108", "i2c109", "i2c110", "i2c111", "idle";
|
||||
pinctrl-0 = <&i2cmux_0>;
|
||||
pinctrl-1 = <&i2cmux_1>;
|
||||
pinctrl-2 = <&i2cmux_2>;
|
||||
pinctrl-3 = <&i2cmux_3>;
|
||||
pinctrl-4 = <&i2cmux_4>;
|
||||
pinctrl-5 = <&i2cmux_5>;
|
||||
pinctrl-6 = <&i2cmux_6>;
|
||||
pinctrl-7 = <&i2cmux_7>;
|
||||
pinctrl-8 = <&i2cmux_8>;
|
||||
pinctrl-9 = <&i2cmux_9>;
|
||||
pinctrl-10 = <&i2cmux_10>;
|
||||
pinctrl-11 = <&i2cmux_11>;
|
||||
pinctrl-12 = <&i2cmux_pins_i>;
|
||||
i2c100: i2c_sfp1 {
|
||||
reg = <0x0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
i2c101: i2c_sfp2 {
|
||||
reg = <0x1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
i2c102: i2c_sfp3 {
|
||||
reg = <0x2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
i2c103: i2c_sfp4 {
|
||||
reg = <0x3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
i2c104: i2c_sfp5 {
|
||||
reg = <0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
i2c105: i2c_sfp6 {
|
||||
reg = <0x5>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
i2c106: i2c_sfp7 {
|
||||
reg = <0x6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
i2c107: i2c_sfp8 {
|
||||
reg = <0x7>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
i2c108: i2c_sfp9 {
|
||||
reg = <0x8>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
i2c109: i2c_sfp10 {
|
||||
reg = <0x9>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
i2c110: i2c_sfp11 {
|
||||
reg = <0xa>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
i2c111: i2c_sfp12 {
|
||||
reg = <0xb>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0_emux {
|
||||
mux-gpios = <&gpio 55 GPIO_ACTIVE_HIGH
|
||||
&gpio 60 GPIO_ACTIVE_HIGH
|
||||
&gpio 61 GPIO_ACTIVE_HIGH
|
||||
&gpio 54 GPIO_ACTIVE_HIGH>;
|
||||
idle-state = <0x8>;
|
||||
i2c112: i2c_sfp13 {
|
||||
reg = <0x0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
i2c113: i2c_sfp14 {
|
||||
reg = <0x1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
i2c114: i2c_sfp15 {
|
||||
reg = <0x2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
i2c115: i2c_sfp16 {
|
||||
reg = <0x3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
i2c116: i2c_sfp17 {
|
||||
reg = <0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
i2c117: i2c_sfp18 {
|
||||
reg = <0x5>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
i2c118: i2c_sfp19 {
|
||||
reg = <0x6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
i2c119: i2c_sfp20 {
|
||||
reg = <0x7>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "sparx5_pcb134_board.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Sparx5 PCB134 Reference Board (eMMC enabled)";
|
||||
compatible = "microchip,sparx5-pcb134", "microchip,sparx5";
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x00000000 0x10000000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "sparx5_pcb135_board.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Sparx5 PCB135 Reference Board (NAND)";
|
||||
compatible = "microchip,sparx5-pcb135", "microchip,sparx5";
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x00000000 0x10000000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,92 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "sparx5_pcb_common.dtsi"
|
||||
|
||||
/{
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c152 = &i2c152;
|
||||
i2c153 = &i2c153;
|
||||
i2c154 = &i2c154;
|
||||
i2c155 = &i2c155;
|
||||
};
|
||||
|
||||
gpio-restart {
|
||||
compatible = "gpio-restart";
|
||||
gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
|
||||
priority = <200>;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
i2cmux_pins_i: i2cmux-pins-i {
|
||||
pins = "GPIO_35", "GPIO_36",
|
||||
"GPIO_50", "GPIO_51";
|
||||
function = "twi_scl_m";
|
||||
output-low;
|
||||
};
|
||||
i2cmux_s29: i2cmux-0 {
|
||||
pins = "GPIO_35";
|
||||
function = "twi_scl_m";
|
||||
output-high;
|
||||
};
|
||||
i2cmux_s30: i2cmux-1 {
|
||||
pins = "GPIO_36";
|
||||
function = "twi_scl_m";
|
||||
output-high;
|
||||
};
|
||||
i2cmux_s31: i2cmux-2 {
|
||||
pins = "GPIO_50";
|
||||
function = "twi_scl_m";
|
||||
output-high;
|
||||
};
|
||||
i2cmux_s32: i2cmux-3 {
|
||||
pins = "GPIO_51";
|
||||
function = "twi_scl_m";
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
&axi {
|
||||
i2c0_imux: i2c0-imux@0 {
|
||||
compatible = "i2c-mux-pinctrl";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
i2c-parent = <&i2c0>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0_imux {
|
||||
pinctrl-names =
|
||||
"i2c152", "i2c153", "i2c154", "i2c155",
|
||||
"idle";
|
||||
pinctrl-0 = <&i2cmux_s29>;
|
||||
pinctrl-1 = <&i2cmux_s30>;
|
||||
pinctrl-2 = <&i2cmux_s31>;
|
||||
pinctrl-3 = <&i2cmux_s32>;
|
||||
pinctrl-4 = <&i2cmux_pins_i>;
|
||||
i2c152: i2c_sfp1 {
|
||||
reg = <0x0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
i2c153: i2c_sfp2 {
|
||||
reg = <0x1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
i2c154: i2c_sfp3 {
|
||||
reg = <0x2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
i2c155: i2c_sfp4 {
|
||||
reg = <0x3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "sparx5_pcb135_board.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Sparx5 PCB135 Reference Board (eMMC enabled)";
|
||||
compatible = "microchip,sparx5-pcb135", "microchip,sparx5";
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x00000000 0x10000000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "sparx5.dtsi"
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2019 Microchip Inc.
|
||||
*
|
||||
* Author: Lars Povlsen <lars.povlsen@microchip.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_SPARX5_H
|
||||
#define _DT_BINDINGS_CLK_SPARX5_H
|
||||
|
||||
#define CLK_ID_CORE 0
|
||||
#define CLK_ID_DDR 1
|
||||
#define CLK_ID_CPU2 2
|
||||
#define CLK_ID_ARM2 3
|
||||
#define CLK_ID_AUX1 4
|
||||
#define CLK_ID_AUX2 5
|
||||
#define CLK_ID_AUX3 6
|
||||
#define CLK_ID_AUX4 7
|
||||
#define CLK_ID_SYNCE 8
|
||||
|
||||
#define N_CLOCKS 9
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue