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x86, apic: clean up ->vector_allocation_domain() 

- separate the namespace

 - remove macros

 - move the default vector-allocation-domain to mach-generic

 - fix whitespace damage

Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Ingo Molnar 2009-01-28 06:50:47 +01:00
parent 2e867b17cc
commit e2d40b1878
8 changed files with 24 additions and 24 deletions
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13
arch/x86/include/asm/mach-default/mach_apic.h
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@ -23,7 +23,6 @@ static inline const struct cpumask *default_target_cpus(void)
#define cpu_mask_to_apicid (apic->cpu_mask_to_apicid)
#define cpu_mask_to_apicid_and (apic->cpu_mask_to_apicid_and)
#define phys_pkg_id (apic->phys_pkg_id)
#define vector_allocation_domain (apic->vector_allocation_domain)
#define read_apic_id() (GET_APIC_ID(apic_read(APIC_ID)))
#define send_IPI_self (apic->send_IPI_self)
#define wakeup_secondary_cpu (apic->wakeup_cpu)
@ -89,18 +88,6 @@ static inline int apicid_to_node(int logical_apicid)
#endif
}
static inline void vector_allocation_domain(int cpu, struct cpumask *retmask)
{
/* Careful. Some cpus do not strictly honor the set of cpus
* specified in the interrupt destination when using lowest
* priority interrupt delivery mode.
*
* In particular there was a hyperthreading cpu observed to
* deliver interrupts to the wrong hyperthread when only one
* hyperthread was specified in the interrupt desitination.
*/
*retmask = (cpumask_t) { { [0] = APIC_ALL_CPUS } };
}
#endif
static inline unsigned long default_check_apicid_used(physid_mask_t bitmap, int apicid)

1
arch/x86/include/asm/mach-generic/mach_apic.h
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@ -15,7 +15,6 @@
#define check_phys_apicid_present (apic->check_phys_apicid_present)
#define cpu_mask_to_apicid (apic->cpu_mask_to_apicid)
#define cpu_mask_to_apicid_and (apic->cpu_mask_to_apicid_and)
#define vector_allocation_domain (apic->vector_allocation_domain)
#define enable_apic_mode (apic->enable_apic_mode)
#define phys_pkg_id (apic->phys_pkg_id)
#define wakeup_secondary_cpu (apic->wakeup_cpu)

2
arch/x86/kernel/io_apic.c
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@ -1316,7 +1316,7 @@ __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
int new_cpu;
int vector, offset;
vector_allocation_domain(cpu, tmp_mask);
apic->vector_allocation_domain(cpu, tmp_mask);
vector = current_vector;
offset = current_offset;

4
arch/x86/mach-generic/bigsmp.c
View File

@ -42,7 +42,7 @@ static const struct dmi_system_id bigsmp_dmi_table[] = {
{ }
};
static void vector_allocation_domain(int cpu, cpumask_t *retmask)
static void bigsmp_vector_allocation_domain(int cpu, cpumask_t *retmask)
{
cpus_clear(*retmask);
cpu_set(cpu, *retmask);
@ -74,7 +74,7 @@ struct genapic apic_bigsmp = {
.check_apicid_used = bigsmp_check_apicid_used,
.check_apicid_present = bigsmp_check_apicid_present,
.vector_allocation_domain = vector_allocation_domain,
.vector_allocation_domain = bigsmp_vector_allocation_domain,
.init_apic_ldr = init_apic_ldr,
.ioapic_phys_id_map = ioapic_phys_id_map,

16
arch/x86/mach-generic/default.c
View File

@ -18,6 +18,20 @@
#include <asm/mach-default/mach_mpparse.h>
#include <asm/mach-default/mach_wakecpu.h>
static void default_vector_allocation_domain(int cpu, struct cpumask *retmask)
{
/*
* Careful. Some cpus do not strictly honor the set of cpus
* specified in the interrupt destination when using lowest
* priority interrupt delivery mode.
*
* In particular there was a hyperthreading cpu observed to
* deliver interrupts to the wrong hyperthread when only one
* hyperthread was specified in the interrupt desitination.
*/
*retmask = (cpumask_t) { { [0] = APIC_ALL_CPUS } };
}
/* should be called last. */
static int probe_default(void)
{
@ -41,7 +55,7 @@ struct genapic apic_default = {
.check_apicid_used = default_check_apicid_used,
.check_apicid_present = default_check_apicid_present,
.vector_allocation_domain = vector_allocation_domain,
.vector_allocation_domain = default_vector_allocation_domain,
.init_apic_ldr = init_apic_ldr,
.ioapic_phys_id_map = ioapic_phys_id_map,

4
arch/x86/mach-generic/es7000.c
View File

@ -86,7 +86,7 @@ static int __init es7000_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
}
#endif
static void vector_allocation_domain(int cpu, cpumask_t *retmask)
static void es7000_vector_allocation_domain(int cpu, cpumask_t *retmask)
{
/* Careful. Some cpus do not strictly honor the set of cpus
* specified in the interrupt destination when using lowest
@ -116,7 +116,7 @@ struct genapic apic_es7000 = {
.check_apicid_used = es7000_check_apicid_used,
.check_apicid_present = es7000_check_apicid_present,
.vector_allocation_domain = vector_allocation_domain,
.vector_allocation_domain = es7000_vector_allocation_domain,
.init_apic_ldr = init_apic_ldr,
.ioapic_phys_id_map = ioapic_phys_id_map,

4
arch/x86/mach-generic/numaq.c
View File

@ -31,7 +31,7 @@ static int probe_numaq(void)
return found_numaq;
}
static void vector_allocation_domain(int cpu, cpumask_t *retmask)
static void numaq_vector_allocation_domain(int cpu, cpumask_t *retmask)
{
/* Careful. Some cpus do not strictly honor the set of cpus
* specified in the interrupt destination when using lowest
@ -61,7 +61,7 @@ struct genapic apic_numaq = {
.check_apicid_used = numaq_check_apicid_used,
.check_apicid_present = numaq_check_apicid_present,
.vector_allocation_domain = vector_allocation_domain,
.vector_allocation_domain = numaq_vector_allocation_domain,
.init_apic_ldr = init_apic_ldr,
.ioapic_phys_id_map = ioapic_phys_id_map,

4
arch/x86/mach-generic/summit.c
View File

@ -24,7 +24,7 @@ static int probe_summit(void)
return 0;
}
static void vector_allocation_domain(int cpu, cpumask_t *retmask)
static void summit_vector_allocation_domain(int cpu, cpumask_t *retmask)
{
/* Careful. Some cpus do not strictly honor the set of cpus
* specified in the interrupt destination when using lowest
@ -54,7 +54,7 @@ struct genapic apic_summit = {
.check_apicid_used = summit_check_apicid_used,
.check_apicid_present = summit_check_apicid_present,
.vector_allocation_domain = vector_allocation_domain,
.vector_allocation_domain = summit_vector_allocation_domain,
.init_apic_ldr = init_apic_ldr,
.ioapic_phys_id_map = ioapic_phys_id_map,