mirror of https://gitee.com/openkylin/linux.git
clk: qcom: clk-alpha-pll: Refactor trion PLL
Remove duplicate function for calculating the round rate of PLL and also update the trion pll ops to use the common function. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lkml.kernel.org/r/20200224045003.3783838-3-vkoul@kernel.org Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -845,33 +845,12 @@ static unsigned long
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clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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{
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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struct regmap *regmap = pll->clkr.regmap;
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u32 l, frac;
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u64 prate = parent_rate;
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u32 l, frac, alpha_width = pll_alpha_width(pll);
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regmap_read(regmap, PLL_L_VAL(pll), &l);
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regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac);
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regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
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regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
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return alpha_pll_calc_rate(prate, l, frac, ALPHA_REG_16BIT_WIDTH);
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}
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static long clk_trion_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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unsigned long min_freq, max_freq;
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u32 l;
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u64 a;
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rate = alpha_pll_round_rate(rate, *prate,
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&l, &a, ALPHA_REG_16BIT_WIDTH);
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if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
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return rate;
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min_freq = pll->vco_table[0].min_freq;
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max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
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return clamp(rate, min_freq, max_freq);
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return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
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}
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const struct clk_ops clk_alpha_pll_fixed_ops = {
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@ -917,7 +896,7 @@ const struct clk_ops clk_trion_fixed_pll_ops = {
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.disable = clk_trion_pll_disable,
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.is_enabled = clk_trion_pll_is_enabled,
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.recalc_rate = clk_trion_pll_recalc_rate,
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.round_rate = clk_trion_pll_round_rate,
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.round_rate = clk_alpha_pll_round_rate,
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};
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EXPORT_SYMBOL_GPL(clk_trion_fixed_pll_ops);
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@ -1173,7 +1152,7 @@ static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
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* Due to limited number of bits for fractional rate programming, the
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* rounded up rate could be marginally higher than the requested rate.
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*/
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if (rrate > max || rrate < rate) {
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if (rrate > (rate + PLL_RATE_MARGIN) || rrate < rate) {
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pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n",
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clk_hw_get_name(hw), rrate, rate, max);
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return -EINVAL;
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