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dt-bindings: i2c: stm32: Migrate i2c-stm32 documentation to yaml
The document was migrated to Yaml format and renamed st,stm32-i2c.yaml Signed-off-by: Alain Volmat <alain.volmat@st.com> Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Alain Volmat
Rob Herring
parent
1e25c5f533
commit
f33dabf59d
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* I2C controller embedded in STMicroelectronics STM32 I2C platform
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Required properties:
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- compatible: Must be one of the following
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- "st,stm32f4-i2c"
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- "st,stm32f7-i2c"
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- reg: Offset and length of the register set for the device
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- interrupts: Must contain the interrupt id for I2C event and then the
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interrupt id for I2C error.
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- resets: Must contain the phandle to the reset controller.
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- clocks: Must contain the input clock of the I2C instance.
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- A pinctrl state named "default" must be defined to set pins in mode of
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operation for I2C transfer
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- #address-cells = <1>;
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- #size-cells = <0>;
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Optional properties:
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- clock-frequency: Desired I2C bus clock frequency in Hz. If not specified,
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the default 100 kHz frequency will be used.
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For STM32F4 SoC Standard-mode and Fast-mode are supported, possible values are
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100000 and 400000.
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For STM32F7, STM32H7 and STM32MP1 SoCs, Standard-mode, Fast-mode and Fast-mode
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Plus are supported, possible values are 100000, 400000 and 1000000.
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- dmas: List of phandles to rx and tx DMA channels. Refer to stm32-dma.txt.
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- dma-names: List of dma names. Valid names are: "rx" and "tx".
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- i2c-scl-rising-time-ns: I2C SCL Rising time for the board (default: 25)
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For STM32F7, STM32H7 and STM32MP1 only.
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- i2c-scl-falling-time-ns: I2C SCL Falling time for the board (default: 10)
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For STM32F7, STM32H7 and STM32MP1 only.
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I2C Timings are derived from these 2 values
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- st,syscfg-fmp: Use to set Fast Mode Plus bit within SYSCFG when Fast Mode
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Plus speed is selected by slave.
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1st cell: phandle to syscfg
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2nd cell: register offset within SYSCFG
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3rd cell: register bitmask for FMP bit
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For STM32F7, STM32H7 and STM32MP1 only.
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Example:
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i2c@40005400 {
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compatible = "st,stm32f4-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005400 0x400>;
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interrupts = <31>,
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<32>;
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resets = <&rcc 277>;
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clocks = <&rcc 0 149>;
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pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>;
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pinctrl-names = "default";
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};
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i2c@40005400 {
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compatible = "st,stm32f7-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005400 0x400>;
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interrupts = <31>,
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<32>;
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resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
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clocks = <&rcc 1 CLK_I2C1>;
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pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>;
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pinctrl-names = "default";
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st,syscfg-fmp = <&syscfg 0x4 0x1>;
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};
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@ -0,0 +1,141 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/i2c/st,stm32-i2c.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: I2C controller embedded in STMicroelectronics STM32 I2C platform
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maintainers:
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- Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
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allOf:
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- $ref: /schemas/i2c/i2c-controller.yaml#
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- if:
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properties:
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compatible:
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contains:
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enum:
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- st,stm32f7-i2c
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then:
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properties:
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i2c-scl-rising-time-ns:
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default: 25
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i2c-scl-falling-time-ns:
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default: 10
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st,syscfg-fmp:
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description: Use to set Fast Mode Plus bit within SYSCFG when
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Fast Mode Plus speed is selected by slave.
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Format is phandle to syscfg / register offset within
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syscfg / register bitmask for FMP bit.
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allOf:
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- $ref: "/schemas/types.yaml#/definitions/phandle-array"
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- items:
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minItems: 3
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maxItems: 3
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- if:
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properties:
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compatible:
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contains:
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enum:
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- st,stm32f4-i2c
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then:
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properties:
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clock-frequency:
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enum: [100000, 400000]
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properties:
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compatible:
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enum:
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- st,stm32f4-i2c
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- st,stm32f7-i2c
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reg:
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maxItems: 1
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interrupts:
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items:
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- description: interrupt ID for I2C event
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- description: interrupt ID for I2C error
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resets:
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maxItems: 1
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clocks:
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maxItems: 1
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dmas:
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items:
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- description: RX DMA Channel phandle
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- description: TX DMA Channel phandle
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dma-names:
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items:
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- const: rx
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- const: tx
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clock-frequency:
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description: Desired I2C bus clock frequency in Hz. If not specified,
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the default 100 kHz frequency will be used.
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For STM32F7, STM32H7 and STM32MP1 SoCs, Standard-mode,
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Fast-mode and Fast-mode Plus are supported, possible
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values are 100000, 400000 and 1000000.
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default: 100000
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enum: [100000, 400000, 1000000]
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required:
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- compatible
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- reg
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- interrupts
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- resets
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- clocks
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examples:
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- |
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#include <dt-bindings/mfd/stm32f7-rcc.h>
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#include <dt-bindings/clock/stm32fx-clock.h>
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//Example 1 (with st,stm32f4-i2c compatible)
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i2c@40005400 {
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compatible = "st,stm32f4-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005400 0x400>;
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interrupts = <31>,
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<32>;
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resets = <&rcc 277>;
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clocks = <&rcc 0 149>;
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};
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//Example 2 (with st,stm32f7-i2c compatible)
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i2c@40005800 {
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compatible = "st,stm32f7-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005800 0x400>;
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interrupts = <31>,
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<32>;
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resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
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clocks = <&rcc 1 CLK_I2C1>;
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};
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//Example 3 (with st,stm32f7-i2c compatible on stm32mp)
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/stm32mp1-clks.h>
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#include <dt-bindings/reset/stm32mp1-resets.h>
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i2c@40013000 {
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compatible = "st,stm32f7-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40013000 0x400>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc I2C2_K>;
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resets = <&rcc I2C2_R>;
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i2c-scl-rising-time-ns = <185>;
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i2c-scl-falling-time-ns = <20>;
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st,syscfg-fmp = <&syscfg 0x4 0x2>;
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};
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...
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