The correct values referred by a boolean control are
value.integer.value[], not value.enumerated.item[].
The former is long while the latter is int, so it's even incompatible
on 64bit architectures.
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
Cc: <stable@vger.kernel.org>
The TAS5086 has two power domains, DVDD and AVDD. Enable them both as
long as the codec is in use.
Also, switch on the power to identify the chip at device probe level,
and switch it off again afterwards. The codec level will take care for
power handling later.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
For CODEC controls snd_kcontrol_chip() currently returns a pointer to the
CODEC that registered the control. With the upcoming consolidation of
platform and CODEC controls this will change. Prepare for this by introducing
the snd_soc_kcontrol_codec() helper function that will hide the implementation
details of how the CODEC for a control can be obtained. This will allow us to
change this easily in the future.
The patch also updates all CODEC drivers to use the new helper function.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Acked-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
- Further work on the dmaengine helpers, including support for
configuring the parameters for DMA by reading the capabilities of the
DMA controller which removes some guesswork and magic numbers fromm
drivers.
- A refresh of the documentation.
- Conversions of many drivers to direct regmap API usage in order to
allow the ASoC level register I/O code to be removed, this will
hopefully be completed by v3.14.
- Support for using async register I/O in DAPM, reducing the time taken
to implement power transitions on systems that support it.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.14 (GNU/Linux)
iQIcBAABAgAGBQJSajLdAAoJELSic+t+oim9MVEQAJ3t7df5K9R/OynjhKiEFxpP
cBWo306CegZ5oO17UqG+SReJkOWgUI8zIUkNC818suTjtgyhv4WUBx1QgXG8akO5
arHZEQGyReLxgWbnO5ScP7BJt5ZYldfQWN+NPnNlzwvVA8R4xChvAwuHL+kUSSYW
DrOb0ag/Gtn2jQo3o9GbZb5c3UhZqoMg/pQSoVtnvG/O8N/xR0yoeXGsdJv1su6g
OKhCJTRWU8v3FONatR2wWXnSrCBOeJ2Ec7YUJil1FQQdENYZfV3AOsFHxmqsyG2O
Xj2P7CioY0JY7dtFcKjrXgsnjvgZmVdVsdegTJPWS9RjunjyupvSyhMhZYkoA60j
V7RxyIbHAx7hILQqCYYhlOczYHom4MSwAGGt7y7T3oKt0432RvIjE2fP7sTGaqD8
wzuVYuVl4km03xX9g9abF6xjyDE6e+4wun+d8kSvOosvd/nF47gkXUXEvPZh0Ley
013e5fHNDaNF4uaSVXE169JyVxVnHP6nXJDRWZakXsryGXGUpn0quIzobf6fb6XE
fY5Q3QoyP5rHdSMIvGN5Gi76KsHF5CWILWqcWLEVPLnaf9gJmrp3IypmF1c8i7VE
CrcTim5mhNePEX56skRaHhpYHmsxYApSAzxNAA/t3cJ2rtwb87jMM4jOcjHi/war
emSVe5lXkcwv/lU/Pa0N
=rVsK
-----END PGP SIGNATURE-----
Merge tag 'asoc-v3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-next
ASoC: Updates for v3.13
- Further work on the dmaengine helpers, including support for
configuring the parameters for DMA by reading the capabilities of the
DMA controller which removes some guesswork and magic numbers fromm
drivers.
- A refresh of the documentation.
- Conversions of many drivers to direct regmap API usage in order to
allow the ASoC level register I/O code to be removed, this will
hopefully be completed by v3.14.
- Support for using async register I/O in DAPM, reducing the time taken
to implement power transitions on systems that support it.
'of_match_ptr' is defined in linux/of.h. Include it explicitly.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mark Brown <broonie@linaro.org>
When going to suspend, shut down all channels and re-do the init
procedure at resume time.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
We'll need to call code to initialize and reset the codec again at
resume time, so factor it out first.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
We need to access the charge_period and start_mid_z values from other
places later, so move them to the private struct.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
It turns out that the TAS5086 doesn't like channel start parts to be
empty, and if all channels are configured to Mid-Z, part 1 has to be
used.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
The TAS5086 has two alternative modes to start its PWM channels, Mid-Z
and Low-Z. Which one to use depends on how the PWM power stages are
connected to the TAS5086.
This patch adds 6 optional boolean properties to the DT bindings of the
driver which allow the user to configure each individual channel to the
Mid-Z scheme, and leaves all the others to the default (Low-Z).
Signed-off-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
The TAS5086 has two muxes, one for connecting I2S inputs to internal
channels, and another one for selecting which internal channel should
be routed to which PWM output pin.
This patch adds DAPM widgets and routes for this driver.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Add register definitions for input and output mux registers, and rewrite
the tas5086_accessible_reg() function.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
In order to support registers of unequal sizes, the I2C I/O has to be
open-coded.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
"val" has to be signed for the error handling to work.
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Use the module_i2c_driver() macro to make the code smaller
and a bit simpler.
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Acked-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This patch adds a driver for TI's TA5086 6-channel PWM processor.
This chip has a very unusual register layout, specifically because the
registers are of unequal size, and multi-byte registers require bulk
writes to take effect. Regmap does not support these kind of mappings.
Currently, the driver does not touch any of the registers >= 0x20, so
it doesn't matter, because the register map is mapped to an 8-bit array.
In case more features will be added in the future that require access
to higher registers, the entire regmap H/W I/O routines have to be
open-coded.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Takashi Iwai