platform_driver does not need to set the owner field, as this will
be populated by the driver core.
Generated by scripts/coccinelle/api/platform_no_drv_owner.cocci.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The blackfin architecture is getting removed, so these are
now obsolete.
Acked-by: Aaron Wu <aaron.wu@analog.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
In certain cases interrupt enablement will be delayed relative to when
the InterruptEnable bits are written. One example of this is when
a GPIO's "debounce" logice is first enabled. After enabling debounce,
there is a 900 us "warm up" period during which InterruptEnable[0]
(bit 11) will read as 0 despite being written 1. During this time
InterruptSts will not be updated, nor will interrupts be delivered, even
if the GPIO's interrupt configuration has been written to the register.
To work around this delay, poll the InterruptEnable bits after setting
them to ensure interrupts have truly been enabled in hardware before
returning from the irq_enable handler.
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Bits have to be cleared in DEVCPU_GCB:GPIO:GPIO_OE for input and set for
output. ocelot_gpio_set_direction() got it wrong and this went unnoticed
when the driver was reworked.
Reported-by: Gregory Clement <gregory.clement@bootlin.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
For generic pins, parameter "arg" is 0 or 1.
For special pins, bias-disable is set by R0R1,
so we need transmited "00" to set bias-disable
When we set "bias-disable" as high-z property,
the parameter should be "MTK_PUPD_SET_R1R0_00".
Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
Reviewed-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The commit includes mt2712 pinctrl driver.
Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
Reviewed-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This fixes pcs_request_gpio() in the pinctrl-single driver when
bits_per_mux != 0. It appears this was overlooked when the multiple
pins per register feature was added.
Fixes: 4e7e8017a8 ("pinctrl: pinctrl-single: enhance to configure multiple pins of different modules")
Signed-off-by: David Lechner <david@lechnology.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Allows querying GPIO direction from the pad config register.
If the pad is not in GPIO mode, return an error.
Signed-off-by: Javier Arteaga <javier@emutex.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
These configs select MFD_SYSCON, but do not depend on HAS_IOMEM.
Compile testing on architecture without HAS_IOMEM causes "unmet
direct dependencies" in Kconfig phase.
Detected by "make ARCH=score allyesconfig".
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Assign true or false to boolean variables instead of an integer value.
This issue was detected with the help of Coccinelle.
Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The Allwinner pinctrl device tree binding suggests that a clock named
"apb" would drive the pin controller IP. However (for legacy reasons) we
rely on this clock actually being the first clock defined.
Since named clocks can be in any order, let's explicitly check for a
clock called "apb" if there is more than one clock referenced.
Kudo to Maxime for suggesting this much more elegant approach.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The U8540 was an evolved version of the U8500, but it was never
mass produced or put into products, only reference designs exist.
The upstream support was never completed and it is unlikely that
this will happen so drop the support for now to simplify
maintenance of the U8500.
Cc: Loic Pallardy <loic.pallardy@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Add USB pin groups on R-Car M3-N,
- Add support for the new R-Car V3H SoC,
- Add EtherAVB pin groups on R-Car V3M,
- Miscellaneous fixes and cleanups.
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Merge tag 'sh-pfc-for-v4.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v4.17 (take two)
- Add USB pin groups on R-Car M3-N,
- Add support for the new R-Car V3H SoC,
- Add EtherAVB pin groups on R-Car V3M,
- Miscellaneous fixes and cleanups.
Use union vin_data and VIN_DATA_PIN_GROUP() to reduce redundancies
in pin definitions.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Use union vin_data and VIN_DATA_PIN_GROUP() to reduce redundancies
in pin definitions.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Use union vin_data and VIN_DATA_PIN_GROUP() to reduce redundancies
in pin definitions.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
RGB666 has a pin assignment that differs from the other formats.
Fixes: fbd452aeb4 ("pinctrl: sh-pfc: r8a77995: Add VIN4 pins, groups and function")
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
RGB666 has a pin assignment that differs from the other formats.
Fixes: 8db6cbabac ("pinctrl: sh-pfc: r8a7796: Add VIN4, VIN5 pins, groups and functions")
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
RGB666 has a pin assignment that differs from the other formats.
Fixes: 6b4de40810 ("pinctrl: sh-pfc: r8a7795: Add VIN4, VIN5 pins, groups and functions")
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
On other Renesas SoCs, the pin group for the MDIO bus is named "mdio"
instead of "mdc". Fix the inconsistency, while retaining backwards
compatibility with old DTBs using a pin group alias.
Fixes: 66abd968d0 ("pinctrl: sh-pfc: r8a77995: Add EthernetAVB pins, groups and functions")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
On other Renesas SoCs, the pin group for the MDIO bus is named "mdio"
instead of "mdc". Fix the inconsistency, while retaining backwards
compatibility with old DTBs using a pin group alias.
Fixes: fa3e8b71b9 ("pinctrl: sh-pfc: r8a77965: Add EtherAVB groups/functions")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
On other Renesas SoCs, the pin group for the MDIO bus is named "mdio"
instead of "mdc". Fix the inconsistency, while retaining backwards
compatibility with old DTBs using a pin group alias.
Fixes: 41397032c4 ("pinctrl: sh-pfc: r8a7796: Add group for AVB MDIO and MII pins")
Fixes: 9c99a63ec7 ("pinctrl: sh-pfc: r8a7796: Add EtherAVB pins, groups and functions")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
On other Renesas SoCs, the pin group for the MDIO bus is named "mdio"
instead of "mdc". Fix the inconsistency, while retaining backwards
compatibility with old DTBs using a pin group alias.
Fixes: b25719eb93 ("pinctrl: sh-pfc: r8a7795: Add group for AVB MDIO and MII pins")
Fixes: 819fd4bfcc ("pinctrl: sh-pfc: r8a7795: add EtherAVB support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
On other Renesas SoCs, the pin group for the MDIO bus is named "mdio"
instead of "mdc". Fix the inconsistency, while retaining backwards
compatibility with old DTBs using a pin group alias.
Fixes: 30c078de6f ("pinctrl: sh-pfc: r8a7795: Add EtherAVB pins, groups and function")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Add a macro to refer to another pin group with a different name.
This will be used to rename wrongly-named pin groups, while retaining
backwards compatibility with old DTBs.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
The pin controller drivers for all R-Car Gen2 SoCs have entries for the
EtherAVB TX_ER pins in their EtherAVB MII groups, except on R-Car H2.
Add the missing pin to restore consistency.
Note that technically TX_ER is an optional signal in the MII bus, and
thus could have its own group, but this is currently not supported by
any R-Car Gen2 pin controller driver.
Fixes: 19ef697d1e ("sh-pfc: r8a7790: add EtherAVB pin groups")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Add the EtherAVB pin groups to the R8A77970 PFC driver.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add the PFC support for the R8A77980 SoC including pin groups for some
on-chip devices such as AVB, CAN-FD, GETHER, [H]SCIF, I2C, INTC-EX, MMC,
MSIOF, PWM, and VIN...
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
They follow the style of the existing PORT_GP_CFG_<n>() macros and
will be used by a follow-up patch for the R8A77980 SoC.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Driver uses alias from Device Tree as an index of pin controller data
array. In case of a wrong DTB or an out-of-tree DTB, the alias could be
outside of this data array leading to out-of-bounds access.
Depending on binary and memory layout, this could be handled properly
(showing error like "samsung-pinctrl 3860000.pinctrl: driver data not
available") or could lead to exceptions.
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: <stable@vger.kernel.org>
Fixes: 30574f0db1 ("pinctrl: add samsung pinctrl and gpiolib driver")
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch adds USB30 (USB3.0 host) pin, group and function to
the R8A77965 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
- Add DU and VIN pin groups on R-Car D3,
- Add HDMI, TMU, and VIN pin groups on R-Car H3 and M3-W,
- Add support for the new R-Car M3-N SoC,
- Small fixes and cleanups.
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Merge tag 'sh-pfc-for-v4.17-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v4.17
- Add DU and VIN pin groups on R-Car D3,
- Add HDMI, TMU, and VIN pin groups on R-Car H3 and M3-W,
- Add support for the new R-Car M3-N SoC,
- Small fixes and cleanups.
Systems that don't have devicetree need pinctrl_register_mappings.
It should be EXPORT_SYMBOL_GPL so that it can be called from
pinctrl drivers built as modules.
Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Meson8b is a cost reduced variant of the Meson8 SoC. It's package size
is smaller than Meson8.
Unfortunately there are a few key differences which cannot be seen
without close inspection of the code and the public S805 datasheet:
- the GPIOX bank is missing the GPIOX_12, GPIOX_13, GPIOX_14 and
GPIOX_15 GPIOs
- the GPIOY bank is missing the GPIOY_2, GPIOY_4, GPIOY_5, GPIOY_15 and
GPIOY_16 GPIOs
- the GPIODV bank is missing all GPIOs except GPIODV_9, GPIODV_24,
GPIODV_25, GPIODV_26, GPIODV_27, GPIODV_28 and GPIODV_29
- the GPIOZ bank is missing completely
- there is a new GPIO bank called "DIF"
This means that Meson8b only has 83 actual GPIO lines. Without any holes
there would be 130 GPIO lines in total (120 are inherited from Meson8
plus 10 new from the DIF bank).
GPIOs greater GPIOZ_3 (whose ID is 83 - as a reminder: this is exactly
the number of actual GPIO lines on Meson8b and also the value of
meson8b_cbus_pinctrl_data.num_pins) cannot berequested. Using CARD_6
(which used ID 100 prior to this patch, "base of the GPIO controller was
382) as an example:
$ echo 482 > /sys/class/gpio/export
export_store: invalid GPIO 482
This removes all non-existing pins from to dt-bindings header file
(include/dt-bindings/gpio/meson8b-gpio.h). This allows us to have a
consecutive numbering for the GPIO #defines (GPIOY_2 doesn't exist for
example, so previously the GPIOY_3 ID was "GPIOY_1 + 2", after this
patch it is "GPIOY_1 + 1"). As a nice side-effect this means that we get
compile-time (instead of runtime) errors if Meson8b .dts uses a pin that
only exists on Meson8.
Additionally the pinctrl-meson8b driver has to be updated to handle this
new GPIO numbering. By default a struct meson_bank only handles GPIO
banks where the pins are numbered consecutively because it calculates
the bit offsets based on the GPIO IDs.
This is solved by taking the original BANK() definition and splitting it
into consecutive subsets (X0..11 and X16..21). The bit offsets for each
new bank includes the skipped GPIOs (the definition of the "X0..11" bank
is identical to the old "X" bank apart from the "last IRQ" field, the
definition of the new, split "X16..21" bank takes the original "X" bank
and adds 16 - the start of the new split bank - to the "first IRQ",
pullen bit, pull bit, dir bit, out bit and in bit).
Commit 984cffdeae ("pinctrl: Fix gpio/pin mapping for Meson8b")
fixed the same issue by setting "ngpio" (of the gpio_chip) to 130.
Unfortunately this broke in db80f0e158 ("pinctrl: meson: get rid of
unneeded domain structures").
The solution from this patch was considered to be better than the
previous attempt at fixing this because it provides compile-time error
checking for the GPIOs that exist on Meson8 but don't exist on Meson8b.
The following pins were tested on an Odroid-C1 using the sysfs GPIO
interface checking that their value (high or low) could be read:
- GPIOX_0, GPIOX_1, GPIOX_2, GPIOX_3, GPIOX_4, GPIOX_5, GPIOX_6,
GPIOX_7, GPIOX_8, GPIOX_9, GPIOX_10, GPIOX_11, GPIOX_18, GPIOX_19,
GPIOX_20, GPIOX_21
- GPIOY_3, GPIOY_7, GPIOY_8
(some of these had to be pulled up because they were low by default,
others were high by default so these had to be pulled down)
Reported-by: Linus Lüssing <linus.luessing@c0d3.blue>
Suggested-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
When dt_to_map_one_config() is called with a pinctrl_dev passed
in, it should only be using this if the node being looked up
is a hog. The code was always using the passed pinctrl_dev
without checking whether the dt node referred to it.
A pin controller can have pinctrl-n dependencies on other pin
controllers in these cases:
- the pin controller hardware is external, for example I2C, so
needs other pin controller(s) to be setup to communicate with
the hardware device.
- it is a child of a composite MFD so its of_node is shared with
the parent MFD and other children of that MFD. Any part of that
MFD could have dependencies on other pin controllers.
Because of this, dt_to_map_one_config() can't assume that if it
has a pinctrl_dev passed in then the node it looks up must be
a hog. It could be a reference to some other pin controller.
Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add group configuration for uarts that are cut down
variants, the standard being full, i.e. all signals,
flow control, i.e. rx/tx and cts/rts, and rx/tx only.
This allows us to be more precise in which pins we're
actually using.
Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Now that arch/metag/ has been removed, along with TZ1090 SoC support,
remove the TZ1090 pinctrl drivers. They are of no value without the
architecture and SoC platform code.
Signed-off-by: James Hogan <jhogan@kernel.org>
Cc: linux-gpio@vger.kernel.org
Cc: linux-metag@vger.kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Most pins on the R8A77965 SoC can be configured in GPIO mode for
interrupt and GPIO functionality, while a couple of them can also
be routed to the INTC-EX hardware block (formerly known as IRQC).
On R8A77965 the INTC-EX hardware handles pins IRQ0 -> IRQ5 and
this patch adds support for them to the PFC driver as "intc_ex_irqN".
Based on a similar patch for the R8A7795 PFC driver by Magnus Damm
<damm+renesas@opensource.se>.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch adds VIN4 pins, groups and function for the
R8A77995 (D3) SoC.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch adds VIN4 and VIN5 pins, groups and functions for the
R8A7795 SoC.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch adds VIN4 and VIN5 pins, groups and functions for the
R8A7796 SoC.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The mcp23s08 series device can be configured for wired and interrupts
using an external pull-up and open drain output via the IOCON_ODR bit.
And "drive-open-drain" property to enable this.
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: Phil Reid <preid@electromag.com.au>
Reviewed-by: Jan Kundrát <jan.kundrat@cesnet.cz>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
one_regmap_config is always null if mcp type is MCP_TYPE_S18.
Remove the null check so that the mcp23s18 will probe.
Fixes: 1781af563a ("pinctrl: mcp23s08: spi: Fix duplicate pinctrl debugfs entries")
Signed-off-by: Phil Reid <preid@electromag.com.au>
Reviewed-by: Jan Kundrát <jan.kundrat@cesnet.cz>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
On boot, gpiochip_add_data() initializes the FLAG_IS_OUT bit in
desc->flags iff its gpio_chip does not have ->direction_input() handler,
else it is initialized to 0, which implies the GPIO is an "input".
Later, the sysfs "direction" handler will use gpiod_get_direction() to
get the current direction, but if no ->get_direction() handler is
installed, the result will just be the current (initial) value of flags,
which will always be OUT irregardless of the initial register value.
Add a get_direction() handler to pinctrl-amd to fix this and always
provide the correct value for direction.
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
...instead of open coding file operations followed by custom ->open()
callbacks per each attribute.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The function ocelot_pinctrl_probe is local to the source and does not
need to be in global scope, so make it static.
Cleans up sparse warning:
drivers/pinctrl/pinctrl-ocelot.c:465:5: warning: symbol
'ocelot_pinctrl_probe' was not declared. Should it be static?
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add SCIF[0-5] groups and pin function definitions for R-Car M3-N.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add initial PFC support for R-Car M3-N (r8a77965) SoC.
No groups or functions defined, just pin and registers enumeration.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch adds TMU TCLK{1,2} pins, groups and functions to
the R8A7796 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch adds TMU TCLK{1,2} pins, groups and functions to
the R8A7795 ES1.x SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch adds TMU TCLK{1,2} pins, groups and functions to
the R8A7795 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch adds HDMI0 CEC pin, group and function to the R8A7796 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch adds HDMI0 CEC pin, group and function to
the R8A7795 ES1.x SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[uli: fixed typo in comment]
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch adds HDMI0 CEC pin, group and function to the R8A7795 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[uli: fixed typo in comment]
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch fixes to set IPSR and MOD_SEL when using NFDATA{14,15}_A and
NF{RB,WP}_N_A pin function is selected. And renamess MOD_SEL2 bit22 value
definition name to SEL_NDFC.
This is a correction to the incorrect implementation of MOD_SEL register
pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware
User's Manual Rev.0.53E.
Fixes: f9aece7344 ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch fixes MOD_SEL1 bit20 and MOD_SEL2 bit20, bit21 pin assignment
for SSI pins group.
This is a correction to the incorrect implementation of MOD_SEL register
pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware
User's Manual Rev.0.51E or later.
Fixes: f9aece7344 ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch fixes MOD_SEL1 bit20 and MOD_SEL2 bit20, bit21 pin assignment
for SSI pins group.
This is a correction because MOD_SEL register specification for R8A7795
ES2.0 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.53E.
Fixes: b205914c8f ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0")
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch adds DU pins, groups and function for the R8A77995 (D3) SoC.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The MUSB block in the Nomadik has two pin settings: high speed or
full speed. These correspond to two unique pin group settings: all
pins set to function B for high speed and all set to function C
for full speed. Full speed uses more pins than high speed.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
A string which did not contain a data format specification should be put
into a sequence. Thus use the corresponding function "seq_puts".
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Simply adjust the pin group to _x _y _z style, as to
keep the consistency in DT with previous naming scheme.
Fixes: 83c566806a ("pinctrl: meson-axg: Add new pinctrl driver for Meson AXG SoC")
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The base of the TLMM gpiochip should not be statically defined as 0, fix
this to not artificially restrict the existence of multiple pinctrl-msm
devices.
Fixes: f365be0925 ("pinctrl: Add Qualcomm TLMM driver")
Reported-by: Timur Tabi <timur@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This is a bit more involved because the pinctrl core so far always
assumed that one device (with a unique dev_name) only contains a single
pinctrl thing. This is not true for the mcp23s08 driver for chips
connected over SPI. They have a "logical address" which means that
several chips can share one physical CS signal.
A downside of this patch are some possibly ugly names for the debugfs
entries, such as "spi1.1-mcp23xxx-pinctrl.2", etc.
Signed-off-by: Jan Kundrát <jan.kundrat@cesnet.cz>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
When several devices are sharing one hardware SPI CS, there is no visual
clue in `lsgpio` or in /sys/kernel/debug/gpio about which one is which
one. Stuff depends on the enumeration order, and therefore lower chip
addresses always go first, but that's just an implementation detail.
This change includes the device-specific address in the debug output:
gpiochip4: GPIOs 464-479, parent: spi/spi1.1, mcp23s17.2, can sleep:
gpiochip3: GPIOs 480-495, parent: spi/spi1.1, mcp23s17.1, can sleep:
Signed-off-by: Jan Kundrát <jan.kundrat@cesnet.cz>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The SPI version of this chip allows several devices to be present on the
same SPI bus via a local address. If this is in action and if the kernel
has debugfs, however, the code attempts to create duplicate entries for
the regmap's debugfs:
mcp23s08 spi1.1: Failed to create debugfs directory
This patch simply assigns a local name matching the device logical
address to the `struct regmap_config`.
No changes are needed for MCP23S18 because that device does not support
any logical addressing. Similarly, I2C devices do not need any action,
either, because they are already different in their I2C address.
A similar problem is present for the pinctrl debugfs instance, but that
one is not addressed by this patch.
Signed-off-by: Jan Kundrát <jan.kundrat@cesnet.cz>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds the pinctrl definitions for the TLMM of SDM845.
Signed-off-by: Kyle Yan <kyan@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Core changes:
- After lengthy discussions and partly due to my ignorance, we have
merged a patch making pinctrl_force_default() and pinctrl_force_sleep()
reprogram the states into the hardware of any hogged pins, even
if they are already in the desired state. This only apply to hogged
pins since groups of pins owned by drivers need to be managed by
each driver, lest they could not do things like runtime PM and
put pins to sleeping state even if the system as a whole is not
in sleep.
New drivers:
- New driver for the Microsemi Ocelot SoC. This is used in ethernet
switches.
- The X-Powers AXP209 GPIO driver was extended to also deal with pin
control and moved over from the GPIO subsystem. This circuit is
a mixed-mode integrated circuit which is part of AllWinner designs.
- New subdriver for the Qualcomm MSM8998 SoC, core of a high end
mobile devices (phones) chipset.
- New subdriver for the ST Microelectronics STM32MP157 MPU and
STM32F769 MCU from the STM32 family.
- New subdriver for the MediaTek MT7622 SoC. This is used for routers,
repeater, gateways and such network infrastructure.
- New subdriver for the NXP (former Freescale) i.MX 6ULL. This SoC has
multimedia features and target "smart devices", I guess in-car
entertainment, in-flight entertainment, industrial control panels etc.
General improvements:
- Incremental improvements on the SH-PFC subdrivers for things like
the CAN bus.
- Enable the glitch filter on Baytrail GPIOs used for interrupts.
- Proper handling of pins to GPIO ranges on the Semtec SX150X
- An IRQ setup ordering fix on MCP23S08.
- A good set of janitorial coding style fixes.
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Merge tag 'pinctrl-v4.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v4.16 kernel cycle.
Like with GPIO it is actually a bit calm this time.
Core changes:
- After lengthy discussions and partly due to my ignorance, we have
merged a patch making pinctrl_force_default() and
pinctrl_force_sleep() reprogram the states into the hardware of any
hogged pins, even if they are already in the desired state.
This only apply to hogged pins since groups of pins owned by
drivers need to be managed by each driver, lest they could not do
things like runtime PM and put pins to sleeping state even if the
system as a whole is not in sleep.
New drivers:
- New driver for the Microsemi Ocelot SoC. This is used in ethernet
switches.
- The X-Powers AXP209 GPIO driver was extended to also deal with pin
control and moved over from the GPIO subsystem. This circuit is a
mixed-mode integrated circuit which is part of AllWinner designs.
- New subdriver for the Qualcomm MSM8998 SoC, core of a high end
mobile devices (phones) chipset.
- New subdriver for the ST Microelectronics STM32MP157 MPU and
STM32F769 MCU from the STM32 family.
- New subdriver for the MediaTek MT7622 SoC. This is used for
routers, repeater, gateways and such network infrastructure.
- New subdriver for the NXP (former Freescale) i.MX 6ULL. This SoC
has multimedia features and target "smart devices", I guess in-car
entertainment, in-flight entertainment, industrial control panels
etc.
General improvements:
- Incremental improvements on the SH-PFC subdrivers for things like
the CAN bus.
- Enable the glitch filter on Baytrail GPIOs used for interrupts.
- Proper handling of pins to GPIO ranges on the Semtec SX150X
- An IRQ setup ordering fix on MCP23S08.
- A good set of janitorial coding style fixes"
* tag 'pinctrl-v4.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (102 commits)
pinctrl: mcp23s08: fix irq setup order
pinctrl: Forward declare struct device
pinctrl: sunxi: Use of_clk_get_parent_count() instead of open coding
pinctrl: stm32: add STM32F769 MCU support
pinctrl: sx150x: Add a static gpio/pinctrl pin range mapping
pinctrl: sx150x: Register pinctrl before adding the gpiochip
pinctrl: sx150x: Unregister the pinctrl on release
pinctrl: ingenic: Remove redundant dev_err call in ingenic_pinctrl_probe()
pinctrl: sprd: Use seq_putc() in sprd_pinconf_group_dbg_show()
pinctrl: pinmux: Use seq_putc() in pinmux_pins_show()
pinctrl: abx500: Use seq_putc() in abx500_gpio_dbg_show()
pinctrl: mediatek: mt7622: align error handling of mtk_hw_get_value call
pinctrl: mediatek: mt7622: fix potential uninitialized value being returned
pinctrl: uniphier: refactor drive strength get/set functions
pinctrl: imx7ulp: constify struct imx_cfg_params_decode
pinctrl: imx: constify struct imx_pinctrl_soc_info
pinctrl: imx7d: simplify imx7d_pinctrl_probe
pinctrl: imx: use struct imx_pinctrl_soc_info as a const
pinctrl: sunxi-pinctrl: fix pin funtion can not be match correctly.
pinctrl: qcom: Add msm8998 pinctrl driver
...
Core changes:
- Disallow open drain and open source flags to be set
simultaneously. This doesn't make electrical sense, and would
the hardware actually respond to this setting, the result
would be short circuit.
- ACPI GPIO has a new core infrastructure for handling quirks.
The quirks are there to deal with broken ACPI tables centrally
instead of pushing the work to individual drivers. In the world
of BIOS writers, the ACPI tables are perfect. Until they find a
mistake in it. When such a mistake is found, we can patch it
with a quirk. It should never happen, the problem is that it
happens. So we accomodate for it.
- Several documentation updates.
- Revert the patch setting up initial direction state from
reading the device. This was causing bad things for drivers
that can't read status on all its pins. It is only affecting
debugfs information quality.
- Label descriptors with the device name if no explicit label is
passed in.
- Pave the ground for transitioning SPI and regulators to use
GPIO descriptors by implementing some quirks in the device tree
GPIO parsing code.
New drivers:
- New driver for the Access PCIe IDIO 24 family.
Other:
- Major refactorings and improvements to the GPIO mockup driver
used for test and verification.
- Moved the AXP209 driver over to pin control since it gained a
pin control back-end. These patches will appear (with the same
hashes) in the pin control pull request as well.
- Convert the onewire GPIO driver w1-gpio to use descriptors.
This is merged here since the W1 maintainers send very few
pull requests and he ACKed it.
- Start to clean up driver headers using <linux/gpio.h> to just
use <linux/gpio/driver.h> as appropriate.
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Merge tag 'gpio-v4.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio
Pull GPIO updates from Linus Walleij:
"The is the bulk of GPIO changes for the v4.16 kernel cycle. It is
pretty calm this time around I think. I even got time to get to things
like starting to clean up header includes.
Core changes:
- Disallow open drain and open source flags to be set simultaneously.
This doesn't make electrical sense, and would the hardware actually
respond to this setting, the result would be short circuit.
- ACPI GPIO has a new core infrastructure for handling quirks. The
quirks are there to deal with broken ACPI tables centrally instead
of pushing the work to individual drivers. In the world of BIOS
writers, the ACPI tables are perfect. Until they find a mistake in
it. When such a mistake is found, we can patch it with a quirk. It
should never happen, the problem is that it happens. So we
accomodate for it.
- Several documentation updates.
- Revert the patch setting up initial direction state from reading
the device. This was causing bad things for drivers that can't read
status on all its pins. It is only affecting debugfs information
quality.
- Label descriptors with the device name if no explicit label is
passed in.
- Pave the ground for transitioning SPI and regulators to use GPIO
descriptors by implementing some quirks in the device tree GPIO
parsing code.
New drivers:
- New driver for the Access PCIe IDIO 24 family.
Other:
- Major refactorings and improvements to the GPIO mockup driver used
for test and verification.
- Moved the AXP209 driver over to pin control since it gained a pin
control back-end. These patches will appear (with the same hashes)
in the pin control pull request as well.
- Convert the onewire GPIO driver w1-gpio to use descriptors. This is
merged here since the W1 maintainers send very few pull requests
and he ACKed it.
- Start to clean up driver headers using <linux/gpio.h> to just use
<linux/gpio/driver.h> as appropriate"
* tag 'gpio-v4.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (103 commits)
gpio: Timestamp events in hardirq handler
gpio: Fix kernel stack leak to userspace
gpio: Fix a documentation spelling mistake
gpio: Documentation update
gpiolib: remove redundant initialization of pointer desc
gpio: of: Fix NPE from OF flags
gpio: stmpe: Delete an unnecessary variable initialisation in stmpe_gpio_probe()
gpio: stmpe: Move an assignment in stmpe_gpio_probe()
gpio: stmpe: Improve a size determination in stmpe_gpio_probe()
gpio: stmpe: Use seq_putc() in stmpe_dbg_show()
gpio: No NULL owner
gpio: stmpe: i2c transfer are forbiden in atomic context
gpio: davinci: Include proper header
gpio: da905x: Include proper header
gpio: cs5535: Include proper header
gpio: crystalcove: Include proper header
gpio: bt8xx: Include proper header
gpio: bcm-kona: Include proper header
gpio: arizona: Include proper header
gpio: amd8111: Include proper header
...
When using mcp23s08 module with gpio-keys, often (50% of boots)
it fails to get irq numbers with message:
"gpio-keys keys: Unable to get irq number for GPIO 0, error -6".
Seems that irqs must be setup before devm_gpiochip_add_data().
Cc: stable@vger.kernel.org
Signed-off-by: Dmitry Mastykin <mastichi@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Without such a range, gpiolib fails with -EPROBE_DEFER, pending the
addition of the range. So, without a range, gpiolib will keep
deferring indefinitely.
Cc: stable@vger.kernel.org
Fixes: 9e80f9064e ("pinctrl: Add SX150X GPIO Extender Pinctrl Driver")
Fixes: e10f72bf4b ("gpio: gpiolib: Generalise state persistence beyond sleep")
Suggested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Various gpiolib activity depend on the pinctrl to be up and kicking.
Therefore, register the pinctrl before adding a gpiochip.
Cc: stable@vger.kernel.org
Suggested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
There is no matching call to pinctrl_unregister, so switch to the
managed devm_pinctrl_register to clean up properly when done.
Cc: stable@vger.kernel.org
Fixes: 9e80f9064e ("pinctrl: Add SX150X GPIO Extender Pinctrl Driver")
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
There is a error message within devm_ioremap_resource
already, so remove the dev_err call to avoid redundant
error message.
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
A single character (line break) should be put into a sequence.
Thus use the corresponding function "seq_putc".
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
A single character (line break) should be put into a sequence.
Thus use the corresponding function "seq_putc".
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
A single character (line break) should be put into a sequence.
Thus use the corresponding function "seq_putc".
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Make consistent error handling of all mtk_hw_get_value occurrences using
propagating error code from the internal instead of creating a new one.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
commit d6ed935513 ("pinctrl: mediatek: add pinctrl driver for MT7622
SoC") leads to the following static checker warning:
drivers/pinctrl/mediatek/pinctrl-mt7622.c:1419 mtk_gpio_get()
error: uninitialized symbol 'value'.
1412 static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
1413 {
1414 struct mtk_pinctrl *hw = dev_get_drvdata(chip->parent);
1415 int value;
1416
1417 mtk_hw_get_value(hw, gpio, PINCTRL_PIN_REG_DI, &value);
^^^^^^^^^^^^^^^^
1418
1419 return !!value;
1420 }
The appropriate error handling must be added to avoid the potential error
caused by uninitialized value being returned.
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
There is code duplication between uniphier_conf_pin_drive_get() and
uniphier_conf_pin_drive_set(). Factor out the common code into
uniphier_conf_get_drvctrl_data().
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The decode parameters are constant mark them const.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Now that imx_pinctrl_probe accepts const struct imx_pinctrl_soc_info
we can constify all declarations of struct imx_pinctrl_soc_info.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Using of_device_get_match_data in imx7d_pinctrl_probe simplifies
the function. Also get rid of the void pointer cast since
imx_pinctrl_probe now accepts const struct imx_pinctrl_soc_info.
Cc: Arvind Yadav <arvind.yadav.cs@gmail.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
For some SoCs the struct imx_pinctrl_soc_info is passed through
of_device_id.data which is const. Most variables are already const
or otherwise not written. However, some fields are modified at
runtime. Move those fields to the dynamically allocated struct
imx_pinctrl.
Fixes: b3060044e4 ("pinctrl: freescale: imx7d: make of_device_ids const")
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Arvind Yadav <arvind.yadav.cs@gmail.com>
Cc: Gary Bisson <gary.bisson@boundarydevices.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Pin function can not be match correctly when SUNXI_PIN describe with
mutiple variant and same function.
such as:
on pinctrl-sun4i-a10.c
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_VARIANT(0x2, "pwm", /* PWM0 */
PINCTRL_SUN4I_A10 |
PINCTRL_SUN7I_A20),
SUNXI_FUNCTION_VARIANT(0x3, "pwm", /* PWM0 */
PINCTRL_SUN8I_R40)),
it would always match to the first variant function
(PINCTRL_SUN4I_A10, PINCTRL_SUN7I_A20)
so we should add variant compare on it.
Signed-off-by: hao_zhang <hao5781286@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Print a line break together with other data in a single function call.
* Adjust indentation.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
On i.MX 6ULL, the BOOT_MODEx and TAMPERx pin MUX and CTRL registers
are available in a separate IOMUXC_SNVS module. Add support for the
IOMUXC_SNVS module to the i.MX 6UL pinctrl driver.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The Microsemi Ocelot SoC has a few pins that can be used as GPIOs or take
multiple other functions. Add a driver for the pinmuxing and the GPIOs.
There is currently no support for interrupts.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
desc->mux_setting is set to NULL in pin_free() called just below.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Add PWM pin groups on various R-Car Gen2 and RZ/G1 SoCs,
- Add missing I2C5 pin groups on R-Car E2 and RZ/G1E,
- Add SATA pin groups on R-Car H3 ES2.0.
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Merge tag 'sh-pfc-for-v4.16-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v4.16 (take two)
- Add PWM pin groups on various R-Car Gen2 and RZ/G1 SoCs,
- Add missing I2C5 pin groups on R-Car E2 and RZ/G1E,
- Add SATA pin groups on R-Car H3 ES2.0.
The data field of an of_device_id structure has type const void *, so
there is no need for a const-discarding cast when putting const values
into such a structure.
Done using Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The return value of of_device_get_match_data has type const void *.
The desc field of the pctl structure also has a const type, so there
is no need for the const-discarding cast between them.
Done using Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This driver creates a const structure that it stores in the data field
of an of_device_id array.
Adding const to the declaration of the location that receives the
const value from the data field ensures that the compiler will
continue to check that the value is not modified. Furthermore, the
const-discarding cast on the extraction from the data field is no
longer needed.
Done using Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
On some systems, some PCB traces attached to GpioInts are routed in such
a way that they pick up enough interference to constantly (many times per
second) trigger.
Enabling glitch-filtering fixes this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Omit an extra message for a memory allocation failure in these functions.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Omit extra messages for a memory allocation failure in this function.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Omit an extra message for a memory allocation failure in this function.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Omit extra messages for a memory allocation failure in this function.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Omit extra messages for a memory allocation failure in this function.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Omit an extra message for a memory allocation failure in this function.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Omit an extra message for a memory allocation failure in these functions.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Omit an extra message for a memory allocation failure in these functions.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The script "checkpatch.pl" pointed information out like the following.
WARNING: void function return statements are not generally useful
Thus remove such a statement in the affected function.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Omit an extra message for a memory allocation failure in this function.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Adjust words in these descriptions.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Replace the specification of a data structure by a pointer dereference
as the parameter for the operator "sizeof" to make the corresponding size
determination a bit safer according to the Linux coding style convention.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Omit extra messages for a memory allocation failure in these functions.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Omit an extra message for a memory allocation failure in this function.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Omit an extra message for a memory allocation failure in this function.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The 'early' argument of irq_domain_activate_irq() is actually used to
denote reservation mode. To avoid confusion, rename it before abuse
happens.
No functional change.
Fixes: 7249164346 ("genirq/irqdomain: Update irq_domain_ops.activate() signature")
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Alexandru Chirvasitu <achirvasub@gmail.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Dou Liyang <douly.fnst@cn.fujitsu.com>
Cc: Pavel Machek <pavel@ucw.cz>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: Mikael Pettersson <mikpelinux@gmail.com>
Cc: Josh Poulson <jopoulso@microsoft.com>
Cc: Mihai Costache <v-micos@microsoft.com>
Cc: Stephen Hemminger <sthemmin@microsoft.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: linux-pci@vger.kernel.org
Cc: Haiyang Zhang <haiyangz@microsoft.com>
Cc: Dexuan Cui <decui@microsoft.com>
Cc: Simon Xiao <sixiao@microsoft.com>
Cc: Saeed Mahameed <saeedm@mellanox.com>
Cc: Jork Loeser <Jork.Loeser@microsoft.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: devel@linuxdriverproject.org
Cc: KY Srinivasan <kys@microsoft.com>
Cc: Alan Cox <alan@linux.intel.com>
Cc: Sakari Ailus <sakari.ailus@intel.com>,
Cc: linux-media@vger.kernel.org
When merging A20 pinctrl support to A10 pinctrl driver, the I2C function
of PI3 is wrongly written as "i2c3" (it should be "i2c4").
Fix this typo.
Fixes: cad4e209c1 ("pinctrl: sunxi: add support of R40 to A10 pinctrl driver")
Reported-by: Mark Kettenis <mark.kettenis@xs4all.nl>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Omit an extra message for a memory allocation failure in this function.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This reverts commit 93ebe8636b.
After discussion and review of the v11 patchset, a new approach
was found so that this patch is not needed.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl-msm only accepts an array of GPIOs from 0 to n-1, and it expects
each group to support have only one pin (npins == 1).
We can support "sparse" GPIO maps if we allow for some groups to have zero
pins (npins == 0). These pins are "hidden" from the rest of the driver
and gpiolib.
Access to unavailable GPIOs is blocked via a request callback. If the
requested GPIO is unavailable, -EACCES is returned, which prevents
further access to that GPIO.
Signed-off-by: Timur Tabi <timur@codeaurora.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Replace the specification of data structures by variable references
as the parameter for the operator "sizeof" to make the corresponding size
determination a bit safer according to the Linux coding style convention.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Omit an extra message for a memory allocation failure in these functions.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Replace the specification of a data structure by a pointer dereference
as the parameter for the operator "sizeof" to make the corresponding size
determination a bit safer according to the Linux coding style convention.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Omit an extra message for a memory allocation failure in this function.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Tested with a Salvator-XS and H3 ES2.0.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Omit an extra message for a memory allocation failure in this function.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Pinctrl single should just show how many pins were found, the physical
address is already in the dev information. So let's remove the wrong
information that claims to show the physical address but really prints
a virtual address that is now hashed.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Add CAN pin groups on RZ/G1E,
- Add CAN and CAN FD pin groups on R-Car H3 ES2.0, and R-Car D3,
- Add support for the new R-Car V3M SoC,
- Add support for I2C on R-Car D3,
- Small fixes and cleanups.
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Merge tag 'sh-pfc-for-v4.16-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v4.16
- Add CAN pin groups on RZ/G1E,
- Add CAN and CAN FD pin groups on R-Car H3 ES2.0, and R-Car D3,
- Add support for the new R-Car V3M SoC,
- Add support for I2C on R-Car D3,
- Small fixes and cleanups.
This fixes some compilation issues.
GENERIC_PINCONF and OF at least for pinconf_generic_dt_*, PINMUX at
least for pinmux_ops and GPIOLIB for at least gpio_chip.
Fixes: 23f75d7dfa ("pinctrl: axp209: add pinctrl features")
Reported-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The number of GPIOs is gotten from a field within the structure
referenced in the of_device.data but it was actually read before it was
retrieved, thus it was dereferencing a null pointer.
Set the number of GPIOs after retrieving of_device.data.
Fixes: e1190083b8 ("pinctrl: axp209: add support for AXP813 GPIOs")
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Reported-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Tested-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
We generally leave the GPIO clock disabled, unless an interrupt is
requested or we're accessing IO registers. We forgot to do this for the
->get_direction() callback, which means we can sometimes [1] get
incorrect results [2] from, e.g., /sys/kernel/debug/gpio.
Enable the clock, so we get the right results!
[1] Sometimes, because many systems have 1 or mor interrupt requested on
each GPIO bank, so they always leave their clock on.
[2] Incorrect, meaning the register returns 0, and so we interpret that
as "input".
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add support for pinctrl on MT7622 SoC. The IO core found on the SoC has
the registers for pinctrl, pinconf and gpio mixed up in the same register
range. However, the IO core for the MT7622 SoC is completely distinct from
anyone of previous MediaTek SoCs which already had support, such as
the hardware internal, register address map and register detailed
definition for each pin.
Therefore, instead, the driver is being newly implemented by reusing
generic methods provided from the core layer with GENERIC_PINCONF,
GENERIC_PINCTRL_GROUPS, and GENERIC_PINMUX_FUNCTIONS for the sake of code
simplicity and rid of superfluous code. Where the function of pins
determined by groups is utilized in this driver which can help developers
less confused with what combinations of pins effective on the SoC and even
reducing the mistakes during the integration of those relevant boards.
As the gpio_chip handling is also only a few lines, the driver also
implements the gpio functionality directly through GPIOLIB.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Reviewed-by: Biao Huang <biao.huang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Since lots of MediaTek drivers had been added, it seems slightly better
for that adding cleanup for placing MediaTek pinctrl drivers under the
independent menu as other kinds of drivers usually was done.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Reviewed-by: Biao Huang <biao.huang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This driver consists of 2 controllers due to a hole in mapping:
-1 controller for GPIO bankA to K.
-1 controller for GPIO bankZ.
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
In case a platform only defaults a "default" set of pins, but not a
"sleep" set of pins, and this particular platform suspends and resumes
in a way that the pin states are not preserved by the hardware, when we
resume, we would call pinctrl_single_resume() -> pinctrl_force_default()
-> pinctrl_select_state() and the first thing we do is check that the
pins state is the same as before, and do nothing.
In order to fix this, decouple the actual state change from
pinctrl_select_state() and move it pinctrl_commit_state(), while keeping
the p->state == state check in pinctrl_select_state() not to change the
caller assumptions. pinctrl_force_sleep() and pinctrl_force_default()
are updated to bypass the state check by calling pinctrl_commit_state().
[Linus Walleij]
The forced pin control states are currently only used in some pin
controller drivers that grab their own reference to their own pins.
This is equal to the pin control hogs: pins taken by pin control
devices since there are no corresponding device in the Linux device
hierarchy, such as memory controller lines or unused GPIO lines,
or GPIO lines that are used orthogonally from the GPIO subsystem
but pincontrol-wise managed as hogs (non-strict mode, allowing
simultaneous use by GPIO and pin control). For this case forcing
the state from the drivers' suspend()/resume() callbacks makes
sense and should semantically match the name of the function.
Fixes: 6e5e959dde ("pinctrl: API changes to support multiple states per device")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch adds tpu groups and function to r8a7743/r8a7791/r8a7793.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add i2c5 pin groups and function to r8a7745 PFC driver.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch adds tpu groups and function to r8a7745/r8a7794.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch adds PFC PWM[0123456] pin groups and functions, enabling
PWM on the r8a7794 and r8a7745.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
According to datasheet, we should use numbers for the pin naming
instead of letters. The patch here try to fix this to keep
the consistency.
This patch should not bring any functional change.
Fixes: 83c566806a ("pinctrl: meson-axg: Add new pinctrl driver for Meson AXG SoC")
Suggested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Guenter Roeck reported an interrupt storm on a prototype system which is
based on Cyan Chromebook. The root cause turned out to be a incorrectly
configured pin that triggers spurious interrupts. This will be fixed in
coreboot but currently we need to prevent the interrupt storm from
happening by masking all interrupts (but not GPEs) on those systems.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=197953
Fixes: bcb48cca23 ("pinctrl: cherryview: Do not mask all interrupts in probe")
Reported-and-tested-by: Guenter Roeck <linux@roeck-us.net>
Reported-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The AXP813 has only two GPIOs. GPIO0 can either be used as a GPIO, an
LDO regulator or an ADC. GPIO1 can be used either as a GPIO or an LDO
regulator.
Moreover, the status bit of the GPIOs when in input mode is not offset
by 4 unlike the AXP209.
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
To prepare for patches that will add support for a new PMIC that has a
different GPIO adc muxing value, add an adc_mux within axp20x_pctl
structure and use it.
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fabio Estevam