HIP04 was added out of order, but so was the previous HISI debug uart
support as well. Minor reshuffling of order.
Signed-off-by: Olof Johansson <olof@lixom.net>
- PM changes to make the code easier to use on newer SoCs
- PM changes for newer SoCs suspend and resume and wake-up events
- Minor clean-up to remove dead Kconfig options
Note that these have a dependency to the fixes-v3.18-not-urgent
tag and is based on a commit in that series.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUEhKGAAoJEBvUPslcq6VzURoP/3tM1iOFzQ83xe0ijEnHuUEz
To5DF1AgJ/l8a6H9FV9xDTn7SXjV8Fts0MrPwveGnKRUMmZfrUBedvWGM9NyyWm5
L7IJKHvSc7FAj7ee5crNobCYTrQ9THUlr8X1mLILFl5mTh2pDnm4ZRscHy+OxN0+
w97d/T5MrFhoCa8LXo8nGm7jROvayp+E0VTxjFdU07VKJK8xjd++M0B5U3pXsqCC
8VabNDt8VBK/SVCOKYn3tnNop1/9t9nSWfN18OAEaIS6rn5ZaQxXETKxyRWgjTvn
OVEgsazFiPVm87H3O6cj0BizOSXG2gMfBTECZwVPtavyQR2lb/YljHUQ5Z9/T4v9
x+nOWFxqVAr8OM1kKcatSMrZymY4AG5NdOmOgrAqKoQzWGGKhT3LcNz3Ecja25vX
ZWGYsJl6hbF4PPaCgKe8KGRISLuv1g1N4TI8ztsxELRzhClxhuaERt7TkdQRLGrH
emKSFP8Kkn6yrQy/RirOaXnwPWJRzuMrgpLuwDTKY6vY07MGk+nHkzF+2itKkvLB
CG/Tw29jUi9gnOU9QwjkpBiJxsHlgcO/XzSTGN89p6EjVylyqdCqkpO3MCfjPV7Q
kPap33Zx5SvxMMMSXRDKrrez533RfxBeTXkgT1O0fnR0r4fWYoc5+zL8Y02g10Wt
tZ4gZRYP68IuxzfPUAgJ
=LW8C
-----END PGP SIGNATURE-----
Merge tag 'soc-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
SoC related changes for omaps for v3.18 merge window:
- PM changes to make the code easier to use on newer SoCs
- PM changes for newer SoCs suspend and resume and wake-up events
- Minor clean-up to remove dead Kconfig options
Note that these have a dependency to the fixes-v3.18-not-urgent
tag and is based on a commit in that series.
* tag 'soc-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (514 commits)
ARM: OMAP5+: Reuse OMAP4 PM code for OMAP5 and DRA7
ARM: dts: OMAP3+: Add PRM interrupt
ARM: omap: Remove stray ARCH_HAS_OPP references
ARM: DRA7: Add hook in SoC initcalls to enable pm initialization
ARM: OMAP5: Add hook in SoC initcalls to enable pm initialization
ARM: OMAP5 / DRA7: Enable CPU RET on suspend
ARM: OMAP5 / DRA7: PM: Provide a dummy startup function for CPU hotplug
ARM: OMAP5 / DRA7: PM: Avoid all SAR saves
ARM: OMAP5 / DRA7: PM: Enable Mercury retention mode on CPUx powerdomains
ARM: OMAP5 / DRA7: PM / wakeupgen: Enables ES2 PM mode by default
ARM: OMAP5 / DRA7: PM: Set MPUSS-EMIF clock-domain static dependency
ARM: OMAP5 / DRA7: PM: Update CPU context register offset
ARM: AM437x: use pdata quirks for pinctrl information
ARM: DRA7: use pdata quirks for pinctrl information
ARM: OMAP5: use pdata quirks for pinctrl information
ARM: OMAP4+: PM: Use only valid low power state for CPU hotplug
ARM: OMAP4+: PM: use only valid low power state for suspend
ARM: OMAP4+: PM: Make logic state programmable
ARM: OMAP2+: powerdomain: introduce logic for finding valid power domain
ARM: OMAP2+: powerdomain: pwrdm_for_each_clkdm iterate only valid clkdms
...
OMAP4, OMAP5 and DRA7 share a lot of common logic and data structures.
These have been enabled in the previous patches, however, this also
means that OMAP5 or DRA7 only builds also need to build OMAP4 logic.
Update to reuse OMAP4 logic.
This fixes the 'undefined reference to 'omap4_pm_init_early'' in
OMAP5 or DRA7 only builds.
Fixes: 6af16a1dac ("ARM: DRA7: Add hook in SoC initcalls to enable pm initialization")
Fixes: 628ed47170 ("ARM: OMAP5: Add hook in SoC initcalls to enable pm initialization")
Reported-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
* Initial r8a7794 SoC support
* Support Cortex-A7 in shmobile_init_delay()
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUDnyTAAoJENfPZGlqN0++xcUP/RO2TIFpvKKQ69B8v7OJpPKJ
yaqZFsg5A0lTHos7as3/4osHQfUtp6dz0Ko9DZIs7EYQ7Xue0OoIJ48O/c9EaPJD
zLVvNYuh/LavXHeXnvKyp9ixYzY5f3A26+mx3PZAFJrmlaqAypt5STPNdqmf61ot
U/uEwhtXU2hDY0AW865RgvOESDWpRY+YjrVihMgW/EQE+Glq2U6mnmrjANglZyRv
/FnifymlhTByH81KauYqLTYbtdoAJFCvOa+ZHqLIZHqu7/K5G29b6TgnlbqanVBp
GFIxLVHFqppgyIbJqpmBqHRB5BLL1ISoAV5z5p7K6ujjz73yIMReBoCVP4rZ7ZXh
j+t4E7HyzaI5JoGJJyUEmtv4+gqQq486mDYEsJl3r/3ByLT52DglerAFnOhd1fmU
VBpFydYfOtpA9LtGJXlxTBDJOecP857Kv81agROLY+NID24dcq1lRImffq88poHQ
ck3DRSyagdZWWc7uGxhZqTltJufgazP7odya31roIC2C5q6j5kDON04inxzH0FBU
eqNhYEYYgBUYWUBje1cL50WuPboRdvV5kJjAspKNbLt8jAQ+mky9pZqoJbndRdNT
kg30WH2WXaMD+naQPh6g07kQPrmuwz0tOtIdcZ598T6k+tXGufwE6OPIR/LsxMIq
TSw0JlT6DO8XPSMMGMDs
=iaYv
-----END PGP SIGNATURE-----
Merge tag 'renesas-soc3-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
Pull "Third Round of Renesas ARM Based SoC Soc Updates for v3.18" from Simon Horman:
* Initial r8a7794 SoC support
* Support Cortex-A7 in shmobile_init_delay()
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'renesas-soc3-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Initial r8a7794 SoC support
ARM: shmobile: support Cortex-A7 in shmobile_init_delay()
In general Renesas hardware is not documented to the extent
where the relationship between IP blocks on different SoCs can be assumed
although they may appear to operate the same way. Furthermore the
documentation typically does not specify a version for individual
IP blocks. For these reasons a convention of using the SoC name in place
of a version and providing SoC-specific compat strings has been adopted.
Although not universally liked this convention is used in the bindings for
a number of drivers for Renesas hardware. The purpose of this patch is to
make use of the SoC-specific CMT compat string for the r8a7740 48-bit CMT
clock source.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
In general Renesas hardware is not documented to the extent
where the relationship between IP blocks on different SoCs can be assumed
although they may appear to operate the same way. Furthermore the
documentation typically does not specify a version for individual
IP blocks. For these reasons a convention of using the SoC name in place
of a version and providing SoC-specific compat strings has been adopted.
Although not universally liked this convention is used in the bindings for
a number of drivers for Renesas hardware. The purpose of this patch is to
make use of the SoC-specific CMT compat string for the r8a7779 TMU
clock source.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
In general Renesas hardware is not documented to the extent
where the relationship between IP blocks on different SoCs can be assumed
although they may appear to operate the same way. Furthermore the
documentation typically does not specify a version for individual
IP blocks. For these reasons a convention of using the SoC name in place
of a version and providing SoC-specific compat strings has been adopted.
Although not universally liked this convention is used in the bindings for
a number of drivers for Renesas hardware. The purpose of this patch is to
make use of the SoC-specific CMT compat string for the r8a7791 48-bit CMT
clock source.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
In general Renesas hardware is not documented to the extent
where the relationship between IP blocks on different SoCs can be assumed
although they may appear to operate the same way. Furthermore the
documentation typically does not specify a version for individual
IP blocks. For these reasons a convention of using the SoC name in place
of a version and providing SoC-specific compat strings has been adopted.
Although not universally liked this convention is used in the bindings for
a number of drivers for Renesas hardware. The purpose of this patch is to
make use of the SoC-specific CMT compat string for the r7s72100 MTU2
clock source.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
In general Renesas hardware is not documented to the extent
where the relationship between IP blocks on different SoCs can be assumed
although they may appear to operate the same way. Furthermore the
documentation typically does not specify a version for individual
IP blocks. For these reasons a convention of using the SoC name in place
of a version and providing SoC-specific compat strings has been adopted.
Although not universally liked this convention is used in the bindings for
a number of drivers for Renesas hardware. The purpose of this patch is to
make use of the SoC-specific CMT compat string for the r8a7790 48-bit CMT
clock source.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
When booting using the r8a7740/armadillo800eva using dt-reference:
* Use CCF to initialise clocks via DT
* Initialise timers via DT
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJT/BT6AAoJENfPZGlqN0++MPwQAIzGfi79jMY14Xep790KD17A
wvae1QGyLpIPH/nyVr6iEbHiX3YBfW4kcvrQ1GWOG19tFoWlc4fiOK1ZcCAnydFD
SU1lnkpT6+ZIEeFkdXwMyux2lVeaZSQHOInT7UYZnWLUhfkCkuf7IJNvrYNMGb+Z
3viXbRkqz1cz9nyIRDmryq0IZO8d7ZNFhOSdTTq3Rjzn32V68I2HZVGKOu00bI7J
UEpEXlPqAs8R90NkyLvoEaN3d0NHz6TrX8VqgWW6cNxu8Kv3OCLhkjmGdjmWXZ3P
SuVXJv37vcjkKXuclRVaPV8GcQgJZO34RSUpc0HMYJyutEp3ANLxujT7zFSwJEvK
vUZkPGpzWY9+icqfPOoGlEoGIcVGTnB1rH25ap5y/b7SnfNsw2dJyhx/Mr8nln2b
SwTMXxZZvP8V2qK7CrXU5TXnhl2nYJwvjU8ORhe3ZJrAOmrlfrBNFBTzm/8Txik7
/JUFjInTkOoLX4a0vjJlwc/rRAAe8jASmpWTC6N9mTzJhY7gySpXwxWOwT2f/+YR
otDz1JS4EpqRFiK3ptnPVJ7sVpamz5glCLCCZWMZdwWG7G1B+daXD2shTPk7aup5
EsN0YKIjMfdTL5sQcQIhS5Yoj/KJEhwkNny+EsMofExKZeQerqQT3SG9a798xxLR
8ACepiF2VECSLNCWvUKj
=uu7K
-----END PGP SIGNATURE-----
Merge tag 'renesas-r8a7740-ccf-and-timers-for-v3.18' into dt-timers-for-v3.18
Renesas ARM Based SoC R8a7740 CCF and Timers Updates for v3.18
When booting using the r8a7740/armadillo800eva using dt-reference:
* Use CCF to initialise clocks via DT
* Initialise timers via DT
Provide OMAP3, 4 and OMAP5 with interrupt number for PRM
And for DRA7, provide crossbar number for prm interrupt.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
OPP is now a normal kernel library selected by its users rather than a
feature that architectures need to enable so ARCH_HAS_OPP serves no
function any more - remove the selects.
Signed-off-by: Mark Brown <broonie@kernel.org>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
With consolidated code, now we can add the required hooks for
DRA7 to enable power management.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: minor modifications]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
With consolidated code, now we can add the required hooks for
OMAP5 to enable power management.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[nm@ti.com: minor rebase updates]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
On OMAP5 / DRA7, prevent a CPU powerdomain OFF and resulting MPU OSWR
and instead attempt a CPU RET and side effect, MPU RET in suspend.
NOTE: the hardware was originally designed to be capable of achieving
deep power states such as OFF and OSWR, however due to various issues
and risks, deepest valid state was determined to be CSWR - hence we use
the errata framework to handle this case.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: updates]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Dont assume that all OMAP4+ code will be able to use OMAP4 hotplug
logic. On OMAP5, DRA7, we do not need this in place yet, also,
currently the CPU startup pointer is located in omap4_cpu_pm_info
instead of cpu_pm_ops.
So, isolate the function to hotplug_restart pointer in cpu_pm_ops
where it should have belonged, initalize them as per valid startup
pointers for OMAP4430/60 as in current logic, however provide
dummy_cpu_resume to be the startup location as well.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[nm@ti.com: split this out of original code and isolate it]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Get rid of all assumptions about always having a sar base on *all*
OMAP4+ platforms. We dont need one on DRA7 and it is not necessary at
this point for OMAP5 either.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: Split and optimize]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
In addition to the standard power-management technique, the OMAP5 / DRA7
MPU subsystem also employs an SR3-APG (mercury) power management
technology to reduce leakage.
It allows for full logic and memories retention on MPU_C0 and MPU_C1 and
is controlled by the PRCM_MPU. Only "Fast-mode" is supported on the
OMAP5 and DRA7 family of processors.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[nm@ti.com: minor consolidation]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Enables MPUSS ES2 power management mode using ES2_PM_MODE in
AMBA_IF_MODE register.
0x0: OMAP5 ES1 behavior, CPU cores would enter and exit OFF mode together.
Broken! Fortunately, we do not support this anymore.
0x1: OMAP5 ES2, DRA7 behavior, CPU cores are allowed to enter/exit OFF mode
independently.
This is one time settings thanks to always ON domain.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[nm@ti.com: minor conflict resolutions, consolidation for DRA7]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
With EMIF clock-domain put under hardware supervised control, memory
corruption and untraceable crashes are observed on OMAP5. Further
investigation revealed that there is a weakness in the PRCM on this
specific dynamic depedency.
The recommendation is to set MPUSS static dependency towards EMIF
clock-domain to avoid issues. This recommendation holds good for DRA7
family of devices as well.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[rnayak@ti.com: DRA7]
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: conflict resolution, dra7]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
On OMAP5, RM_CPUi_CPUi_CONTEXT offset has changed. Update the code
so that same code works for OMAP4+ devices. DRA7 and OMAP5 have the same
context offset as well.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[rnayak@ti.com: for DRA7]
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: rebase, split/merge etc..]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Not all SoCs support OFF mode - for example DRA74/72. So, use valid
power state during CPU hotplug.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
We are using power domain state as RET and logic state as OFF. This
state is OSWR. This may not always be supported on ALL power domains. In
fact, on certain power domains, this might result in a hang on certain
platforms. Instead, depend on powerdomain data to provide accurate
information about the supported powerdomain states and use the
appropriate function to query and use it as part of suspend path.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Move the logic state as different for each power domain. This allows us
to customize the deepest power state we should target over all for each
powerdomain in the follow on patches.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
powerdomain configuration in OMAP is done using PWRSTCTRL register for
each power domain. However, PRCM lets us write any value we'd like to
the logic and power domain target states, however the SoC integration
tends to actually function only at a few discrete states. These valid
states are already in our powerdomains_xxx_data.c file.
So, provide a function to easily query valid low power state that the
power domain is allowed to go to.
Based on work originally done by Jean Pihet <j-pihet@ti.com>
https://patchwork.kernel.org/patch/1325091/ . There is no attempt to
create a new powerdomain solution here, except fixing issues seen
attempting invalid programming attempts. Future consolidation to the
generic powerdomain framework should consider this requirement as
well.
Similar solutions have been done in product kernels in the past such
as:
https://android.googlesource.com/kernel/omap.git/+blame/android-omap-panda-3.0/arch/arm/mach-omap2/pm44xx.c
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
No need to invoke callback when the clkdm pointer is NULL.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Update the power domain power states for final production chip
capability. OFF mode, OSWR etc have been descoped for various domains.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Allow the PRM interrupt information to be picked up from device tree.
OMAP3 may use legacy boot and needs to be compatible with old dtbs
(without interrupt populated), for these, we use the value which is
pre-populated.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
OMAP5 and DRA7 can now use pinctrl based I/O daisychain wakeup
capability. So, enable the support.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
"wkup" event at bit offset 0 exists only on OMAP3.
OMAP4430/60 PRM_IRQSTATUS_A9, OMAP5/DRA7 PRM_IRQSTATUS_MPU
register bit 0 is DPLL_CORE_RECAL_ST not wakeup event like OMAP3.
The same applies to AM437x as well.
Remove the wrong definition.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Allow the PRM interrupt information to be picked up from device tree.
the only exception is for OMAP4 which uses values pre-populated and allows
compatibility with older dtb.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
use the generic function to pick up the prm_instance for a generic logic
which can be reused from OMAP4+
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
PRM device instance can vary depending on SoC. We already handle the
same during reset of the device, However, this is also needed
for other logic instances. So, first abstract this out to a generic
function.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
by way of GPIO descriptors, avoiding any use of the GPIO
global numberspace.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUCXtyAAoJEEEQszewGV1zGLsQAKeUjWMSeSZj/6POdBUsAGz/
eDfVBdMBuc9X8jOupqW3fEyKnWAG0ItfHuKJ69k/z+E8qUuih3Op6Wzb3DTZl7KF
Vhqiw2Wxc+V+UuuQbGuHNStph8OlBdM1kct19S5nUScNE6eiyg14HGPKC9Pjn37X
Oz4OAnIUxuLOFSNRCujCO2Q9DCINRAmR5hzFrKw5rmYsk/ekFkZFmIwY4yjuHszE
3YxS7lbwyd9PgsFtKzFPCD2CaE+bg5XnW0og6u4fRx96uUZsFD3p1V0LXczicm5H
vcgUHeZS+cMWyuvwoA6ODr6tHILgNVofyqW9YyIRVTfH1FT2/dBh7/gmVsGoEbBd
Y2L75huOprHl6rgrt21zcIBQIY2S9GTBspXIhZBuRt4mhtUI/e4ahVvOP2CaZXtM
hz7csVH2VNuO5E2NYHTAm0jcWrrwrdtYKoiuAi0RGVRgZBkg9uYUDmlTKAclsORu
uH2MDx3+p8G74vgD6DCiaAep3OsS5PCEbECkSkym91y6ZbpuNh7VyhCKbAEw8q6C
+hVP/T7hydRD0EIxNkNB0M5Q/YarXVvrClcj2oXo2C1mTZFdQrTFMijpUhMxVgND
3QEhHZrS6k205LtuCaADgd5R4Qgf4LM0SdAigm1FwRUgoNlKiyONoOeY8UWQCdE0
fovRupLS65wD2Xur5M77
=/CT4
-----END PGP SIGNATURE-----
Merge tag 'integrator-for-v3.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/soc
Merge "single Integrator patch" from Linus Walleij:
This sets up the dynamically detected IM-PD1 GPIO lines
by way of GPIO descriptors, avoiding any use of the GPIO
global numberspace.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'integrator-for-v3.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
ARM: integrator: add MMCI device to IM-PD1
* Add r8a7794 support
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUA9NYAAoJENfPZGlqN0++T2EP/Akt8EMj8Wy0QQ51VLTqfEu5
YrA2UnZo927GaXuwqPnFcePz6ZR29Kq7HQAzJN7UwghPa18u5RkPxnxK+MBLldWF
87bd7urI1sr8TqG7Ilaxp9E2+RYhwBJc+n+cDJOwQHb/pdcVrIfgVc0YajsGpw8f
bSguW9UUfdLj+gz6pIO7uxtX+sS8Wt6CXwu/3a05I9puox4EmD/n+IWjD9K0Ckq4
EiNZKSquUnv0g4NOUleOll5EZ1HCaTM/YOylx+ePXXZ/hilXl8o8ncJwS9zzhFBy
ihFUqQ0j+JoCZRnSjOLfD7NoX0iqosRm/s60no7T8FhVwllIxgmwmMDxJx11J/u/
q0CH2YnzvE7ChqjK1fz/hm1JQJNACeok3inSXCsUdt8mle8LxxgxqfIGg0vsDc3L
0I0SGfJltxtj+pa/vSbta3OzGguux7WwOe7Llfg1ERUmJge1Ee+nPc6ExHUs1TZ+
Il8eirH45Oa9ONurQBwgtbCyWpAV7g3r97ije2dURRycatuq+svHMK41tJyd8vAo
YDMz1/yxS1YN+N5FnSc1xlpShj2WN6pU9gkA08XczLnOZzaNsTEoVtnofXOCJvaX
or8fJD2cm6rCEAnrUoVibGdJzbaR0pxO9iya8qNSE1PpWh2Dlj5aAM7y3zu1Oo6f
ffAPgjvbBxHAmnVqrIhV
=tvK/
-----END PGP SIGNATURE-----
Merge tag 'renesas-clk-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
Merge "Renesas ARM Based SoC Clk Updates for v3.18" from Simon Horman:
* Add r8a7794 support
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'renesas-clk-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
clk: shmobile: Add r8a7794 support
* Enable timers using DT when booting boards without Legacy-C code
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJT8+H9AAoJENfPZGlqN0++FWcP/jO8bI4iFQXzZS13a1IzehTy
8PW1d8wu7+9KMrUaSNRVSBk20U5xGrNgykzBbM/kyB4JDqBsc7d97zOEnus7x9WP
ujP6cD3TaiX3EDssS9UMcZJlT95PtcTEIicwMj38dflvM6JoU3Od08s15Fp3AiwB
XzhtCG8PvbVCe6RagglC/1g4r8GCB2cA0bBnyoybOoHGNZv+bpn9D5j/m6ltp2TH
f4sKuXrPQKGeOi4RKjSaCKnKqrRrfZ6S6fOZGjzZw9lSSw72EXVsE763IDFs8osd
Sdc4FKtcM2CaiL1/BuJ6NP5kYyMPHc37il+FbyYIOdi0l75RzKoMLRBcQjbgfUyy
3KahXSk3k8xv2qpCUoS2UKBeiCSc3ejs0AcOUD540igy1OuRRHQRrjHv5D2MJwjm
92W4/74hS0ihWTjIG9WQ0lIb2SQfBsUwpQwANN/9zR7cWnsSrPOowK0f+q8rPQXc
K2nrXis1YL2uU04JPU2BPAMtw/XdYzDADRfg+dSCKntdEC2MHvlkdqcxOYaoUM/3
8slW8hYxFo5vO1c5sYxGHd573i5JTKHhPOzrs/f4faw5/I1ZyiJotbfVt8//6K1D
ocnTxXZKzh5X0FcckEhdRyFa1QcHk0v5PqsqmQAYYjXmq5+3HV7GAskGL9tUuOq0
97qsr4ScwT63EBl9yFZY
=cyP9
-----END PGP SIGNATURE-----
Merge tag 'renesas-dt-timers-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
Merge "Renesas ARM Based SoC DT Timers Updates for v3.18" from Simon Horman:
* Enable timers using DT when booting boards without Legacy-C code
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'renesas-dt-timers-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: genmai-reference: Enable MTU2 in device tree
ARM: shmobile: r7s72100: Add MTU2 device to DT
ARM: shmobile: marzen-reference: Enable TMU0 in device tree
ARM: shmobile: koelsch-reference: Enable CMT0 in device tree
ARM: shmobile: lager-reference: Enable CMT0 in device tree
ARM: shmobile: r8a7779: Add TMU devices to DT
ARM: shmobile: r8a7791: Add CMT devices to DT
ARM: shmobile: r8a7790: Add CMT devices to DT
Conflicts:
arch/arm/mach-shmobile/setup-r8a7779.c
Olof Johansson