Commit Graph

12939 Commits

Author SHA1 Message Date
Dave Airlie cf0613d242 Merge branch 'gma500-next' of git://github.com/patjak/drm-gma500 into drm-next
SDVO support for minnowboard

* 'gma500-next' of git://github.com/patjak/drm-gma500:
  drm/gma500/mrst: Add SDVO to output init
  drm/gma500/mrst: Don't blindly guess a mode for LVDS
  drm/gma500/mrst: Setup GMBUS for oaktrail/mrst
  drm/gma500/mrst: Replace WMs and chickenbits with values from EMGD
  drm/gma500/mrst: Add aux register writes to SDVO
  drm/gma500/mrst: Properly route oaktrail hdmi hooks
  drm/gma500/mrst: Add aux register writes when programming pipe
  drm/gma500/mrst: Add SDVO clock calculation
  drm/gma500: Add aux device support for gmbus
  drm/gma500: Add support for aux pci vdc device
  drm/gma500: Add chip specific sdvo masks
  drm/gma500: Add Minnowboard to the IS_MRST() macro
2013-11-11 07:25:33 +10:00
Laurent Pinchart 8d01e1ef67 drm: shmob_drm: Convert to clk_prepare/unprepare
Turn clk_enable() and clk_disable() calls into clk_prepare_enable() and
clk_disable_unprepare() to get ready for the migration to the common
clock framework.

Cc: David Airlie <airlied@linux.ie>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-10 18:48:38 +10:00
Dave Airlie ab0169bb5c Merge tag 'bdw-stage1-2013-11-08-v2' of git://people.freedesktop.org/~danvet/drm-intel into drm-next
So here's the Broadwell pull request. From a kernel driver pov there's
two areas with big changes in Broadwell:
- Completely new enumerated interrupt bits. On the plus side it now looks
  fairly unform and sane.
- Completely new pagetable layout.

To ensure minimal impact on existing platforms we've refactored both the
irq and low-level gtt handling code a lot in anticipation of the bdw push.
So now bdw enabling in these areas just plugs in a bunch of vfuncs.

Otherwise it's all fairly harmless adjusting of switch cases and
if-ladders to shovel bdw into the right blocks. So minimized impact on
existing platforms. I've also merged the bdw-stage1 branch into our
-nightly integration branch for the past week to make sure we don't break
anything.

Note that there's still quite a flurry or patches floating around, but
I've figured I'll push this out. I plan to keep the bdw fixes separate
from my usual -fixes stream so that you can reject them easily in case it
still looks like too much churn. Also, bdw is for now hidden behind the
preliminary hw enabling module option. So there's no real pressure to get
follow-up patches all into 3.13.

* tag 'bdw-stage1-2013-11-08-v2' of git://people.freedesktop.org/~danvet/drm-intel: (75 commits)
  drm/i915: Mask the vblank interrupt on bdw by default
  drm/i915: Wire up cpu fifo underrun reporting support for bdw
  drm/i915: Optimize gen8_enable|disable_vblank functions
  drm/i915: Wire up pipe CRC support for bdw
  drm/i915: Wire up PCH interrupts for bdw
  drm/i915: Wire up port A aux channel
  drm/i915: Fix up the bdw pipe interrupt enable lists
  drm/i915: Optimize pipe irq handling on bdw
  drm/i915/bdw: Take render error interrupt out of the mask
  drm/i915/bdw: Add BDW PCH check first
  drm/i915: Use hsw_crt_get_config on BDW
  drm/i915/bdw: Change dp aux timeout to 600us on DDIA
  drm/i915/bdw: Enable trickle feed on Broadwell
  drm/i915/bdw: WaSingleSubspanDispatchOnAALinesAndPoints
  drm/i915/bdw: conservative SBE VUE cache mode
  drm/i915/bdw: Limit SDE poly depth FIFO to 2
  drm/i915/bdw: Sampler power bypass disable
  ddrm/i915/bdw: Disable centroid pixel perf optimization
  drm/i915/bdw: BWGTLB clock gate disable
  drm/i915/bdw: Implement edp PSR workarounds
  ...
2013-11-10 18:35:33 +10:00
Dave Airlie 8d0a221593 Merge branch 'drm-next-3.13' of git://people.freedesktop.org/~agd5f/linux into drm-next
A few more patches for 3.13.  The big one here is Hawaii support.
I wanted to get that out sooner, but was sick earlier this week.  That
said, it's mostly self contained, so it shouldn't impact other asics.
The rest are just bug fixes and a merge fix.

* 'drm-next-3.13' of git://people.freedesktop.org/~agd5f/linux: (23 commits)
  Revert "drm/radeon/audio: don't set speaker allocation on DCE4+"
  drm/radeon/audio: improve ACR calculation
  drm/radeon/audio: correct ACR table
  drm/radeon: fix mismerge of drm-next with 3.12
  drm/radeon: add pci ids for hawaii
  drm/radeon: fill in radeon_asic_init for hawaii
  drm/radeon: modesetting updates for hawaii
  drm/radeon: atombios.h updates for hawaii
  drm/radeon: update cik_get_csb_buffer for hawaii
  drm/radeon: add hawaii dpm support
  drm/radeon/cik: add hawaii UVD support
  drm/radeon: update firmware loading for hawaii
  drm/radeon: update rb setup for hawaii
  drm/radeon: add golden register settings for hawaii
  drm/radeon: update cik_tiling_mode_table_init() for hawaii
  drm/radeon: minor updates to cik.c for hawaii
  drm/radeon: update cik_gpu_init() for hawaii
  drm/radeon: add Hawaii chip family
  drm/radeon: fix-up some float to fixed conversion thinkos
  drm/radeon: use HDP_MEM_COHERENCY_FLUSH_CNTL for sdma as well
  ...
2013-11-10 18:33:17 +10:00
Dave Airlie c4b3a81f4e Merge branch 'msm-next' of git://people.freedesktop.org/~robclark/linux into drm-next
prime support, inactive rework, render nodes
* 'msm-next' of git://people.freedesktop.org/~robclark/linux:
  drm/msm/mdp4: page_flip cleanups/fixes
  drm/msm: EBUSY status handling in msm_gem_fault()
  drm/msm: rework inactive-work
  drm/msm: add plane support
  drm/msm: resync generated headers
  drm/msm: support render nodes
  drm/msm: prime support
2013-11-10 18:27:31 +10:00
Dave Airlie 98706ea99f drm/nouveau: fix 32-bit build
This uses the proper div macro.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-10 09:24:24 +10:00
Jani Nikula 1dca220b2b drm/i915/opregion: fix build error on CONFIG_ACPI=n
Fix CONFIG_ACPI=n build fail

  CC      drivers/gpu/drm/i915/intel_opregion.o
drivers/gpu/drm/i915/intel_opregion.c: In function ‘intel_opregion_setup’:
drivers/gpu/drm/i915/intel_opregion.c:879:2: error: ‘asle_work’ undeclared (first use in this function)
drivers/gpu/drm/i915/intel_opregion.c:879:2: note: each undeclared identifier is reported only once for each function it appears in
make[4]: *** [drivers/gpu/drm/i915/intel_opregion.o] Error 1

introduced in
commit 91a60f2071
Author: Jani Nikula <jani.nikula@intel.com>
Date:   Thu Oct 31 18:55:48 2013 +0200

    drm/i915: move opregion asle request handling to a work queue

Reported-by: Jim Davis <jim.epost@gmail.com>
Reference: http://lkml.kernel.org/r/CA+r1ZhjcFpr5KKVX0pLCOP8cAyZoiYO=UyqYMJtNSV-Kt_p7xQ@mail.gmail.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 19:32:52 +01:00
Alex Deucher 28ed756f1f Revert "drm/radeon/audio: don't set speaker allocation on DCE4+"
This reverts commit 555b1b651a.

Let's try this again for 3.13.  It's required for proper
interaction with alsa.  Was disabled previously in 3.12
to be on the safe side since it caused problems on older
asics.
2013-11-08 13:07:51 -05:00
Pierre Ossman a2098250fb drm/radeon/audio: improve ACR calculation
In order to have any realistic chance of calculating proper
ACR values, we need to be able to calculate both N and CTS,
not just CTS. We still aim for the ideal N as specified in
the HDMI spec though.

bug:
https://bugs.freedesktop.org/show_bug.cgi?id=69675

Signed-off-by: Pierre Ossman <pierre@ossman.eu>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08 13:06:33 -05:00
Pierre Ossman 3e71985f24 drm/radeon/audio: correct ACR table
The values were taken from the HDMI spec, but they assumed
exact x/1.001 clocks. Since we round the clocks, we also need
to calculate different N and CTS values.

Note that the N for 25.2/1.001 MHz at 44.1 kHz audio is out of
spec. Hopefully this mode is rarely used and/or HDMI sinks
tolerate overly large values of N.

bug:
https://bugs.freedesktop.org/show_bug.cgi?id=69675

Signed-off-by: Pierre Ossman <pierre@ossman.eu>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08 13:05:27 -05:00
Alex Deucher e31fadd372 drm/radeon: fix mismerge of drm-next with 3.12
Audio is enabled by default now.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08 13:03:47 -05:00
Ville Syrjälä 00fe639a56 drm/i915: Make AGP support optional
We only depend on the intel-gtt module for GTT frobbign on older gens.
The intel_agp module is optional, except for UMS and some old XvMC
userland on gen3. So make AGP support optional. As before, we will
fail the i915 init for UMS and gen3 KMS the same as before if
intel_agp isn't around.

intel-gtt.c is left with a somewhat ugly ifdef mess, but I'm going
to save that for a later cleaning.

At least my gen2 still works with the patch and CONFIG_AGP=n.

v2: Make i915 depend on X86 and PCI, and intel-gtt depend on PCI

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:37:32 +01:00
Alex Deucher 41971b37d1 drm/radeon: fill in radeon_asic_init for hawaii
Fill in gpu details for hawaii.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08 12:33:47 -05:00
Alex Deucher 7eeeabfcce drm/radeon: modesetting updates for hawaii
Uses the same code as bonaire.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08 12:33:46 -05:00
Alex Deucher 60669d56f5 drm/radeon: atombios.h updates for hawaii
This updates atombios.h with the latest changes
required for hawaii.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08 12:33:45 -05:00
Alex Deucher bbfe90bd4e drm/radeon: update cik_get_csb_buffer for hawaii
Set the PA_SC_RASTER_CONFIG[_1] registers for hawaii.
The rest is the same as the other asics.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08 12:33:45 -05:00
Alex Deucher 2d40038d3f drm/radeon: add hawaii dpm support
This updates the CI dpm (dynamic power management)
support for hawaii.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08 12:33:44 -05:00
Alex Deucher 4256331ae9 drm/radeon/cik: add hawaii UVD support
Has same version of UVD as other CIK parts.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08 12:33:43 -05:00
Alex Deucher d47756556d drm/radeon: update firmware loading for hawaii
This just updates the firmware loading functions
to look for the appropriate firmware files for
hawaii.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08 12:33:43 -05:00
Alex Deucher fc821b70b0 drm/radeon: update rb setup for hawaii
The formula needs to be adjusted since there are 4 RBs
per SH rather than 2 as on previous asics.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08 12:33:42 -05:00
Alex Deucher 8efff33742 drm/radeon: add golden register settings for hawaii
The golden register settings are optimal settings for
certain registers from the hardware team.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08 12:33:41 -05:00
Alex Deucher 21e438af64 drm/radeon: update cik_tiling_mode_table_init() for hawaii
Hawaii uses a different tiling configuration.  Add support
for it.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08 12:33:41 -05:00
Alex Deucher 939c0d3c08 drm/radeon: minor updates to cik.c for hawaii
Skip programming a register that was removed and
adjust the mask of the VM client status.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08 12:33:40 -05:00
Alex Deucher b496038bd4 drm/radeon: update cik_gpu_init() for hawaii
This adds the hawaii asic specific configuration
details.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08 12:33:39 -05:00
Alex Deucher 3bf599e8a2 drm/radeon: add Hawaii chip family
Hawaii is a new CI-based dGPU.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08 12:33:39 -05:00
Alex Deucher 1cd73ff70d drm/radeon: fix-up some float to fixed conversion thinkos
Spotted by Brad Smith when porting to OpenBSD.

Noticed-by: Brad Smith <brad@comstyle.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08 12:33:38 -05:00
Alex Deucher d45fd24dd3 drm/radeon: use HDP_MEM_COHERENCY_FLUSH_CNTL for sdma as well
The new HDP flush method doesn't seem to work reliably on
sDMA either, so use the old method here too.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08 12:33:37 -05:00
Ilija Hadzic 520a8718fe drm/radeon/kms: add crtc_disable function for legacy crtc
To plug the VRAM memory leak (see previous patch for
details) we must unpin the frame buffer when disabling the
CRTC. This warrants the addition of disable function for legacy
CRTC, which puts the CRTC in DPMS-OFF state and unpins the
frame buffer if there is one associated with the CRTC.

Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08 12:33:37 -05:00
Ilija Hadzic 75b871e2d8 drm/radeon/kms: unpin fb in atombios crtc disable
When drm_helper_disable_unused_functions calls disable
function of the CRTC, it also sets the crtc->fb pointer
to NULL. This can later (when the mode on that CRTC is setup
again from user space) cause ***_do_set_base functions to
"think" that there is no old buffer and skip the unpinning
code. Consequently, the buffer that has been NULL-ified in
drm_helper_disable_unused_functions will never be unpinned
causing a leak in VRAM.

This patch plugs the leak by unpinning the frame buffer
in crtc_disable function.

Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08 12:33:36 -05:00
Anssi Hannula 0f57bca922 drm/radeon/audio: fix missing multichannel PCM SAD in some cases
The current code writing SADs to the audio registers seems to assume
that there is at most a single SAD per audio format.

However, that is not the case. Especially for PCM it is somewhat common
for sinks to have two SADs, one for 8-channel and one for 2-channel
audio, which may have different supported sample rates (i.e. the sink
supports stereo audio at higher sample rates than multichannel audio).

Because of this, only the 2-channel SAD may be used if it appears before
the 8-channel SAD. Unless other SADs require otherwise, this may cause
the ALSA HDA driver to allow stereo playback only.

Fix the code to pick the PCM SAD with the highest number of channels,
while merging the rate masks of PCM SADs with lower amount of channels
into the additional stereo rate mask byte.

Technically there are even more cases to handle (multiple non-PCM SADs
of the same type, more than two PCM SADs with varying channel counts,
etc), but those have not actually been encountered in the field and
handling them would be non-trivial.

Example affected EDID from Onkyo TX-SR674 specifying 192kHz stereo
support and 96kHz 8-channel support (and other 8-channel compressed
formats):
00ffffffffffff003dcb010000000001
ffff0103800000780a0dc9a057479827
12484c00000001010101010101010101
010101010101011d8018711c1620582c
2500c48e2100009e011d007251d01e20
6e285500c48e2100001e000000fc0054
582d53523637342020202020000000fd
00313d0f2e08000a202020202020019b
02032f724f8504030f0e07069413121e
1d1615012f097f070f1f071707503707
503f07c0834f000066030c00ffff808c
0ad08a20e02d10103e9600c48e210000
18011d80d0721c1620102c2580c48e21
00009e011d00bc52d01e20b8285540c4
8e2100001e8c0ad090204031200c4055
00c48e210000180000000000000000a8

Signed-off-by: Anssi Hannula <anssi.hannula@iki.fi>
Tested-by: Andre Heider <a.heider@gmail.com>
Cc: Rafał Miłecki <zajec5@gmail.com>
Acked-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08 12:33:35 -05:00
Daniel Vetter 13b3a0a776 drm/i915: Mask the vblank interrupt on bdw by default
Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:14 +01:00
Daniel Vetter 38d83c96a3 drm/i915: Wire up cpu fifo underrun reporting support for bdw
HW engineers have listened and given us again a real interrupt with
masking and status regs. Yay!

For consistency with other platforms call the #define FIFO_UNDERRUN.
Eventually we also might need to have some enable/disable functions
for bdw display interrupts, but for now open-coding seems to be good
enough.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:13 +01:00
Daniel Vetter 7167d7c677 drm/i915: Optimize gen8_enable|disable_vblank functions
Let's cache the IMR value like on other platforms. This is needed to
implement the underrun reporting since then we'll have two places that
change the same register at runtime.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:13 +01:00
Daniel Vetter 0fbe7870d7 drm/i915: Wire up pipe CRC support for bdw
The layout of the CRC registers is the same as on hsw, only the
interrupt handling has changed a bit. So trivial to wire up, yay!

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:12 +01:00
Daniel Vetter 92d03a8048 drm/i915: Wire up PCH interrupts for bdw
Gives us hotplug, gmbus, dp aux and south errors (underrun
reporting!).

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:12 +01:00
Daniel Vetter 6d766f022a drm/i915: Wire up port A aux channel
Useful for dp aux to work better. Also stop enabling the port A
hotplug event - eDP panels are expected to fire that interupt and
we're not really ready to deal with them. This is consistent with how
we handle port A on ilk-hsw.

The more important bit is that we must delay the enabling of hotplug
interrupts until all the encoders are fully set up. But we need irq
support earlier than that, hence hotplug interrupts can only be
enabled in the ->hpd_irq_setup callback.

v2: Drop the _HOTPLUG, it isn't (Ville).

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:11 +01:00
Daniel Vetter 30100f2bea drm/i915: Fix up the bdw pipe interrupt enable lists
- Pipe underrun can't just be enabled, we need some support code like
  on ilk-hsw to make this happen. So drop it for now.
- CRC error is a special mode of the CRC hardware that we don't use,
  so again drop it. Real CRC support for bdw will be added later.
- All the other error bits are about faults, so rename the #define and
  adjust the output.

v2: Use pipe_name as pointed out by Ville. Ville's comment was on a
previous patch, but it was easier to squash in here.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:11 +01:00
Daniel Vetter c42664cceb drm/i915: Optimize pipe irq handling on bdw
We have a per-pipe bit in the master irq control register, so use it.
This allows us to drop the masks for aggregate interrupt bits and be a
bit more explicit in the code. It also removes one indentation level.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:10 +01:00
Daniel Vetter 40c499f93f drm/i915/bdw: Take render error interrupt out of the mask
The handling of the error interrupts isn't wired up at all. And it
hasn't been ever since ilk happened, so don't bother.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:10 +01:00
Ben Widawsky e76e063486 drm/i915/bdw: Add BDW PCH check first
Early platforms use the same PCH as HSW, and to avoid triggering the
!ULT, and !HSW warnings, simply put it first in the search.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:09 +01:00
Ville Syrjälä a29857914d drm/i915: Use hsw_crt_get_config on BDW
Broadwell should also use hsw_crt_get_config(). Just move the
function pointer assignment to the if HAS_DDI block we already
have there.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:09 +01:00
Ben Widawsky a81a507d48 drm/i915/bdw: Change dp aux timeout to 600us on DDIA
Cc: Art Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:07 +01:00
Ville Syrjälä b42c60090c drm/i915/bdw: Enable trickle feed on Broadwell
Like on HSW, trickle feed should always be enabled on BDW.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:07 +01:00
Ben Widawsky 4c2e7a5f64 drm/i915/bdw: WaSingleSubspanDispatchOnAALinesAndPoints
Implement WaSingleSubspanDispatchOnAALinesAndPoints

BDW-A workaround.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:06 +01:00
Ben Widawsky a75f36283d drm/i915/bdw: conservative SBE VUE cache mode
Hold vertex data in cache until last reference

BDW-A workaround

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:06 +01:00
Ben Widawsky 7f88da0cf6 drm/i915/bdw: Limit SDE poly depth FIFO to 2
BDW-A workaround

BDW Bug #1899155

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:05 +01:00
Ben Widawsky bf66347cd3 drm/i915/bdw: Sampler power bypass disable
BDW-A workaround.

BDW Bug #1899812

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:05 +01:00
Ben Widawsky fd392b6003 ddrm/i915/bdw: Disable centroid pixel perf optimization
BDW-A workaround

BDW Bug #1899532

v2: WARN on when not using preliminary HW support

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Jesse Barnes <jbarnes@virtuosugeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:04 +01:00
Ben Widawsky 4afe8d3347 drm/i915/bdw: BWGTLB clock gate disable
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Jesse Barnes <jbarnes@virtuosugeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:04 +01:00
Ben Widawsky fe4ab3ceef drm/i915/bdw: Implement edp PSR workarounds
This implements a workaround for PSR dealing with some vblank issue.

WaPsrDPAMaskVBlankInSRD && WaPsrDPRSUnmaskVBlankInSRD

v2: forgot to git add bogus whitespace fix

v3: Update with workaround names.
Use for_each_pipe() and CHICKEN_PIPESL_1(pipe) macro (Ville)

Cc: Art Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Jesse Barnes <jbarnes@virtuosugeek.org>
[danvet: Kill redundant IS_BDW check and remove the copious amount of
uneeded lines added.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:03 +01:00
Ben Widawsky e64c4a1b8a drm/i915/bdw: Disable semaphores
We've done insufficient testing on them thus far, so keep them disabled
until we do test.

v2: Use WARN when not enabling preliminary HW support as this should
only be disabled for that case.

v3: Rip out the now useless (and really noisy) DRM_INFO output.

Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Jesse Barnes <jbarnes@virtuosugeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:03 +01:00
Ben Widawsky 6edee7f3e7 drm/i915/bdw: Create a separate BDW rps enable
This is mostly what we have for HSW with the exceptions of:
no writes:
  GEN6_RC1_WAKE_RATE_LIMIT
  GEN6_RC6pp_WAKE_RATE_LIMIT
  GEN6_RC1e_THRESHOLD
  GEN6_RC6p_THRESHOLD
  GEN6_RC6pp_THRESHOLD

GEN6_RP_DOWN_TIMEOUT - use 1s instead of 1.28s

Don't try to overclock, or program ring/IA frequency tables since we
don't quite have sufficient docs yet.

NOTE: These values do not reflect the changes made recently by Chris.
Since we have no evidence yet what the proper way to tweak for this
platform is, I think it is good to go, and can be optimized by Chris, or
whomever, later.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
[danvet: Drop spurious hunk and drop TODO - having per-platform rps
register frobbing code is in my opinion preferred, now that all the
infrastructure functions are extracted.]
Reviewed-by: Jesse Barnes <jbarnes@virtuosugeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:02 +01:00
Damien Lespiau e3c3357863 drm/i915/bdw: Broadwell has a max port clock of 300Mhz on HDMI
Just like HSW.

This means we can scan out a mode with a 300Mhz pixel clock with a depth
of 24 bits, but only a 200Mhz one with a 36bits depth.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:01 +01:00
Ben Widawsky 0f161f7075 drm/i915/bdw: Don't wait for c0 threads on forcewake
It's no longer a required workaround on BDW.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
[danvet: Move compile fix from a later patch to this one.]
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:01 +01:00
Ben Widawsky 46c764d41f drm/i915/bdw: Use HSW formula for ring freq scaling
The current formula we use for HSW is not what is in current docs.
However, changing to the HSW formula on my HSW does not improve power
usage, and decreases performance by about 5% in limited xonotic testing.

For gen8, until we know otherwise, or run experiments, let's use
the HSW formula - which should be the same used in the Windows driver
(and thus help make an apples-applies comparison) on gen8.

v2: Use >= 8 instead of > 7 to be consistent with all other gen
checks.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:00 +01:00
Ben Widawsky ed8546ac1f drm/i915/bdw: Support eDP PSR
Broadwell PSR support is a superset of Haswell. With this simple
register base calculation, everything that worked on HSW for eDP PSR
should work on BDW.

Note that Broadwell provides additional PSR support. This is not
addressed at this time.

v2: Make the HAS_PSR include BDW

v3: Use the correct offset (I had incorrectly used one from my faulty
brain) (Art!)

v4: It helps if you git add

v5: Be explicit about not setting min link entry time for BDW. This
should be no functional change over v4 (Jani)

Reviewed-by: Art Runyan <arthur.j.runyan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:10:00 +01:00
Ben Widawsky 2a114cc1b9 drm/i915/bdw: Use The GT mailbox for IPS enable/disable
v2: Squash in fixup from Ben to synchronize the GT mailbox commands.

CC: Art Runyan <arthur.j.runyan@intel.com>
Reviewed-by: Art Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:59 +01:00
Ville Syrjälä 416f4727ab drm/i915/bdw: Add Broadwell display FIFO limits
Broadwell has bigger display FIFOs than Haswell. Otherwise the
two are very similar.

v2: Fix FBC WM_LP shift for BDW

v3: Rebase on top of the big Haswell wm rework.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v2)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:59 +01:00
Paulo Zanoni 77d8d00944 drm/i915/bdw: check DPD on port D when setting the DDI buffers
Use the eDP values on platforms where port D is eDP. This doesn't
affect Haswell since it uses the same DDI buffer values for eDP and
DP.

Reviewed-by: Art Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:58 +01:00
Paulo Zanoni bafb655367 drm/i915/bdw: BDW also has only 2 FDI lanes
So treat it like Haswell.

Reviewed-by: Art Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:58 +01:00
Paulo Zanoni 8f93f4f1e8 drm/i915/bdw: add support for BDW DP voltage swings and pre-emphasis
They're not the same as the Haswell ones.

Reviewed-by: Art Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Todd Previte <tprevite@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:57 +01:00
Paulo Zanoni 300644c7dc drm/i915/bdw: add BDW DDI buf translations for eDP
Broadwell has different DDI buffer translations for eDP and DP, so add
support for the missing eDP and keep Haswell the same.

A future patch addresses the suggestion from Art to check for eDP on
port D and use the eDP values there, too.

v2: Make checkpatch happy.

Reviewed-by: Art Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:57 +01:00
Art Runyan e58623cb65 drm/i915/bdw: Add BDW DDI buffer translation values
Many of the DDI buffer translation values have changed for BDW.
Add new translation tables and selection between HSW and BDW.

v2: s/BUG/WARN/ to avoid breaking future GENs.

v3: Rebase on top of the hdmi translation table changes.

v4: Fix up the multiline comment while at it.

Signed-off-by: Art Runyan <arthur.j.runyan@intel.com> (v2)
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:56 +01:00
Ben Widawsky 50ed5fbd9d drm/i915/bdw: Implement WaSwitchSolVfFArbitrationPriority
GEN8 also needs this workaround.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
[danvet: Add a generic comment that we need to recheck all these w/a.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:55 +01:00
Ville Syrjälä 6bbfa1c5b6 drm/i915/bdw: Use pipe CSC on Broadwell
Route cursor and sprite data through the pipe CSC unit on BDW.
Primary plane data is already sent through the pipe CSC.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:55 +01:00
Paulo Zanoni e39bf98a91 drm/i915/bdw: get the correct LCPLL frequency on Broadwell
v2: Rebased onto Paulo's MHz->kHz change.

v3: Rebased on top of the Haswell pc8+ adjustements.

v4: Use the exact 337.5MHz clock, should have been done as part of v2.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:54 +01:00
Paulo Zanoni 756f85cffe drm/i915/bdw: Broadwell has PIPEMISC
And it inherits some bits from the previous TRANS_CONF (aka PIPE_CONF
on previous gens).

v2: Rebase on to of the pipe config bpp handling rework.

v3: Rebased on top of the pipe_config->dither refactoring.

v4: Drop the read-modify-write cycle for PIPEMISC, similarly to how we
now also build up PIPECONF completely ourselves - keeping around
random stuff set by the BIOS just isn't a good idea. I've checked BDW
BSpec and we already set all relevant bits.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:54 +01:00
Paulo Zanoni c7670b1098 drm/i915/bdw: on Broadwell, the panel fitter is on the pipe
So you can use the panel fitter while the power well is disabled and
you also don't need to set the "pipe" bit.

v2: Rebased on top of Jesse's pfit refactor, which moved pfit state
into the pipe_config.

v3: Rebase on top of the latest Haswell/panel fitter rework, which
neatly resolves a FIXME we have in this patch here:

v4: Rebase on top of the new power domain framework.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:53 +01:00
Paulo Zanoni 018f52c9c3 drm/i915/bdw: pretend we have LPT LP on Broadwell
The platforms we currently have all have LPT LP on them. As such, we
have no way to identify the new WPT PCH that will ship with Broadwell.

NOTE: For all purposes relevant to the driver that this point, LPT and
WPT are equivalent. Therefore there should be no need to actually change
this for some time.

v2: Don't assign dev_priv->num_pch_pll any more.

v3: Rebase on top of the PCH detection changes for virtualized
enviroments.

v4: Wrote commit message

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v3)
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:53 +01:00
Paulo Zanoni 6745a2ceaa drm/i915/bdw: Broadwell also has the "power down well"
Just like Haswell, but with the small twist that the panel fitter for pipe A is
now also in the always-on power well.

v2: Use the new HAS_POWER_WELL macro.

v3: Rebase on top of intel_using_power_well patches.

v4: This time actually update the PFIT check correctly so that the
pipe A pfit is in the always-on domain.

v5: Rebase on top of the VGA power domain addition.

v6: Rebase on top of the new power domain infrastructure. Also pimp the commit
message a bit while at it.

v7: Use IS_BROADWELL instead of IS_GEN8 (Ville).

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:52 +01:00
Paulo Zanoni b3dc685e2f drm/i915/bdw: add Broadwell sprite/plane/cursor checks
Just make Broadwell follow the same code paths as Haswell here,
instead of running code for the even-older platforms.

v2: Shuffle around Ben's vma prep work.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:52 +01:00
Damien Lespiau 4b30553d89 drm/i915/bdw: Broadwell has 3 pipes
v2: Rebase (Paulo Zanoni)

v3: Rebase on top of num_pipes having moved to intel_device_info.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v1)
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v2)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:51 +01:00
Paulo Zanoni 4e8058a20a drm/i915/bdw: add IS_BROADWELL macro
For now it's just equivalent to IS_GEN8, but in the future we might
want to change that (e.g., on Gen 7 we have IS_VALLEYVIEW,
IS_IVYBRIDGE and IS_HASWELL).

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:51 +01:00
Ben Widawsky 780f18c84c drm/i915/bdw: BSD init for gen8 also
This was an oversight and should have been in a previous series
somewhere.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:50 +01:00
Ben Widawsky 77df677291 drm/i915/bdw: ppgtt info in debugfs
It's not so much that the information is terribly useful, but rather
that the gen6/7 information is completely useless.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:50 +01:00
Ville Syrjälä b42218c19f drm/i915/bdw: Don't muck with gtt_size on Gen8 when PPGTT setup fails
v2: Resolve rebase conflicts and switch to gen < 8 color for GenX
checking.

v3: Rebase on top of the address space refactoring.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:49 +01:00
Ben Widawsky a5f3d68e2e drm/i915/bdw: Render ring flushing
PIPE_CONTROL added the high address dword. I'm not sure how the
simulator let me get away with this. I've explicitly left out all the
workarounds from Gen7 because in the minimal digging that I did, most
don't seem necessary, and the simulator doesn't complain without them

Note that BLT and BSD ring commands had already been updated previously.
Just render/pipe_control should have been broken.

v2: Squash in a fixup from Ville to follow the recent IVB PIPE_CONTROL
updates: "BDW uses the IVB PIPE_CONTROL style for specifying GTT vs.
PPGTT for the PIPE_CONTROL QW/DW write."

v3: Rebase on top of Chris' cleanup to have an explicit ring->scratch
buffer object instead of an opaque ring->private where everyone stores
the same stuff inside.

Reported-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net> (for the fixup)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:49 +01:00
Ben Widawsky 28cf541543 drm/i915/bdw: unleash PPGTT
v2: Squash in fix from Ben: Set PPGTT batches as necessary

This fixes the regression in the last couple of days when we enabled
PPGTT.

v3: Squash in fixup to still use GTT for secure batches from Ville:

BDW doesn't have a separate secure vs. non-secure bit in
MI_BATCH_BUFFER_START. So for secure batches we have to simply
leave the PPGTT bit unset. Fortunately older generations (except
HSW) had similar limitations so execbuffer already creates a GTT
mapping for all secure batches.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:48 +01:00
Ben Widawsky 94e409c144 drm/i915/bdw: Implement PPGTT enable
Legacy PPGTT on GEN8 requires programming 4 PDP registers per ring.
Since all rings are using the same address space with the current code
the logic is simply to program all the tables we've setup for the PPGTT.

v2: Turn on PPGTT in GFX_MODE

v3: v2 was the wrong patch

v4: Resolve conflicts due to patch series reordering.

v5: Squash in fixup from Ben: Use LRI to write PDPs

The docs (and simulator seems to back up) suggest that we can only
program legacy PPGTT PDPs with LRI commands.

v6: Rebase around context differences conflicts.

v7: Use #defines for per ring PDPs. (Damien)

v8: Don't use typede'f private_t.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (up to v3 and v7)
Reviewed-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:47 +01:00
Ben Widawsky 9df15b499b drm/i915/bdw: Implement PPGTT insert
GEN8 insertion is very similar to GEN6.

v2: Rebase on top of Imre's for_each_sg_page helpers.

v3: Fixup my conversion (spotted by Ville).

v4: Rebase on top of the address space refactoring.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:47 +01:00
Ben Widawsky 459108b8cc drm/i915/bdw: Implement PPGTT clear range
GEN8 PPGTT range clearing is very similar to GEN6 if we assume that our
PDEs are all valid, which they should be.

v2: Rebase on top of the address space refactoring.

v3: Rebase on top of the bool use_scratch addition to the clear_range interface.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:46 +01:00
Ben Widawsky b1fe667329 drm/i915/bdw: Initialize the PDEs
The upcoming clear and insert routines will expect that PDEs all point
to valid Page Directories. Doing that lazily doesn't really buy us
anything.

The page allocation is done regardless earlier in init so it shouldn't
hurt set the PDEs.

v2: Squash in patches to implement fixed PDE write function:

- If I had done this in the first place, the bug that's going to be
  fixed in an upcoming patch would have been much easier to find.

- Use WB for PDEs.

  The PAT bit is used for page size. 2ME PDEs aren't even supported in
  BDW, so this was completely invalid. The solution is to make our
  PDEs WB+LLC instead of the pervious WB+eLLC. As far as I can guess,
  this change won't matter for performance.

  Thanks to Ville for the quick correction when discussing on IRC.

v3: Return the pde type for pde encoding (Damien)

Reviewed-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:46 +01:00
Ben Widawsky 37aca44ad5 drm/i915/bdw: PPGTT init & cleanup
Aside from the potential size increase of the PPGTT, the primary
difference from previous hardware is the Page Directories are no longer
carved out of the Global GTT.

Note that the PDE allocation is done as a 8MB contiguous allocation,
this needs to be eventually fixed (since driver reloading will be a
pain otherwise). Also, this will be a no-go for real PPGTT support.

v2: Move vtable initialization

v3: Resolve conflicts due to patch series reordering.

v4: Rebase on top of the address space refactoring of the PPGTT
support. Drop Imre's r-b tag for v2, too outdated by now.

v5: Free the correct amount of memory, "get_order takes size not a page
count." (Imre)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:45 +01:00
Ben Widawsky fbe5d36e77 drm/i915/bdw: Support BDW caching
BDW caching works differently than the previous generations. Instead of
having bits in the PTE which directly control how the page is cached,
the 3 PTE bits PWT PCD and PAT provide an index into a PAT defined by
register 0x40e0. This style of caching is functionally equivalent to how
it works on HSW and before.

v2: Tiny bikeshed as discussed on internal irc.

v3: Squash in patch from Ville to mirror the x86 PAT setup more like
in arch/x86/mm/pat.c. Primarily, the 0th index will be WB, and not
uncached.

v4: Comment for reason to not use a 64b write on the PPAT.

v5: Add a FIXME comment that the caching bits in the PAT registers
might be wrong due to doc confusion.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:45 +01:00
Ben Widawsky 94ec8f6130 drm/i915/bdw: Add GTT functions
With the PTE clarifications, the bind and clear functions can now be
added for gen8.

v2: Use for_each_sg_pages in gen8_ggtt_insert_entries.

v3: Drop dev argument to pte encode functions, upstream lost it. Also
rebase on top of the scratch page movement.

v4: Rebase on top of the new address space vfuncs.

v5: Add the bool use_scratch argument to clear_range and the bool valid argument
to the PTE encode function to follow upstream changes.

v6: Add a FIXME(BDW) about the size mismatch of the readback check
that Jon Bloomfield spotted.

v7: Squash in fixup patch from Ben for the posting read to match the
64bit ptes and so shut up the WARN.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:44 +01:00
Ben Widawsky d31eb10e6c drm/i915/bdw: Create gen8_gtt_pte_t
With gen6 PTE type in place, pave the way for the new gen8 type.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:44 +01:00
Ben Widawsky 63340133f3 drm/i915/bdw: Make gen8_gmch_probe
Probing gen8 is similar to gen6. To make the code cleaner and more
maintainable however we can use the probe functions to split it out.

v2: Rebased on top of update gtt probe infrastructure.

v3: Rebased on top of Kenneth' Graunke's ->pte_encode refactoring.

V4: Resolve conflicts with Ben's latest ppgtt patches, also switch to
gen < 8 testing instead of gen <= 7.

v5: Resolve conflicts with address space vfunc changes in upstream.

v6: Use 39b DMA mask. At least, for this mode, it is the correct mask.
(Imre)

Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:43 +01:00
Ben Widawsky d0582ed2ff drm/i915/bdw: Update relevant error state
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:43 +01:00
Ben Widawsky 9d3203e16c drm/i915/bdw: debugfs updates
All the gen8 debugfs stuff I wasn't too lazy to update. We'll need more
later, I am certain.

v2: Fix up the register name in the debugfs output as suggested by
Paulo.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
Reviewed-by: Paulo Zanoni <przanoni@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:42 +01:00
Ben Widawsky 075b3bbaae drm/i915/bdw: Update MI_FLUSH_DW
The code is more verbose than necessary for the reader's sake, hopefully
the compiler optimizes away the if.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:42 +01:00
Ben Widawsky 1c7a0623c7 drm/i915/bdw: dispatch updates (64b related)
The command to emit batch buffers has changed to address 48b addresses.
It seemed reasonable that we could still use the old instruction where
emitting 0 for length would do the right thing, but it seems to bother
the simulator when the code does that.

Now the second dword in the command has the upper 16b of the address of
the batchbuffer.

v2: Remove duplicated vfun assignment.

v3: Squash in VECS support changes from Zhao Yakui <yakui.zhao@intel.com>

v4: Make checkpatch happy.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v2)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:41 +01:00
Ben Widawsky 3c94ceeee2 drm/i915/bdw: Support 64b relocations
We don't actually return any to userspace yet, however we can pretend
like we do now so userspace will support it when it happens.

This is just to please Chris as the code itself isn't ready for > 64b
relocations.

v2: Rebase on top of the refactored relocate_entry_gtt|cpu functions.

v3: Squash in fixup from Rafal Barbalho for 64 byte relocs using cpu
relocs and those crossing a page boundary.

v4: Squash in a fixup for the fixup from Rafael.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
Signed-off-by: Barbalho, Rafael <rafael.barbalho@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:41 +01:00
Ben Widawsky a123f157a3 drm/i915/bdw: Add interrupt info to debugfs
v2: Add missed ring interrupt info

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:40 +01:00
Ben Widawsky abd58f0175 drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.

The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.

For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).

The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).

Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.

v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.

v3: fix DE_MISC IER offset

v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.

v5: Rebased on to of recent pch hotplug setup changes.

v6: Fixup on top of moving num_pipes to intel_info.

v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.

v8: Rebase on top of Jani's asle handling rework.

v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/

v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>

v11: Rebase on top of the interrupt cleanups in upstream.

v12: Rebase on top of Ben's DPF changes in upstream.

v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.

v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
  the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
  we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

bikeshed
2013-11-08 18:09:39 +01:00
Ben Widawsky 9459d25237 drm/i915/bdw: support GMS and GGMS changes
All the BARs have the ability to grow.

v2: Pulled out the simulator workaround to a separate patch.
Rebased.

v3: Rebase onto latest vlv patches from Jesse.

v4: Rebased on top of the early stolen quirk patch from Jesse.

v5: Use the new macro names.
s/INTEL_BDW_PCI_IDS_D/INTEL_BDW_D_IDS
s/INTEL_BDW_PCI_IDS_M/INTEL_BDW_M_IDS
It's Jesse's fault for not following the convention I originally set.

Cc: Ingo Molnar <mingo@kernel.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:39 +01:00
Ben Widawsky 4e0bbc316e drm/i915/bdw: display stuff
Just enough to make the code not barf...

Init BDW display to look like HSW. For the simulator this should be
fine, but this will probably require more work.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
[danvet: Add a FIXME comment about RCS flips being untested on bdw.
Also add a note that hblank events are reserved on bdw+ in DERRMR.]
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:38 +01:00
Ben Widawsky 1020a5c2dc drm/i915/bdw: Clock gating init
Clock gating init is really a catch all function for registers we need
to write early in loading the driver.

Atm just the bare metal stuff we need, more will surely come.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:38 +01:00
Ben Widawsky 8897644a6d drm/i915/bdw: HW context support
BDW context sizes varies a bit.

v2: Squash in fixup for the hw context size from Ben.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:37 +01:00
Ben Widawsky 31a5336e1c drm/i915/bdw: Swizzling support
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:37 +01:00
Ben Widawsky 5ab31333ac drm/i915/bdw: Fences on gen8 look just like gen7
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:36 +01:00
Ben Widawsky 4d4dead67a drm/i915/bdw: Add device IDs
v2: Squash in "drm/i915/bdw: Add BDW to the HAS_DDI check" as
suggested by Damien.

v3: Squash in VEBOX enabling from  Zhao Yakui <yakui.zhao@intel.com>

v4: Rebase on top of Jesse's patch to extract all pci ids to
include/drm/i915_pciids.h.

v4: Replace Halo by its marketing moniker Iris. Requested by Ben.

v5: Switch from info->has*ring to info->ring_mask.

v6: Add 0x16X2 variant (which is newer than this patch)
Rename to use new naming scheme (Chris)
Remove Simulator PCI ids. These snuck in during rebase (Chris)

v7: Fix poor sed job from v6
Make the desktop variants use the desktop macro (Rebase error). Notice
that this makes no functional difference - it's just confusing.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:36 +01:00
Daniel Vetter 8fe6bd239a drm/i915/bdw: Disable PPGTT for now
This will be changed once the gen8 code is fully implemented.

v2: Use ENOSYS instead of ENXIO as suggested by Chris.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:09:35 +01:00
Ben Widawsky 43d1b64728 drm/i915/bdw: Initialize BDW forcewake vfuncs
Somehow this got missed or dropped during development. The simulator
does not use forcewake, so it's entirely possible it never worked
correctly. After the mmio rework, this will end up in an OOPs, and the
system will not boot.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
[danvet: Use IS_GEN8 instead of IS_BROADWELL.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 18:08:46 +01:00
Chon Ming Lee ab3c759a04 drm/i915/vlv: Rename VLV DPIO register to be more structure to match configdb document.
Some VLV PHY/PLL DPIO registers have group/lane/channel access.  Current
DPIO register definition doesn't have a structure way to break them
down. As a result it is not easy to match the PHY/PLL registers with the
configdb document.  Rename those registers based on the configdb for easy
cross references, and without the need to check the offset in the header
file.

New format is as following.

<platform name>_<DPIO component><optional lane #>_DW<dword # in the
doc>_<optional channel #>

For example,

VLV_PCS_DW0 - Group access to PCS for lane 0 to 3 for PCS DWORD 0.
VLV_PCS01_DW0_CH0 - PCS access to lane 0/1, channel 0 for PCS DWORD 0.

Another example is

VLV_TX_DW0 - Group access to TX lane 0 to 3 for TX DWORD 0
VLV_TX0_DW0 - Refer to TX Lane 0 access only for TX DWORD 0.

There is no functional change on this patch.

v2: Rebase based on previous patch change.
v3: There may be configdb different version that document the start DW
differently. Add a comment to clarify.  Fix up some mismatch start DW
for second PLL block. (Ville)

Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08 17:37:45 +01:00
Patrik Jakobsson cd3fdbe853 drm/gma500/mrst: Add SDVO to output init
Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
2013-11-08 16:23:19 +01:00
Patrik Jakobsson 49a5d87a89 drm/gma500/mrst: Don't blindly guess a mode for LVDS
Previously we always had something hooked up to LVDS so we tried very
hard to get a mode. With the Minnowboard this is no longer the case.
If no mode can be found over DDC or the firmware we just ignore LVDS.

Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
2013-11-08 16:23:10 +01:00
Patrik Jakobsson 6528c89796 drm/gma500/mrst: Setup GMBUS for oaktrail/mrst
Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
2013-11-08 16:22:13 +01:00
Patrik Jakobsson 99d754bb46 drm/gma500/mrst: Replace WMs and chickenbits with values from EMGD
For the minnowboard to work the values found in EMGD are required.
This might break Oaktrail but without hardware to test with I cannot
really tell (and do not really care).

Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
2013-11-08 16:22:12 +01:00
Patrik Jakobsson fb8e34d561 drm/gma500/mrst: Add aux register writes to SDVO
This turned out to be tricky. Writing to SDVOB on the primary vdc also
writes to SDVOB on the aux vdc, but reading it back on the primary vdc
always fails. Basically we never read from the primary vdc since we
will end up trashing the aux vdc.

Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
2013-11-08 16:22:12 +01:00
Patrik Jakobsson 5aac788323 drm/gma500/mrst: Properly route oaktrail hdmi hooks
Since we can have SDVO on Pipe B we better check the output type instead
of pipe number for Oaktrail HDMI.

Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
2013-11-08 16:22:11 +01:00
Patrik Jakobsson b97b8287a3 drm/gma500/mrst: Add aux register writes when programming pipe
On SDVO pipes (always Pipe B on mrst) we have to sequentially write the
aux vdc. We might be able to skip programming the primary vdc in
some/most places but we don't care about that now.

Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
2013-11-08 16:22:10 +01:00
Patrik Jakobsson ac6113ebb7 drm/gma500/mrst: Add SDVO clock calculation
We start off by adding SDVO limits and converting all limits to the
generic gma_limit_t stuct. Then we separate clock calculations for
LVDS and SDVO. This will be cleaned up later but keep it simple for now.

Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
2013-11-08 16:22:09 +01:00
Patrik Jakobsson 86bd410325 drm/gma500: Add aux device support for gmbus
Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
2013-11-08 16:22:08 +01:00
Patrik Jakobsson 2657929d4e drm/gma500: Add support for aux pci vdc device
Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
2013-11-08 16:22:07 +01:00
Patrik Jakobsson cf8efd3afe drm/gma500: Add chip specific sdvo masks
Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
2013-11-08 16:22:06 +01:00
Patrik Jakobsson 9d3e2f5304 drm/gma500: Add Minnowboard to the IS_MRST() macro
Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
2013-11-08 16:22:05 +01:00
Dave Airlie 91915260ea Merge tag 'drm-intel-fixes-2013-11-07' of git://people.freedesktop.org/~danvet/drm-intel into drm-next
Bit a bit -fixes pull request in the merge window than usual dua to two
feauture-y things:
- Display CRCs are now enabled on all platforms, including the odd DP case
  on gm45/vlv. Since this is a testing-only feature it should ever hurt,
  but I figured it'll help with regression-testing -fixes. So I left it
  in and didn't postpone it to 3.14.
- Display power well refactoring from Imre. Would have caused major pain
  conflict with the bdw stage 1 patches if I'd postpone this to -next.
  It's only an relatively small interface rework, so shouldn't cause pain.
  It's also been in my tree since almost 3 weeks already.

That accounts for about two thirds of the pull, otherwise just bugfixes:
- vlv backlight fix from Jesse/Jani
- vlv vblank timestamp fix from Jesse
- improved edp detection through vbt from Ville (fixes a vlv issue)
- eDP vdd fix from Paulo
- fixes for dvo lvds on i830M
- a few smaller things all over

Note: This contains a backmerge of v3.12. Since the -internal branch
always applied on top of -nightly I need that unified base to merge bdw
patches. So you'll get a conflict with radeon connector props when pulling
this (and nouveau/master will also conflict a bit when Ben doesn't
rebase). The backmerge itself only had conflicts in drm/i915.

There's also a tiny conflict between Jani's backlight fix and your sysfs
lifetime fix in drm-next.

* tag 'drm-intel-fixes-2013-11-07' of git://people.freedesktop.org/~danvet/drm-intel: (940 commits)
  drm/i915/vlv: use per-pipe backlight controls v2
  drm/i915: make backlight functions take a connector
  drm/i915: move opregion asle request handling to a work queue
  drm/i915/vlv: use PIPE_START_VBLANK interrupts on VLV
  drm/i915: Make intel_dp_is_edp() less specific
  drm/i915: Give names to the VBT child device type bits
  drm/i915/vlv: enable HDA display audio for Valleyview2
  drm/i915/dvo: call ->mode_set callback only when the port is running
  drm/i915: avoid unclaimed registers when capturing the error state
  drm/i915: Enable DP port CRC for the "auto" source on g4x/vlv
  drm/i915: scramble reset support for DP port CRC on vlv
  drm/i915: scramble reset support for DP port CRC on g4x
  drm/i916: add "auto" pipe CRC source
  ...

Conflicts:
	MAINTAINERS
	drivers/gpu/drm/i915/intel_panel.c
	drivers/gpu/drm/nouveau/core/subdev/mc/base.c
	drivers/gpu/drm/radeon/atombios_encoders.c
	drivers/gpu/drm/radeon/radeon_connectors.c
2013-11-08 16:34:39 +10:00
Dave Airlie 21136946c4 drm/vmwgfx: fix warning if config intel iommu is off.
Though I'm not really happy with how ugly this code is now.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-08 16:12:42 +10:00
Emil Velikov 4c60fac111 drm/nouveau: consider CLASS_DISPLAY_3D devices while detecting dsm/optimus
The present code assumes that optimus is present whenever two
VGA (PCI_CLASS_DISPLAY_VGA) devices are present. This does not
seem to be the case of newer laptops with optimus, in which
case the nvidia gpu is a PCI_CLASS_DISPLAY_3D device.

Rework the logic so that we count both VGA and 3D devices,
when contemplating if optimus is present on the platform.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70208
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-08 16:02:47 +10:00
Dave Airlie 4a15cdffa9 Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next
- Ilia's PMPEG improvements
- MSI fixes, and another attempt at enabling by default
- Initial GK208 support, just modesetting
- "Old" PM code gone, new infrastructure and various different stages of support (depending which chipset / ram type etc) is in its place.  This includes support that goes beyond what the previous code was capable of.  User control has been deliberately sabotaged, it's not safe to use still.
- Thermal management / fan control that's been present for a while is turned ON by default now.
- Misc other fixes that have accumulated

* 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (74 commits)
  drm/nouveau/fb: implement various bits of work towards memory reclocking
  drm/nouveau: implement a simple sysfs interface to new pm code
  drm/nouveau/device: initial control object class, with pstate control methods
  drm/nouveau/clk: implement power state and engine clock control in core
  drm/nouveau/volt: implement voltage control in core
  drm/nouveau/bios: parsing for various tables required for power management
  drm/nouveau/perfmon: initial infrastructure to expose performance counters
  drm/nouveau/bus: add interfaces/helpers for sequencer
  drm/nouveau/bus: make external class definitions pointers
  drm/nouveau/pwr: initial implementation
  drm/nouveau/therm: update target fanspeed outside of therm lock
  drm/nouveau/therm: automatic mode by default
  drm/nouveau/therm: no toggle fan control either if we can't guarantee no pwm connected
  drm/nvc0/therm: allow fan control if we've killed the vbios ppwr ucode
  drm/nouveau/therm: if no bios trip/linear info, default to perf-suggested speed
  drm/nouveau/therm: add hook for clk to suggest fanspeed to therm
  drm/nouveau/pwr: assign a subdev id for upcoming implementation
  drm/nouveau/gpio: return different error code for not found vs invalid
  drm/nouveau/drm/pm: remove everything except the hwmon interfaces to THERM
  drm/nouveau/core: make all info-level messages silent for runtime pm
  ...
2013-11-08 16:01:02 +10:00
Dave Airlie ec61f5eb58 drm/mgag200: drop pointless info print.
This isn't useful anymore.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-08 15:49:43 +10:00
Ben Skeggs aae95ca708 drm/nouveau/fb: implement various bits of work towards memory reclocking
Not even remotely ready for the vast majority of the world.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:40:19 +10:00
Ben Skeggs 26fdd78cce drm/nouveau: implement a simple sysfs interface to new pm code
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:40:18 +10:00
Ben Skeggs 9838366c15 drm/nouveau/device: initial control object class, with pstate control methods
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:40:18 +10:00
Ben Skeggs 7c85652206 drm/nouveau/clk: implement power state and engine clock control in core
User control of this has been hard-coded as disabled for now.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:40:17 +10:00
Ben Skeggs c9c0ccae48 drm/nouveau/volt: implement voltage control in core
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:40:17 +10:00
Ben Skeggs 0833428e7d drm/nouveau/bios: parsing for various tables required for power management
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:40:16 +10:00
Ben Skeggs aa4d7a4d55 drm/nouveau/perfmon: initial infrastructure to expose performance counters
Internal use only at this point.  Userspace later.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:40:05 +10:00
Ben Skeggs 2984506fb6 drm/nouveau/bus: add interfaces/helpers for sequencer
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:40:05 +10:00
Ben Skeggs 48ae0b355f drm/nouveau/bus: make external class definitions pointers
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:40:04 +10:00
Ben Skeggs ff4b42c753 drm/nouveau/pwr: initial implementation
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:40:04 +10:00
Ben Skeggs 682b1fc793 drm/nouveau/therm: update target fanspeed outside of therm lock
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:40:03 +10:00
Ben Skeggs 208cf0b789 drm/nouveau/therm: automatic mode by default
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:40:03 +10:00
Ben Skeggs 21b1ed10df drm/nouveau/therm: no toggle fan control either if we can't guarantee no pwm connected
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:40:02 +10:00
Ben Skeggs 09b8d73bd5 drm/nvc0/therm: allow fan control if we've killed the vbios ppwr ucode
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:40:02 +10:00
Ben Skeggs 36faa2fc22 drm/nouveau/therm: if no bios trip/linear info, default to perf-suggested speed
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:40:01 +10:00
Ben Skeggs 6387e2cbdc drm/nouveau/therm: add hook for clk to suggest fanspeed to therm
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:40:01 +10:00
Ben Skeggs 547807b8ce drm/nouveau/pwr: assign a subdev id for upcoming implementation
THERM will use this before it exists.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:40:01 +10:00
Ben Skeggs 2d976e3d64 drm/nouveau/gpio: return different error code for not found vs invalid
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:40:00 +10:00
Ben Skeggs b9ed919f1c drm/nouveau/drm/pm: remove everything except the hwmon interfaces to THERM
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:40:00 +10:00
Ben Skeggs c52f4fa61d drm/nouveau/core: make all info-level messages silent for runtime pm
Removes the need for special handling of messages in init paths.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:39:59 +10:00
Ben Skeggs 16c4f227ff drm/nouveau/fifo: make external class definitions into pointers
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:39:59 +10:00
Ben Skeggs aabf19c27f drm/nouveau/device: recognise GK208
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:39:58 +10:00
Ben Skeggs 13d2b35a06 drm/nvc0-/gr: fix a number of missing explicit array terminators...
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:39:58 +10:00
Ben Skeggs 0c0888473d drm/nouveau/mc: fix (incorrect) reporting of unknown pending intr bits
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:39:57 +10:00
Ben Skeggs 8df1d0c07f drm/nouveau/disp: semi-complete link training sequence even if display disappears
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:39:57 +10:00
Ben Skeggs 4767fae8f8 drm/nouveau/bios: some older boards have shorter displayport tables
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:39:56 +10:00
Ben Skeggs 46ea16884c drm/nouveau/fbcon: bracket entrypoints with a per-device enabled check
We don't necessarily have fbcon on all devices these days.

Fixes suspend on (at least) Quadro NVS 450.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:39:56 +10:00
Ben Skeggs 6d8d163132 drm/nvd0-/disp: reorder writes to lane current control regs
Matches the nv94-nvc0 commit with the same title.  Doesn't fix a reported issue,
but NVIDIA use this ordering here too, so let's do it just in case.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:39:55 +10:00
Ben Skeggs d7b023d87a drm/nv94-nvc0/disp: reorder writes to lane current control regs
Fixes link training issues on some boards.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:39:55 +10:00
Ben Skeggs 687d8f66b1 drm/nouveau/disp: log if DP link training fails
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:39:55 +10:00
Martin Peres 9e2b734f1c drm/nouveau/i2c: use a custom bitbanging delay for the adt7473
This patch adds a way to define a custom delay when scanning for i2c devices
because the adt7473 sometimes doesn't like the default bitbanging udelay.

Signed-off-by: Martin Peres <martin.peres@labri.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:39:54 +10:00
Ilia Mirkin fd34381b0e drm/nouveau/agp: add a quirk list to limit agp modes
Certain combinations of hardware can't actually support the maximum
detected speed. Add a quirk list that lists pairs of hostbridge/chip pci
ids and the mode that they should work with.

See https://bugs.freedesktop.org/show_bug.cgi?id=20341

Reported-by: Jason Detring <detringj@gmail.com>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:39:54 +10:00
Ben Skeggs e8d95b22b4 drm/nvd9-/disp: disable display underflow reporting at init
Reported-by: Andy Ritger <aritger@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:39:53 +10:00
Ben Skeggs d29b992470 drm/nva0/clk: fix accidental limiting of pll coefficients
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:39:53 +10:00
Ben Skeggs 75faef78c9 drm/nv50-nvaf/fb: split fbram oclass in preparation for reclocking
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:39:52 +10:00
Ben Skeggs 20cdeaf938 drm/nouveau/fb: merge more bits and pieces into oclass definitions
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:39:52 +10:00
Ben Skeggs 8613e7314a drm/nouveau/fb: remove ram oclass argument from base fb constructor
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:39:51 +10:00
Ben Skeggs 9ca3037e60 drm/nv50-nvaf/fb: split the class definitions up a bit
These will diverge further in the future.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:39:51 +10:00
Ben Skeggs 1e9fc30e38 drm/nouveau/fb: make external class definitions pointers
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:39:50 +10:00
Ben Skeggs 0fef9d8a59 drm/nvaa/mc: blacklist msi to off by default
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:39:50 +10:00
Ben Skeggs 9a9d5c64ef drm/nv50-nv86,nv92/mc: rearm msi via pci config space, rather than mmio mirror
This is what NVIDIA do on these chipsets, let's hope it works around
the reported MSI failures for us on NV86.

v2: updated to include G92, as per information provided by NVIDIA.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:39:38 +10:00
Ben Skeggs 1b4fea0f6a drm/nvc0,nvc4/mc: handle 0xc0's "special" msi rearm
v2. updated to cover GF104, as per information provided by NVIDIA.

Reported-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:39:38 +10:00
Ben Skeggs 08f6fbdb9b drm/nouveau/mc: store static data in nouveau_mc class definition
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:39:35 +10:00
Ben Skeggs 3c792a15ec drm/nouveau/mc: fetch NV_PMC_INTR again after re-arming MSI
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:39:05 +10:00
Ben Skeggs ab5beca895 drm/nouveau/mc: bracket interrupt handler with NV_PMC_INTR_EN disable/re-enable
This looks to be what NVIDIA do pretty much everywhere, since forever.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:39:05 +10:00
Ben Skeggs 6dcee40a9b drm/nouveau/mc: have single entry and exit points to the interrupt handler
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:39:00 +10:00
Ben Skeggs cfc2f2637a drm/nouveau/mc: msi rearm write via subdev, not device
This way we can catch it with debugging on for PMC subdev.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:38:26 +10:00
Ben Skeggs dd5b84ac3c drm/nouveau/device: use an additional bit from NV_PMC_BOOT_0 to identify chipset
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:37:44 +10:00
Ben Skeggs 3db0fdb467 drm/nouveau/bios/init: return failure condition on invalid opcodes
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:37:43 +10:00
Ben Skeggs ab403ac96f drm/nv31/mpeg: remove need for separate refcnt on engine use
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:37:43 +10:00
Martin Peres b449a43f56 drm/nouveau/therm: ack any pending IRQ at init
This is safe because ptherm hasn't been configured yet and will be a
little further down the initialization path. Ptherm should be safe
regarding to runtime reconfiguration.

v2:
  - do not limit this patch to nv84-a3 and make it nv84+

v3:
  - move the ack to fini()
  - disable IRQs on fini()
  - silently ignore un-requested IRQs

Signed-off-by: Martin Peres <martin.peres@labri.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:37:43 +10:00
Ilia Mirkin be0dd4ddef drm/nv31/mpeg: split the nv31 and nv40 dma setting implementations
NV31 has different config bits than NV40+ do. Also fix the DMA_IMAGE
VRAM-only setting to check the right bits.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:37:42 +10:00
Ilia Mirkin e6585cab68 drm/nv31/mpeg: store chan singleton in engine, use it for dispatch
This makes nv31+ able to actually perform the nv_call, since previously
the inst was not available.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:37:42 +10:00
Ilia Mirkin 912de74c81 drm/nv40/mpeg: use the nv31-provided classes
Since nv40 only covers pre-nv44 now, it can use the nv31-provided
functions.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:37:41 +10:00
Ilia Mirkin 5fa7543041 drm/nv44/mpeg: create a copy of the nv31/nv40 impls
The nv31/nv40 impls are actually fairly nv44-specific, since they assume
the presence of the instance register/context switching. Create a copy
before nv31/nv40 get fixed.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:37:41 +10:00
Ilia Mirkin be4ba55046 drm/nv31/mpeg: no need to set compat mode differently for nv44 gr
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:37:40 +10:00
Ilia Mirkin 515de6b27f drm/nv10/kms: add plane support for nv10-nv40
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:37:40 +10:00
Ilia Mirkin 8aa816b0bb drm/nv10: fix chipset checks, mostly for the benefit of nv1a
NV1A is numerically higher than NV17 but generationally lower. Use the
new card type to help disambiguate.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:37:39 +10:00
Ilia Mirkin 4a0ff75418 drm/nv10: introduce a new NV_11 card type
NV11/17/1F/18 come after NV10/15/16/1A. In order to facilitate using
numerical comparisons, split up the two sets into different card types.

This change should be a no-op except that the relevant cards will see
NV11 printed instead of NV10 for the family.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:37:35 +10:00
Ilia Mirkin 73f4b1f893 drm/nouveau: fix backlight mask on ppc powerbook
This code was originally moved to using nv_mask by d31e078d84. This
should not have any actual effect since the mask isn't applied to the
value.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:36:08 +10:00
Ilia Mirkin 4449933a37 drm/nouveau: remove prototype for non-existent nouveau_connector_bpp
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:36:08 +10:00
Ben Skeggs c42a7aec12 drm/nouveau/vic: rename PUNK1C1 to PVIC
NVIDIA's name for what rnndb calls PVCOMP.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:36:07 +10:00
Ben Skeggs 74ce291a49 drm/nouveau/therm: kill some over-zealous debugging
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:36:07 +10:00
Ben Skeggs 15689c3c81 drm/nouveau/core: split lock into list+exec and enable refcount locks
This fixes a reported locking inversion when interacting with the DRM
core's vblank routines.

Reviewed-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:36:06 +10:00
Ben Skeggs 51cb4b392a drm/nouveau/core: convert event handler apis to split create/enable semantics
This is a necessary step towards being able to work with the insane locking
requirements of the DRM core's vblank routines, and a nice cleanup as a
side-effect.

This is similar in spirit to the interfaces that Peter Hurley arrived at
with his nouveau_event rcu conversion series.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:36:06 +10:00
Ben Skeggs 7589563eb3 drm/nv50-/sw: share engine/channel constructor between implementations
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:36:05 +10:00
Ben Skeggs c46c3ddf1f drm/nouveau/sw: prepare for the sharing of constructors between implementations
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:36:05 +10:00
Ben Skeggs ef8d478147 drm/nv50-/sw: make vblank tracking data private to the implementations
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:36:04 +10:00
Ben Skeggs 3bfcec35da drm/nv50-/sw: share engine/channel struct definitions between implementations
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:36:04 +10:00
Peter Hurley ac51bb0983 drm/nouveau/core: Allow asymmetric nouveau_event_get/_put
Most nouveau event handlers have storage in 'static' containers
(structures with lifetimes nearly equivalent to the drm_device),
but are dangerously reused via nouveau_event_get/_put. For
example, if nouveau_event_get is called more than once for a
given handler, the event handler list will be corrupted.

Signed-off-by: Peter Hurley <peter@hurleysoftware.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:36:03 +10:00
Peter Hurley 019255797d drm/nouveau/core: Move event index check from critical section
The index_nr field is constant for the lifetime of the event, so
serialized access is unnecessary.

Signed-off-by: Peter Hurley <peter@hurleysoftware.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:36:03 +10:00
Peter Hurley a25f83ba89 drm/nouveau/core: Add priv field for event handlers
Provide private field for event handlers exclusive use.
Convert nouveau_fence_wait_uevent() and
nouveau_fence_wait_uevent_handler(); drop struct nouveau_fence_uevent.

Signed-off-by: Peter Hurley <peter@hurleysoftware.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:36:02 +10:00
Dan Carpenter ca3562226a drm/nouveau: off by one in nouveau_drm_vblank_enable()
The test here should be ">= ARRAY_SIZE()" instead of "> ARRAY_SIZE()".

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:36:02 +10:00
Dave Jones 1934a2add9 drm/nouveau: remove pointless assignment
self-assignment of a variable doesn't make a lot of sense.

Signed-off-by: Dave Jones <davej@fedoraproject.org>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08 15:36:02 +10:00
Ben Widawsky ab2aa47e4b drm/i915/bdw: Handle forcewake for writes on gen8
GEN8 removes the GT FIFO which we've all come to know and love. Instead
it offers a wider range of optimized registers which always keep a
shadowed copy, and are fed to the GPU when it wakes.

How this is implemented in hardware is still somewhat of a mystery. As
far as I can tell, the basic design is as follows:

If the register is not optimized, you must use the old forcewake
mechanism to bring the GT out of sleep. [1]

If register is in the optimized list the write will signal that the
GT should begin to come out of whatever sleep state it is in.

While the GT is coming out of sleep, the requested write will be stored
in an intermediate shadow register.

Do to the fact that the implementation details are not clear, I see
several risks:
1. Order is not preserved as it is with GT FIFO. If we issue multiple
writes to optimized registers, where order matters, we may need to
serialize it with forcewake.
2. The optimized registers have only 1 shadowed slot, meaning if we
issue multiple writes to the same register, and those values need to
reach the GPU in order, forcewake will be required.

[1] We could implement a SW queue the way the GT FIFO used to work if
desired.

NOTE: Compile tested only until we get real silicon.

v2:
- Use a default case to make future platforms also work.
- Get rid of IS_BROADWELL since that's not yet defined, but we want to
  MMIO as soon as possible.

v3: Apply suggestions from Mika's review:
- s/optimized/shadowed/
- invert the logic of the helper so that it does what it says (the
  code itself was correct, just confusing to read).

v4:
- Squash in lost break.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-07 22:16:04 +01:00
Ville Syrjälä 1272e7b854 drm/i915: Use clamp_t() when limiting cur_delay
Make the cur_delay limiting code a bit less prone to typo errors
by using clamp_t().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-07 20:04:53 +01:00
Ville Syrjälä 4c7915616a drm/i915: Kill vlv_update_rps_cur_delay()
Polling to make sure the current GPU frequency matches the last
requested frequency should not be necessay, and if there's some
throttling involved, the two might not match anyway.

Since we're still seeing this trigger occasionally, and it just
introduces a rather pointless 10 ms delay, it seems like better
to kill it off.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-07 20:04:38 +01:00
Chris Wilson 6917c7b9d9 drm/i915: Initialise min/max frequencies before updating RPS registers
The RPS register writing routines use the current value of min/max to
set certain limits and interrupt gating. If we set those afterwards, we
risk setting up the hw incorrectly and losing power management events,
and worse, trigger some internal assertions.

Reorder the calling sequences to be correct, and remove the then
unrequired clamping from inside set_rps(). And for a bonus, fix the bug
of calling gen6_set_rps() from Valleyview.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
CC: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-07 19:13:07 +01:00
Chon Ming Lee c5bd2bf61d drm/i915/vlv: For i915_cur_delayinfo, the max frequency reporting wrong value.
The max frequency reporting is not correct.  But there is already an existing
valleyview_rps_max_freq and valleyview_rps_min_freq to get the
frequency.  Use that for i915_cur_delayinfo.

Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-07 17:55:34 +01:00
Ville Syrjälä 57e22f4add drm/i915: Use frame counter for intel_wait_for_vblank() on CTG
Use the same wait_for_vblank code for CTG that we use for ILK+.

Also fix the name of the frame counter register while at it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-07 17:44:11 +01:00
Ville Syrjälä edc08d0a40 drm/i915: Fix gen3/4 vblank counter wraparound
When the hardware frame counter reads 0xffffff and we're already past
vblank start, we'd return 0x1000000 as the vblank counter value. Once
we'd cross into the next frame's active portion, the vblank counter
would wrap to 0. So we're reporting two different vblank counter values
for the same frame.

Fix the problem by masking the cooked value by 0xffffff to make sure
the counter wraps already after vblank start.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-07 17:20:17 +01:00
Chon Ming Lee 2325991e02 drm/i915/vlv: Workaround a punit issue in DDR data rate for 1333.
For DDR data rate reporting by Punit in PUNIT_GPU_FREQ_STS, the actual
data encoding is 00b=800, 01b=1066, 10b=1333, 11b=1333.

Some premium VLV sku will get the DDR_DATA_RATE set as 11.  As a result,
the turbo frequency reporting will be incorrect without this workaround.

Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-07 15:19:23 +01:00
Ben Widawsky 8245be3139 drm/i915: Require HW contexts (when possible)
v2: Fixed the botched locking on init_hw failure in i915_reset (Ville)
Call cleanup_ringbuffer on failed context create in init_hw (Ville)

v3: Add dev argument ti clean_ringbuffer

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-07 09:35:44 +01:00
Dave Airlie 212c444baa Merge branch 'ttm-next-3.13' of git://people.freedesktop.org/~thomash/linux into drm-next
- A couple of fixes that never made it into fixes-3.12
- Make NO_EVICT bo's available for shrinkers when on delayed-delete list
- Allow retrying page-faults that need to wait for GPU.

* 'ttm-next-3.13' of git://people.freedesktop.org/~thomash/linux:
  drm/ttm: Fix memory type compatibility check
  drm/ttm: Fix ttm_bo_move_memcpy
  drm/ttm: Handle in-memory region copies
  drm/ttm: Make NO_EVICT bos available to shrinkers pending destruction
  drm/ttm: Allow vm fault retries
2013-11-07 12:22:10 +10:00
Jesse Barnes 07bf139b90 drm/i915/vlv: use per-pipe backlight controls v2
With the connector and pipe passed around, we can now set the backlight
on the right pipe on VLV/BYT.

v2: drop combination mode check for VLV (Jani)
    add save/restore code for VLV backlight regs (Jani)
    check for existing modulation freq when initializing backlight regs (Jani)

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67245
Tested-by: Joe Konno <joe.konno@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-06 18:26:31 +01:00
Ville Syrjälä 2ec3815f29 drm/i915: Pass dev_priv to vlv_gpu_freq() and vlv_freq_opcode()
We'll be looking at more than just mem_freq from dev_priv, so
just pass the whole thing.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-06 18:05:40 +01:00
Ville Syrjälä 07ab118b39 drm/i915: Improve vlv_gpu_freq() and vlv_freq_opcode()
We're currently miscalculating the VLV graphics clock a little bit.
This is caused by rounding the step to integer MHz, which does not
match reality. Change the formula to match the GUnit HAS to give
more accurate answers.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-06 18:05:20 +01:00
Jesse Barnes 752aa88a1e drm/i915: make backlight functions take a connector
On VLV/BYT, backlight controls a per-pipe, so when adjusting the
backlight we need to pass the correct info.  So make the externally
visible backlight functions take a connector argument, which can be used
internally to figure out the pipe backlight to adjust.

v2: make connector pipe lookup check for NULL crtc (Jani)
    fixup connector check in ASLE code (Jani)
v3: make sure we take the mode config lock around lookups (Daniel)
v4: fix double unlock in panel_get_brightness (Daniel)
v5: push ASLE work into a work queue (Daniel)
v6: separate ASLE work to a prep patch, rebase (Jani)

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-06 17:56:28 +01:00
Jani Nikula 91a60f2071 drm/i915: move opregion asle request handling to a work queue
Doing this has been long overdue anyway, but now we really need it in
preparation for per connector backlight handling.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-06 17:55:16 +01:00
Ville Syrjälä c164f833cc drm/i915: Sanitize prepare_pipes after valleyview_modeset_global_pipes()
valleyview_modeset_global_pipes() may add pipes that are getting fully
disabled to prepare_pipes bitmask. The rest of the code doesn't expect
this, so clear out any such pipes from the prepare_pipes bitmask.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-06 17:28:36 +01:00
Thomas Hellstrom 59c8e66378 drm/ttm: Fix memory type compatibility check
Also check the busy placements before deciding to move a buffer object.
Failing to do this may result in a completely unneccessary move within a
single memory type.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>
Cc: stable@vger.kernel.org
2013-11-06 04:36:22 -08:00
Thomas Hellstrom da95c788ef drm/ttm: Fix ttm_bo_move_memcpy
All error paths will want to keep the mm node, so handle this at the
function exit. This fixes an ioremap failure error path.
Also add some comments to make the function a bit easier to understand.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>
Cc: stable@vger.kernel.org
2013-11-06 04:36:12 -08:00
Jakob Bornecrantz 9a0599ddea drm/ttm: Handle in-memory region copies
Fix the case where the ttm pointer may be NULL causing
a NULL pointer dereference.

Signed-off-by: Jakob Bornecrantz <jakob@vmware.com>
Signed-off-by: Thomas Hellström <thellstrom@vmware.com>
Cc: stable@vger.kernel.org
2013-11-06 04:35:58 -08:00
Thomas Hellstrom 15205fbcbe drm/ttm: Make NO_EVICT bos available to shrinkers pending destruction
NO_EVICT bos that are not idle when all references are dropped are put on
the delayed destroy list. However, since they are not on LRU lists, they
are not available to shrinkers at that point, and buffers on the delayed
destroy list are not checked very often for idle.

So when these buffers are put on the delayed destroy list, clear the
NO_EVICT flag and put them on the right LRU list. This way they are
immediately available for eviction or shrinkers and will not cause false
OOMS.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>
2013-11-06 04:21:50 -08:00
Thomas Hellstrom cbe12e74ee drm/ttm: Allow vm fault retries
Make use of the FAULT_FLAG_ALLOW_RETRY flag to allow dropping the
mmap_sem while waiting for bo idle.

FAULT_FLAG_ALLOW_RETRY appears to be primarily designed for disk waits
but should work just as fine for GPU waits..

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>
2013-11-06 04:14:43 -08:00
Thomas Hellstrom d92d985177 drm/vmwgfx: Use the linux DMA api to get valid device addresses of pages
The code handles three different cases:
1) physical page addresses. The ttm page array is used.
2) DMA subsystem addresses. A scatter-gather list is used.
3) Coherent pages. The ttm dma pool is used, together with the dma_ttm
array os dma_addr_t

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>
2013-11-06 03:57:16 -08:00
Thomas Hellstrom 7aeb7448d8 drm/ttm: Enable the dma page pool also for intel IOMMUs
Used by the vmwgfx driver

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
2013-11-06 03:55:52 -08:00
Jesse Barnes 7b5562d401 drm/i915/vlv: use PIPE_START_VBLANK interrupts on VLV
This fixes a mismatch between our vblank enable code and our IRQ
handler.  Also, since vblank start events come in before page flips
reliably, it also fixes the kms_flip plain-flip test on my BYT system.

Spotted-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-06 08:37:07 +01:00
Dave Airlie 4695b03970 qxl: add a connector property to denote hotplug should rescan modes.
So GNOME userspace has an issue with when it rescans for modes on hotplug
events, if the monitor has no EDID it assumes that nothing has changed on
EDID as with real hw we'd never have new modes without a new EDID, and they
kind off rely on the behaviour now, however with virtual GPUs we would
like to rescan the modes and get a new preferred mode on hotplug events
to handle dynamic guest resizing (where you resize the host window and the
guest resizes with it).

This is a simple property we can make userspace watch for to trigger new
behaviour based on it, and can be used to replaced EDID hacks in virtual
drivers.

Acked-by: Marc-André Lureau <marcandre.lureau@gmail.com> (on irc)
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-06 15:23:26 +10:00
David Herrmann 8f6599da8e drm: delay minor destruction to drm_dev_free()
Instead of freeing minors in drm_dev_unregister(), we only unplug them and
delay the free to drm_dev_free(). Note that if drm_dev_register() has
never been called, minors are NULL and this has no effect.

This change is needed to allow early device unregistration. If we want to
call drm_dev_unregister() on live devices, we need to guarantee that
minors are still valid (but unplugged). This way, any open file can still
access file_priv->minor->dev to get the DRM device. However, the minor is
unplugged so no new users can occur.

Signed-off-by: David Herrmann <dh.herrmann@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-06 14:53:25 +10:00
David Herrmann f67e946bf2 drm: remove minor-id during unplug
Don't delay minor removal to drm_put_minor(). Otherwise, user-space can
still open the minor and cause the kernel to oops. Instead, remove the
minor during unplug so any new open() will fail to access this minor.

Note that open() and drm_unplug_minor() are both protected by the global
DRM mutex so we're fine.

Signed-off-by: David Herrmann <dh.herrmann@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-06 14:53:24 +10:00
David Herrmann 865fb47f7f drm: cleanup debugfs in drm_unplug_minor()
There is no reason to delay debugfs-cleanup to drm_put_minor(). We should
forbid any access to debugfs files once the device is dead. Chances they
oops once a card was unplugged are very high, anyway.

Signed-off-by: David Herrmann <dh.herrmann@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-06 14:53:24 +10:00
David Herrmann a99ee459fd drm: make drm_get_minor() static
drm_get_minor() is only used in one file. Make it static and add a
kernel-doc comment which documents the current semantics.

Signed-off-by: David Herrmann <dh.herrmann@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-06 14:53:23 +10:00
David Herrmann 4ac387f516 drm: simplify drm_put_minor()
Allow passing NULL as minor to simplify DRM destruction paths. Also remove
the double-pointer reset as it is no longer needed. drm_put_minor() is
only called when the underlying object is destroyed. Hence, resetting
minors to NULL is not necessary.

As drm_put_minor() is no longer used by other DRM files, we can make it
static, too.

Signed-off-by: David Herrmann <dh.herrmann@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-06 14:53:23 +10:00
David Herrmann f73aca50b7 drm: call drm_unplug_minor() from drm_put_minor()
This protects drm_unplug_minor() against repeated calls so we can use it
in drm_put_minor(). This allows us to further simplify it in follow-ups as
we no longer do minor-destruction in both functions but only in
drm_unplug_minor().
Also add kernel-doc comments about what these calls do.

[airlied: fixup for changes to kdev stuff]
Signed-off-by: David Herrmann <dh.herrmann@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-06 14:52:51 +10:00
Ilija Hadzic 02ee4e9455 drm: eliminate bit-copy restoration of crtc
Bit-copying restoration of CRTC structure in failure-recovery
path of drm_crtc_helper_set_config function evokes a
subtle and rare, but very dangerous, corruption of
CRTC mutex structure.

Namely, if drm_crtc_helper_set_config takes the path under
'fail:' label *and* some other process has attempted to
grab the crtc mutex (and got blocked), restoring the CRTC
structure by bit-copying it will overwrite the CRTC mutex
state and the waiters list pointer within the mutex structure.
Consequently the blocked process will never be scheduled.

This patch fixes the issue by eliminating the bit-copy
restoration. The elimination is possible because previous
patches have cleaned up the resoration path so that only
the fields touched by the drm_crtc_helper_set_config function
are saved and restored if necessary.

Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-06 14:27:51 +10:00
Ilija Hadzic 48b1f5ddaa drm: do not set crtc enabled field twice
There is no need to set crtc->enabled field in
drm_crtc_helper_set_config. This is already done (and
properly restored in case of failure) in
drm_crtc_helper_set_mode that is called by
drm_crtc_helper_set_config. Doing it at only one
place makes restoration in case of failure easier.

Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-06 14:27:51 +10:00
Ilija Hadzic 7e99acdcab drm: fix error recovery path in drm_crtc_helper_set_mode
There is no need to save or restore hwmode field, because by
the time this function sets this field, it cannot fail any more.
However, we should save old enabled field because if
the function fails, we want to return with unchanged CRTC.

Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-06 14:27:50 +10:00
Ilija Hadzic fbce40641b drm: restore crtc origin if mode_set_base fails
Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-06 14:27:50 +10:00
Ilija Hadzic bec2eac3a4 drm: eliminate old_fb from drm_crtc_helper_set_config
Old framebuffer is stored in save_set.fb and it is
the same value that is later stored in old_fb.
This makes old_fb redundant so we can replace
it with save_set.fb.

Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-06 14:27:50 +10:00
Ilija Hadzic fc50a890df drm: remove redundant if statement
Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-06 14:27:49 +10:00
Chris Wilson 1020dc6990 drm: Do not drop root privileges for a fancier younger process
When a second process opens the device and master transferrence is
complete, we walk the list of open devices and remove their
authentication. This also revokes our root privilege. Instead of simply
dropping the authentication, this patch reverts the authenticated state
back to its original value.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: David Herrmann <dh.herrmann@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-06 14:27:35 +10:00
Dave Airlie 33e3fd5567 nouveau: drop interrupt busy setting.
This causes problems with never going busy due to ptherm polling,
and after talking to Ben I can't see it being required.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-06 13:50:16 +10:00
Ville Syrjälä ab13096122 drm/sysfs: Remove stale comments about calling drm_sysfs_connector_add() multiple times
drm_connector_sysfs_add() explicitly checks if connector->kdev
is already populated and returns success. So it clearly now allows
being called multiple times. Remove some stale comments to the contrary.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-06 13:41:37 +10:00
Christian König 721529b578 drm/radeon: fix radeon_fence_wait_empty_locked
Don't block forever if there is nothing to wait for.

Signed-off-by: Christian König <christian.koenig@amd.com>
Tested-by: Rafa? Mi?ecki <zajec5@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-06 13:40:59 +10:00
Gerd Hoffmann d9bbf1895f drm/qxl: add some surface memory logging
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-06 13:36:20 +10:00
Gerd Hoffmann 35541782dc drm/qxl: support 64bit surface bar
qxl devices can have a 64bit surface bar, which is quite handy if
you need a bit more surface memory.  So try to use it if it is
present.  Note that this bar might be mapped above 4g.

QEMU command line to check that out:

    qemu-system-x86_64 -m 4g \
        -vga qxl -global qxl-vga.vram64_size_mb=512 \
        $otheroptions

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-06 13:36:20 +10:00
Gerd Hoffmann 121a6a1743 drm/cirrus: use drm_set_preferred_mode
Explicitly set 1024x768 as default mode, so the display doesn't come up
with the largest supported mode.

While being at it drop first three drm_add_modes_noedid calls.  As
drm_add_modes_noedid fills the mode list with modes from the database
*up to* the specified size it is pretty pointless to call it multiple
times with different sizes.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-06 13:36:19 +10:00
Gerd Hoffmann 3cf70dafd7 drm: add drm_set_preferred_mode
New helper function to set the preferred video mode.  Can be called
after drm_add_modes_noedid if you don't want the largest supported
video mode be used by default.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-06 13:36:18 +10:00
Ville Syrjälä 23c453a4af drm: Pretty print pixel format in drm_fb_get_bpp_depth() and format_check()
drm_fb_get_bpp_depth() likes to complain about unsupported pixel formats
but doesn't bother telling us what the format was. Also format_check()
just returns an error when it encouters an invalid format, leaving the
user scratching his head trying to figure out why addfb failed. Make
life a bit easier by using drm_get_format_name() in both places.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-06 13:29:34 +10:00
Ville Syrjälä e7bfa5c407 drm/edid: Yank a helpful comment about EST modes from xf86EdidModes.c
I got very confused when I tried to compare the EST modes with the spec.
Bring over a comment from xf86EdidModes.c that actually describes some
of history where these things came from.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-06 13:27:56 +10:00
Ville Syrjälä 891a74692f drm/edid: Don't skip every eighth EST III mode
Also check the est3 modes whose presence is indicated by bit 0.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-06 13:27:51 +10:00
Ville Syrjälä c068b32a3e drm/edid: Fix the 1792x1344-75 EST III mode
The correct refresh rate for this mode is 75, not 85.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-06 13:27:26 +10:00
Ville Syrjälä 43789b9e08 drm/vmwgfx: Return -ENOENT when a framebuffer can't be found
Let's be a bit more consistent with our error values.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-06 13:25:22 +10:00
Ville Syrjälä 4ae87ff030 drm/vmwgfx: Return -ENOENT when a mode object can't be found
Let's be a bit more consistent with our error values.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-06 13:25:21 +10:00
Ville Syrjälä 10e10d34ee drm/radeon: Return -ENOENT when a mode object can't be found
Let's be a bit more consistent with our error values.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-06 13:25:20 +10:00
Ville Syrjälä 3f2c20572a drm/i915: Return -ENOENT when a mode object can't be found
Let's be a bit more consistent with our error values.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-06 13:25:19 +10:00
Ville Syrjälä 4f22466109 drm/gma500: Return -ENOENT when a mode object can't be found
Let's be a bit more consistent with our error values.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-06 13:25:19 +10:00
Ville Syrjälä 37c4e705fc drm: Return -ENOENT when a framebuffer can't be found
Return -ENOENT for framebuffers like we do for other mode objects that
can't be found.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-11-06 13:25:18 +10:00