- Video-Input and Serial-ATA support on RZ/G2N,
- Color Management Module support on various R-Car Gen3 SoCs,
- Initial support for the R-Car M3-W+ (r8a77961) SoC on the
Salvator-XS board.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCXbxHYgAKCRCKwlD9ZEnx
cNS0AQDofwzZRnNq8xUumbw9fg2I79qhVqqBFYpg+R8qV7qgQQD/WwOfSfE6UlCf
fTfpYowfPX8z985u7/vYDVfSv19d/Ag=
=qA0S
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm64-dt-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt
Renesas ARM64 DT updates for v5.5 (take two)
- Video-Input and Serial-ATA support on RZ/G2N,
- Color Management Module support on various R-Car Gen3 SoCs,
- Initial support for the R-Car M3-W+ (r8a77961) SoC on the
Salvator-XS board.
* tag 'renesas-arm64-dt-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: dts: renesas: Add support for Salvator-XS with R-Car M3-W+
arm64: dts: renesas: Add Renesas R8A77961 SoC support
arm64: dts: renesas: Prepare for rename of ARCH_R8A7796 to ARCH_R8A77960
dt-bindings: clock: Add r8a77961 CPG Core Clock Definitions
dt-bindings: power: Add r8a77961 SYSC power domain definitions
arm64: dts: renesas: r8a774b1: Add SATA controller node
arm64: dts: renesas: rcar-gen3: Add CMM units
arm64: dts: renesas: r8a774b1: Add VIN and CSI-2 support
Link: https://lore.kernel.org/r/20191101155842.31467-5-geert+renesas@glider.be
Signed-off-by: Olof Johansson <olof@lixom.net>
Add RTD1293 and RTD1296 DTs. Add the watchdog for all of RTD129x DTs.
Add reset controllers for RTD129x and start using them for UARTs.
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEF08DRxvMIhphdW+W+i7RLT5+AT8FAl25CJkRHGFmYWVyYmVy
QHN1c2UuZGUACgkQ+i7RLT5+AT8ndw/+PaYt6B92yzw5DwIYmONvSGuqgy51AFdu
Wm6ATtdHGNJllXe7pAHh8a3cQMKAz04N/Xk+kMUfyYtnaQ2fvByS7yiXnMbVqIj7
Q8AmE++ijDM5wTNF45Q3T+Rd7zcMQujElAGu+8l9I4P3iMwItK6LMAAXwCgOelec
8brsLrqbjRNgtICFbds/7fMSn0ZaHiFu5gld07TyPHs5uTtq0raF8wL13X7IgBiB
R70U62ux24Ld4SaFOShrgkJjDlPeZH8DH7bRh5PGlEmp822ZrFI//fc7a0HNpC8R
ygBz2kmErZ1G9xPUwgEWtnTSh4D9QDJxI1btEaBuMbKI96Yaa9PIqV9tHtjJ0eWr
lKEI8ymoFLaNqSQb9sMf7BGYEw/IXF7JAT42SL6APYYPccLezFUjKBRk9hRQBiy7
PNFGXsa+dmvMu5vpYLoyJKmJf8Z7HXkx3buk8rj39ru7AHr37kJdwy3SAqZdH4KZ
vFt1r2bFeBBhB+i9PuSrAVS+oL49UDd2IcB/1lZkvy6Y1waxIkJKZJPQVXnkrvtE
DUiaq8Fcl4iZHmxL3wIKGdldFb77vCERI5cGwMfbh/qCZ8x+3ra4lEwysOAE9dGb
OWO5KkGHIITZkFDQuOJtNcwXXsM2W4EgKmMdfnStFXycim1Wc3V7ACPyB2GuUR4Y
lgdneqA9dpo=
=yVVf
-----END PGP SIGNATURE-----
Merge tag 'realtek-arm64-dt-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-realtek into arm/dt
Realtek ARM64 based SoC DT for v5.5
Add RTD1293 and RTD1296 DTs. Add the watchdog for all of RTD129x DTs.
Add reset controllers for RTD129x and start using them for UARTs.
* tag 'realtek-arm64-dt-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-realtek:
arm64: dts: realtek: Add RTD129x UART resets
arm64: dts: realtek: Add RTD129x reset controller nodes
dt-bindings: reset: Add Realtek RTD1295
arm64: dts: realtek: Add watchdog node for RTD129x
arm64: dts: realtek: Add oscillator for RTD129x
arm64: dts: realtek: Add RTD1296 and Synology DS418
dt-bindings: arm: realtek: Document RTD1296 and Synology DS418
arm64: dts: realtek: Add RTD1293 and Synology DS418j
arm64: dts: realtek: Change dual-license from MIT to BSD
dt-bindings: arm: realtek: Document RTD1293 and Synology DS418j
dt-bindings: arm: realtek: Tidy up conversion to json-schema
Link: https://lore.kernel.org/r/20191030041000.31848-2-afaerber@suse.de
Signed-off-by: Olof Johansson <olof@lixom.net>
On SAM9X60, slewrate should be enabled on pins with a switching frequency
below 50Mhz. Since most of our pins do not exceed this value, we enable
slewrate by default. Pins with a switching value that exceeds 50Mhz will
have to explicitly disable slewrate.
This patch changes the ABI. However, the slewrate macros are only used
by SAM9X60 and, at this moment, there are no device-tree files available
for this platform.
Suggested-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
Link: https://lore.kernel.org/r/20191101092031.24896-1-codrin.ciubotariu@microchip.com
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Clock and Power Domain definitions for the Renesas R-Car M3-W+
(R8A77961) SoC, shared by driver and DT source files.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCXbwQzAAKCRCKwlD9ZEnx
cGA2AQDvA8Uaf/WQ1zzq5GgHPB6R35ciBFCVn3AG+6izUqsCPAEA0FGEHsrNtWyG
rcJ+C/8vBJ+Pe359DmXaELorJ4Xm6wQ=
=EV4L
-----END PGP SIGNATURE-----
Merge tag 'renesas-r8a77961-dt-binding-defs-tag' into renesas-drivers-for-v5.5
Renesas R-Car M3-W+ DT Binding Definitions
Clock and Power Domain definitions for the Renesas R-Car M3-W+
(R8A77961) SoC, shared by driver and DT source files.
Clock and Power Domain definitions for the Renesas R-Car M3-W+
(R8A77961) SoC, shared by driver and DT source files.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCXbwQzAAKCRCKwlD9ZEnx
cGA2AQDvA8Uaf/WQ1zzq5GgHPB6R35ciBFCVn3AG+6izUqsCPAEA0FGEHsrNtWyG
rcJ+C/8vBJ+Pe359DmXaELorJ4Xm6wQ=
=EV4L
-----END PGP SIGNATURE-----
Merge tag 'renesas-r8a77961-dt-binding-defs-tag' into renesas-arm64-dt-for-v5.5
Renesas R-Car M3-W+ DT Binding Definitions
Clock and Power Domain definitions for the Renesas R-Car M3-W+
(R8A77961) SoC, shared by driver and DT source files.
Clock and Power Domain definitions for the Renesas R-Car M3-W+
(R8A77961) SoC, shared by driver and DT source files.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCXbwQzAAKCRCKwlD9ZEnx
cGA2AQDvA8Uaf/WQ1zzq5GgHPB6R35ciBFCVn3AG+6izUqsCPAEA0FGEHsrNtWyG
rcJ+C/8vBJ+Pe359DmXaELorJ4Xm6wQ=
=EV4L
-----END PGP SIGNATURE-----
Merge tag 'renesas-r8a77961-dt-binding-defs-tag' into clk-renesas-for-v5.5
Renesas R-Car M3-W+ DT Binding Definitions
Clock and Power Domain definitions for the Renesas R-Car M3-W+
(R8A77961) SoC, shared by driver and DT source files.
Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car
M3-W+ (R8A77961) SoC, as listed in Table 8.2b ("List of Clocks [R-Car
M3-W/R-Car M3-W+]") of the R-Car Series, 3rd Generation Hardware User's
Manual (Rev. 2.00, Jul. 31, 2019). A gap is added for CSIREF, to
preserve compatibility with the definitions for R-Car M3-W (R8A77960).
Note that internal CPG clocks (S0, S1, S2, S3, SDSRC, SSPSRC, and POST2)
are not included, as they are used as internal clock sources only, and
never referenced from DT.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20191023122941.12342-3-geert+renesas@glider.be
Add power domain indices for the R-Car M3-W+ (R8A77961) SoC.
Based on Rev. 2.00 of the R-Car Series, 3rd Generation, Hardware User’s
Manual (Jul. 31, 2019).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Link: https://lore.kernel.org/r/20191023122911.12166-6-geert+renesas@glider.be
The AST2600 has an explicit gate for the RMII RCLK for each of the four
MACs.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
The AST2500 has an explicit gate for the RMII RCLK for each of the two
MACs.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
OMAP5 device contains an IVA subsystem (Image and Video Accelerator.)
IVA subsystem clkctrl definitions are currently missing, so add them.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tegra186 and later call this clock SOR0_OUT. Rename it on Tegra124 and
Tegra210 to make the names consistent.
Keep the old name for now to keep device trees buildable until they have
all been converted.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add a header with symbolic reset indices for Realtek RTD1295 SoC.
Naming was derived from reset-names in an OEM's Device Tree.
Acked-by: Rob Herring <robh@kernel.org>
[AF: Dropped RTD1295 specific binding definition, updated SPDX]
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
This tag adds support for Meson SM1 ARB resets, Uniphier Pro5 USB3
resets, the Meson-A1 reset controller, SocFPGA Agilex resets, and
Realtek RTD1195/RTD1295 resets.
It adds some reset controller API keywords for get_maintainers.pl and
makes a few remaining reset_control_ops const. Also included are
a conversion of the Qualcomm device tree bindings to yaml and a few
small kerneldoc improvements.
-----BEGIN PGP SIGNATURE-----
iI0EABYIADUWIQRRO6F6WdpH1R0vGibVhaclGDdiwAUCXbbwUxcccC56YWJlbEBw
ZW5ndXRyb25peC5kZQAKCRDVhaclGDdiwEKeAP498UhJ8+GB8PUCpRIPAmFwjAON
n+2EFHTn5Od08ueqqAEA4SH13tR5PJBo6G/J6KgLULUFts4Uc/Hb760/2ai3eQw=
=eyHx
-----END PGP SIGNATURE-----
Merge tag 'reset-for-v5.5' of git://git.pengutronix.de/git/pza/linux into arm/drivers
Reset controller updates for v5.5
This tag adds support for Meson SM1 ARB resets, Uniphier Pro5 USB3
resets, the Meson-A1 reset controller, SocFPGA Agilex resets, and
Realtek RTD1195/RTD1295 resets.
It adds some reset controller API keywords for get_maintainers.pl and
makes a few remaining reset_control_ops const. Also included are
a conversion of the Qualcomm device tree bindings to yaml and a few
small kerneldoc improvements.
* tag 'reset-for-v5.5' of git://git.pengutronix.de/git/pza/linux:
reset: document (devm_)reset_control_get_optional variants
reset: improve of_xlate documentation
reset: simple: Add Realtek RTD1195/RTD1295
reset: simple: Keep alphabetical order
MAINTAINERS: add reset controller framework keywords
reset: zynqmp: Make reset_control_ops const
reset: hisilicon: hi3660: Make reset_control_ops const
reset: build simple reset controller driver for Agilex
reset: add support for the Meson-A1 SoC Reset Controller
dt-bindings: reset: add bindings for the Meson-A1 SoC Reset Controller
reset: uniphier-glue: Add Pro5 USB3 support
dt-bindings: reset: pdc: Convert PDC Global bindings to yaml
dt-bindings: reset: aoss: Convert AOSS reset bindings to yaml
reset: Remove copy'n'paste redundancy in the comments
reset: meson-audio-arb: add sm1 support
reset: dt-bindings: meson: update arb bindings for sm1
Link: https://lore.kernel.org/r/ede6874508472d0917dca770ef80b90626b0f205.camel@pengutronix.de
Signed-off-by: Olof Johansson <olof@lixom.net>
The mipi pll clock comes from the MIPI PHY PLL output, so
it should not be a fixed clock.
MIPI PHY PLL is in the MIPI DSI space, and it is used as
the bit clock for transferring the pixel data out and its
output clock is configured according to the display mode.
So it should be used only for MIPI DSI and not be exported
out for other usages.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
On imx8mn there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2
each with their own gate. Only one of these gates (the one "dividing" by
one) is currently defined and it's incorrectly set as the parent of all
the fixed-factor dividers.
Add the other 8 gates to the clock tree between sys_pll1/2_bypass and
the fixed dividers.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
On imx8mm there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2
each with their own gate. Only one of these gates (the one "dividing" by
one) is currently defined and it's incorrectly set as the parent of all
the fixed-factor dividers.
Add the other 8 gates to the clock tree between sys_pll1/2_bypass and
the fixed dividers.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
On imx8mq there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2
each with their own gate but these gates are not currently defined in
the clock tree.
Add them between sys1/2_pll_out and the fixed dividers.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
power-tree improvements ofr the roc-rk3399-pc, after a long wait
also support for the CR50 TPM device found on some RK3399-Gru devices,
some audio and gmac improvements for NanoPi4 and Rockpro64 as well
as marking the redundant RK_FUNC_x -> x mapping as deprecated and
fixing a missing #msi-cells on rk3399.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAl2tn3IQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgRQcB/4zxlsdUJbwmocLmZadCfBYII1QKdeh2kcr
u4D1T3KuxFjLPCjDcIdZ94+i8iruvXDjPi/PYGBQc63RQmgTud1woEmL5NxBsNOe
TJm9VOHKbkIYxnwSfrkBNTgtmKvxl6H0VWXpUA85f01s7HDAPnk+/8p37Vm22mIa
+MJy6dFHN2/jM6PC9E0rMmS4GEn90b7US0SRHHu2ENtZTH9qKWPW5+9RUqkgQsnl
qvnopEervmbQ0Di50L1KTaeEnzzCgbclc95rGMWmsUwAXe6gS9UmKuVlSogHCSP3
u4h6gsCPW4IwV4lkYVVubDn3eB0r0T8FUSdNIGUqZ0KYPYgPClun
=BXS2
-----END PGP SIGNATURE-----
Merge tag 'v5.5-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt
A lot of improvements for the (till now) somewhat dormant px30 soc,
power-tree improvements ofr the roc-rk3399-pc, after a long wait
also support for the CR50 TPM device found on some RK3399-Gru devices,
some audio and gmac improvements for NanoPi4 and Rockpro64 as well
as marking the redundant RK_FUNC_x -> x mapping as deprecated and
fixing a missing #msi-cells on rk3399.
* tag 'v5.5-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
include: dt-bindings: rockchip: mark RK_FUNC defines as deprecated
arm64: dts: rockchip: restyle rockchip,pins on rk3399-rock-pi-4
arm64: dts: rockchip: Update nanopi4 phy reset properties
arm64: dts: rockchip: Enable nanopi4 HDMI audio
arm64: dts: rockchip: add cr50 tpm to rk3399-gru scarlet and bob
arm64: dts: rockchip: add analog audio nodes on rk3399-rockpro64
arm64: dts: rockchip: add missing #msi-cells to rk3399
arm64: dts: rockchip: Fix roc-rk3399-pc regulator input rails
arm64: dts: rockchip: Rename vcc12v_sys into dc_12v for roc-rk3399-pc
dt-bindings: document PX30 usb2phy General Register Files
arm64: dts: rockchip: add px30-evb i2c1 devices
arm64: dts: rockchip: document explicit px30 cru dependencies
arm64: dts: rockchip: remove unused pin settings from px30
arm64: dts: rockchip: move px30-evb console output to uart 5
arm64: dts: rockchip: add emmc-powersequence to px30-evb
arm64: dts: rockchip: fix the px30-evb power tree
arm64: dts: rockchip: add default px30 emmc pinctrl
arm64: dts: rockchip: remove px30 emmc_pwren pinctrl
arm64: dts: rockchip: remove static xin32k from px30
arm64: dts: rockchip: fix iface clock-name on px30 iommus
Link: https://lore.kernel.org/r/1650793.YZj09CGBNl@phil
Signed-off-by: Olof Johansson <olof@lixom.net>
Document clocks macros with their description
from 'Documentation/devicetree/bindings/sound/samsung-i2s.txt'
Signed-off-by: Maciej Falkowski <m.falkowski@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20190926110219.6144-1-m.szyprowski@samsung.com
Signed-off-by: Mark Brown <broonie@kernel.org>
The defines RK_FUNC_1, RK_FUNC_2, RK_FUNC_3 and RK_FUNC_4
are no longer used. Mark them as "deprecated"
to prevent that someone start using them again.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20191015205852.4200-2-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the audio clock and reset bindings for the sm1 SoC family
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEE9OFZrhjz9W1fG7cb5vwPHDfy2oUFAl2cO+cACgkQ5vwPHDfy
2oXQug//cqVN9hhMgZv+an1DmZbJ2vt2lJvs9ddk2eNodlLC3wvz93YeNyqNn79p
11KNDBtgaorR5o41wfjHSlqZBqQQjhIPKdod/i5xzAJSi/0d6GzahrcUp6jXsE5o
dzImQcGXzhhYpK21JXftq3OBqwEQrML5DgW+ab42IoV8CERCDSavpn/ZYP2RRqBY
+5n1owpW+2f5xp2fkT5T/HGrDEdAbgM3lZEgM4w/2Tp9XpBxHDqbS7iDV7OLV+4/
Mb4zXwB9ra7u/bxEIPi4tpUaruZYfNFd5c3lWOd6nD+218UHo2pF0ZLlaNhw3Xdp
0M9Cyjy5hgqPDWTfmVKkKQKWXY7ys06rvLXowAfaob0SpHKV11QtPnmJYhsmDP60
vQTwi1ejfl/KsmNm6b6OTuRdflRCuDVueUuuX1xIFc30phnoqt99pvjz8GVSzqiX
rx3QdYvhXbi0ioqSjdiu8KITBjdllsfPpO42qMsnU5wOWeOLQk9Ju42yK9IFwjSs
C5aDeo9WEaUHYHJpI+KXdB38BFDEv2qvKz729t/tnenmgq0F+gy1CUPtwIe0rP8J
GxK/KEEgCuwuwL/LcSb9iA7U2ycmDE0G6Kqoh0kTQd698CeIvPiLy9+yNP5HZeyT
2eUFGpKGSyZ25P5SAIHkQ2PSScjsQ5wemsf1jFuJgn/dngPEDkM=
=XPSR
-----END PGP SIGNATURE-----
Merge tag 'clk-meson-dt-v5.5-1' of git://github.com/BayLibre/clk-meson into v5.5/dt64-redo
First round of amlogic DT binding clock update target for v5.5
Add the audio clock and reset bindings for the sm1 SoC family
* tag 'clk-meson-dt-v5.5-1' of git://github.com/BayLibre/clk-meson:
dt-bindings: clock: meson: add sm1 resets to the axg-audio controller
dt-bindings: clk: axg-audio: add sm1 bindings
This clock is needed by DCSS when high resolutions are used.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
CC: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Third version with the adis rework set dropped as better to just have
a fresh version of that at some future date.
The usual mixed backs of new device support being added to drivers,
long term reworks continuing and little per driver cleanups and
features.
Also a few trivial counter subsystem tidy ups on behalf of William.
Core new feature
* Device label support. A long requested feature no one got around to
implementing before. Allows DT based provision of a 'label' that
identifies a device uniquely within a system. This differs from existing
'name' which is meant to be the part number.
New device support
* ingenic-adc
- Support for the JZ4770 SoC ADC including bindings.
* inv_mpu6050
- Add support for magnetometer in MPU925x parts.
Fiddly to do as this is actually a separate device sitting inside the
package, but with the master device being able to schedule reads etc.
Will only run if the auxiliary bus is not in use for any other devices.
Features
* ad7192
- Userspace calibration controls to do zero and full scale.
* st_lsm6dsx
- Enable latched interrupts by default for sensors events with related clear.
- Motion events and related wakeup source. This needed quite a bit of
refactoring as well.
Cleanups and minor features
* ad7192
- sysfs ABI docs
* ad7949
- Remove code to readback configuration word as driver never actually enabled
it.
- Fix incorrect xfer length. Not actually known to cause problems other
than wasted bus usage.
* adis16080
- Replace core mlock usage with local lock with more appropriate scope.
* adis16130
- Remove pointless mlock usage.
* adis16240
- Remove include of gpio.h as no gpio usage.
* atlas-ph-sensor
- Improve logical ordering of buffer predisable / postenable functions.
This is part of a longer term rework Alexandru is driving towards.
* bh1750
- Fix up a static compiler warning and make the code more readable.
- yaml conversion of binding + MAINTAINERS entry.
* bmp280
- Drop a stray newline.
* cm36651
- Drop a redundant assignment
* itg3200
- Alignment cleanup.
* max31856
- Add missing of_node and parent references, useful to identify the device.
* sc27xx_adc
- Use devm_hwspin_lock_request_specific rather than local rolled version.
* stm32-lptimer counter
- kernel-doc warning.
* stm32-timer counter
- kernel-doc warning.
- Alignment cleanup.
* sx9500
- Improve logical ordering of buffer predisable / postenable functions.
This is part of a longer term rework Alexandru is driving towards.
* tcs3414
- Improve logical ordering of buffer predisable / postenable functions.
This is part of a longer term rework Alexandru is driving towards.
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEbilms4eEBlKRJoGxVIU0mcT0FogFAl2i3GIRHGppYzIzQGtl
cm5lbC5vcmcACgkQVIU0mcT0FohHeRAAlZ0gHdNKJ/30vtX2GZQiSE0IrQlbTYVz
5t0Zvm1RWpuHdbMpANtsjPYI5oDUEO34O8520Kl6g/AwIQ6qfqpbaToTZA76fu8M
B7eHO6a+UHL5kKFV5YQS2cDqtDpuPo1SR/0cCe7dDcjwvAm8jeehKtlCUFTVImU5
sMEuaD41Sr8Y5IuTpQIqFaGc4BS0s4NUJ7+fkq6ud3Qlw6CVWdLz0pz/kjnnLJcP
jdr+VRqD6x+gXrujX+1iaeFu+r2dF+a9z3aPgr8vJj/6asnY0uihs82YTuL2v4Wb
tBM3MKooTQt1zgrCEO7n/+GzC02pXbQ8mRPI2H1eOl4jaJhyttkSNztEo9k4EQ3N
wYbAvc97yWNVthHd/2z7rDYf3SntN8nqjCkeuvn83P/6uhQS9EzSiVV2hkUda0K0
y1ZKOTDH0W+jCFITCtrDR1GLdV6GLPiv1AlG5l9AXyUfRBFBRWg9duLFYeVsVouu
g3yxzO0PbsNKMbPqjwT+YzNCd4/QKpuU7/+WTBSNUVo428i/p3lpnXQyhJiQrWIE
3TH+pj6Es8WYNmuRw3h9bMTjxca9Esk/e6MZ8vnOFUKrHB1T1iQB+rSsascZQM9a
+uv+d2x27KVUqotP8DLat1FYHDIbaIScKJioAWsLepscpBucJ3ayHq5yOFGXXp9i
KKqT9ObTUfw=
=nIWU
-----END PGP SIGNATURE-----
Merge tag 'iio-for-5.5a-take3' of https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into staging-next
Jonathan writes:
First set of IIO new device support, cleanups and features for the 5.5 cycle
Third version with the adis rework set dropped as better to just have
a fresh version of that at some future date.
The usual mixed backs of new device support being added to drivers,
long term reworks continuing and little per driver cleanups and
features.
Also a few trivial counter subsystem tidy ups on behalf of William.
Core new feature
* Device label support. A long requested feature no one got around to
implementing before. Allows DT based provision of a 'label' that
identifies a device uniquely within a system. This differs from existing
'name' which is meant to be the part number.
New device support
* ingenic-adc
- Support for the JZ4770 SoC ADC including bindings.
* inv_mpu6050
- Add support for magnetometer in MPU925x parts.
Fiddly to do as this is actually a separate device sitting inside the
package, but with the master device being able to schedule reads etc.
Will only run if the auxiliary bus is not in use for any other devices.
Features
* ad7192
- Userspace calibration controls to do zero and full scale.
* st_lsm6dsx
- Enable latched interrupts by default for sensors events with related clear.
- Motion events and related wakeup source. This needed quite a bit of
refactoring as well.
Cleanups and minor features
* ad7192
- sysfs ABI docs
* ad7949
- Remove code to readback configuration word as driver never actually enabled
it.
- Fix incorrect xfer length. Not actually known to cause problems other
than wasted bus usage.
* adis16080
- Replace core mlock usage with local lock with more appropriate scope.
* adis16130
- Remove pointless mlock usage.
* adis16240
- Remove include of gpio.h as no gpio usage.
* atlas-ph-sensor
- Improve logical ordering of buffer predisable / postenable functions.
This is part of a longer term rework Alexandru is driving towards.
* bh1750
- Fix up a static compiler warning and make the code more readable.
- yaml conversion of binding + MAINTAINERS entry.
* bmp280
- Drop a stray newline.
* cm36651
- Drop a redundant assignment
* itg3200
- Alignment cleanup.
* max31856
- Add missing of_node and parent references, useful to identify the device.
* sc27xx_adc
- Use devm_hwspin_lock_request_specific rather than local rolled version.
* stm32-lptimer counter
- kernel-doc warning.
* stm32-timer counter
- kernel-doc warning.
- Alignment cleanup.
* sx9500
- Improve logical ordering of buffer predisable / postenable functions.
This is part of a longer term rework Alexandru is driving towards.
* tcs3414
- Improve logical ordering of buffer predisable / postenable functions.
This is part of a longer term rework Alexandru is driving towards.
* tag 'iio-for-5.5a-take3' of https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio: (41 commits)
iio: pressure: bmp280: remove stray newline
iio: adc: sc27xx: Use devm_hwspin_lock_request_specific() to simplify code
iio: chemical: atlas-ph-sensor: fix iio_triggered_buffer_predisable() position
iio: gyro: clean up indentation issue
counter: stm32: clean up indentation issue
iio: proximity: sx9500: fix iio_triggered_buffer_{predisable,postenable} positions
iio: core: Add optional symbolic label to device attributes
dt-binding: iio: Add optional label property
iio: gyro: adis16080: replace mlock with own lock
counter: stm32-lptimer-cnt: fix a kernel-doc warning
counter: stm32-timer-cnt: fix a kernel-doc warning
iio: gyro: adis16130: remove mlock usage
MAINTAINERS: add entry for ROHM BH1750 driver
dt-bindings: iio: light: bh1750: convert bindings to yaml
iio: imu: st_lsm6dsx: add motion report function and call from interrupt
iio: imu: st_lsm6dsx: always enter interrupt thread
iio: imu: st_lsm6dsx: add wakeup-source option
iio: imu: st_lsm6dsx: add motion events
iio: imu: st_lsm6dsx: move interrupt thread to core
iio: imu: inv_mpu6050: add fifo support for magnetometer data
...
Add DT bindings for the Meson-A1 SoC Reset Controller include file,
and also slightly update documentation.
Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Add the reset id of the sm1 audio clock controller
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Add the compatible and clock ids of the sm1 audio clock controller
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
The MSM8956/76 SoCs have two main voltage-level power domains, VDD_CX
and VDD_MX, which also have their own voltage-floor-level (VFL)
corner.
Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The RPM_SMD_LEVEL_TURBO_HIGH is used by MSM8956/8976 and APQ variants:
add the definition.
Signed-off-by: Angelo G. Del Regno <kholk11@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
SM1 SoC family adds two new audio FIFOs with the related arb reset lines
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Add all RZ/G2N Clock Pulse Generator Core Clock Outputs, as listed in
Table 8.2d ("List of Clocks [RZ/G2N]") of the RZ/G2N Hardware User's
Manual.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Link: https://lore.kernel.org/r/1567666360-28035-1-git-send-email-biju.das@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
- boot_mem_map is removed, providing a nice cleanup made possible by the
recent removal of bootmem.
- Some fixes to atomics, in general providing compiler barriers for
smp_mb__{before,after}_atomic plus fixes specific to Loongson CPUs or
MIPS32 systems using cmpxchg64().
- Conversion to the new generic VDSO infrastructure courtesy of Vincenzo
Frascino.
- Removal of undefined behavior in set_io_port_base(), fixing the
behavior of some MIPS kernel configurations when built with recent
clang versions.
- Initial MIPS32 huge page support, functional on at least Ingenic SoCs.
- pte_special() is now supported for some configurations, allowing among
other things generic fast GUP to be used.
- Miscellaneous fixes & cleanups.
And platform specific changes:
- Major improvements to Ingenic SoC support from Paul Cercueil, mostly
enabled by the inclusion of the new TCU (timer-counter unit) drivers
he's spent a very patient year or so working on. Plus some fixes for
X1000 SoCs from Zhou Yanjie.
- Netgear R6200 v1 systems are now supported by the bcm47xx platform.
- DT updates for BMIPS, Lantiq & Microsemi Ocelot systems.
-----BEGIN PGP SIGNATURE-----
iIsEABYIADMWIQRgLjeFAZEXQzy86/s+p5+stXUA3QUCXYaqpRUccGF1bC5idXJ0
b25AbWlwcy5jb20ACgkQPqefrLV1AN2JUQD+PQGFIlq9bo/3vLyqsXJffm+DhwVQ
4WSCSeN5brPkO8EA/153sRJBlRtG+KK5p9f7WYKUuBfbcEawuc1uwmKuy7cG
=lWlM
-----END PGP SIGNATURE-----
Merge tag 'mips_5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS updates from Paul Burton:
"Main MIPS changes:
- boot_mem_map is removed, providing a nice cleanup made possible by
the recent removal of bootmem.
- Some fixes to atomics, in general providing compiler barriers for
smp_mb__{before,after}_atomic plus fixes specific to Loongson CPUs
or MIPS32 systems using cmpxchg64().
- Conversion to the new generic VDSO infrastructure courtesy of
Vincenzo Frascino.
- Removal of undefined behavior in set_io_port_base(), fixing the
behavior of some MIPS kernel configurations when built with recent
clang versions.
- Initial MIPS32 huge page support, functional on at least Ingenic
SoCs.
- pte_special() is now supported for some configurations, allowing
among other things generic fast GUP to be used.
- Miscellaneous fixes & cleanups.
And platform specific changes:
- Major improvements to Ingenic SoC support from Paul Cercueil,
mostly enabled by the inclusion of the new TCU (timer-counter unit)
drivers he's spent a very patient year or so working on. Plus some
fixes for X1000 SoCs from Zhou Yanjie.
- Netgear R6200 v1 systems are now supported by the bcm47xx platform.
- DT updates for BMIPS, Lantiq & Microsemi Ocelot systems"
* tag 'mips_5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (89 commits)
MIPS: Detect bad _PFN_SHIFT values
MIPS: Disable pte_special() for MIPS32 with RiXi
MIPS: ralink: deactivate PCI support for SOC_MT7621
mips: compat: vdso: Use legacy syscalls as fallback
MIPS: Drop Loongson _CACHE_* definitions
MIPS: tlbex: Remove cpu_has_local_ebase
MIPS: tlbex: Simplify r3k check
MIPS: Select R3k-style TLB in Kconfig
MIPS: PCI: refactor ioc3 special handling
mips: remove ioremap_cachable
mips/atomic: Fix smp_mb__{before,after}_atomic()
mips/atomic: Fix loongson_llsc_mb() wreckage
mips/atomic: Fix cmpxchg64 barriers
MIPS: Octeon: remove duplicated include from dma-octeon.c
firmware: bcm47xx_nvram: Allow COMPILE_TEST
firmware: bcm47xx_nvram: Correct size_t printf format
MIPS: Treat Loongson Extensions as ASEs
MIPS: Remove dev_err() usage after platform_get_irq()
MIPS: dts: mscc: describe the PTP ready interrupt
MIPS: dts: mscc: describe the PTP register range
...
This is some material that we picked up into our tree late or
that had complex inter-depondencies. The fact that there are these
interdependencies tends to meant that these are often actually the most
interesting new additions:
The new Aspeed AST2600 baseboard management controller is added, this
is a Cortex-A7 based follow-up to the ARM11 based AST2500 and had some
dependencies on other device drivers.
After many years, support for the MMP2 based OLPC XO-1.75 finally makes
it into the kernel.
The Armada 3720 based Turris Mox open source router platform is a late
addition and it follows some preparatory work across multiple branches.
The OMAP2+ platform had some large-scale cleanup involving driver
changes and DT changes, here we finish it off, dropping a lot of the
now-unused platform data.
The TI K3 platform that got added for 5.3 gains a lot more support
for individual bits on the SoC, this part just came late for the
merge window.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABCAAGBQJdf6P3AAoJEJpsee/mABjZMFUP/i/J9CNJjEec0cWCG1XgP/qh
SpKFf2g9Y9QzqAzDDovo7atTGHTCG8C0fn8W+bkv9h7dWj2uxRtFISM9COomUoHa
0qXUL9bbDB3LAvstLV451p4c67XsJUazV9KZPD7VsCquucWbDDYaGPz+0reSRm6y
imK2jXqD0leG0CNbgRXfh64J32TF3M0/XnwbsNJreCmQvwUvkYLL5VNi/qcnvfyp
k0g1/5OzH9mLertoVKWqJ9o1919Yvxdl6/eyDmTPmX08bs03WnPbCEzRVO/zkOKZ
O6RcAlsjiLblQdfbDJKfbaYDDaE53d2NwdCvBIdSPmDoYM5eYjQC4PmDM0+0dmHe
bFd9giBjzU2Uab7ylgeoVl6pX1ISk6bwmZxNup45cy0xyw8wuky02Wq2bQTuZbgI
UcBlOGWR4aH/OCpNafn+ovDBYGc64I7EQobG7UiilrVq/libx1Uo7yjlWSxe4j8n
wFchiB8It24WUiS4JhJFrTklkaf5JW3K3czdDATW7aZKjv+fnHU5GMre/hvNP4z7
qROlP69/eqNXG25VOcwWPQE8yhP43+ZgyvoVwDh1H6VZdy9WxgYyEoiBAhFfcrng
+RVAT4rzylPmKP8oygVF1fpTHTS8xHrYBbjkdRaj5KqmTDdqI/nMsYoq+E0R1ScV
EsnyNVq7wnvH12zrOv+I
=Qtkp
-----END PGP SIGNATURE-----
Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC late updates from Arnd Bergmann:
"This is some material that we picked up into our tree late or that had
complex inter-depondencies. The fact that there are these
interdependencies tends to meant that these are often actually the
most interesting new additions:
- The new Aspeed AST2600 baseboard management controller is added,
this is a Cortex-A7 based follow-up to the ARM11 based AST2500 and
had some dependencies on other device drivers.
- After many years, support for the MMP2 based OLPC XO-1.75 finally
makes it into the kernel.
- The Armada 3720 based Turris Mox open source router platform is a
late addition and it follows some preparatory work across multiple
branches.
- The OMAP2+ platform had some large-scale cleanup involving driver
changes and DT changes, here we finish it off, dropping a lot of
the now-unused platform data.
- The TI K3 platform that got added for 5.3 gains a lot more support
for individual bits on the SoC, this part just came late for the
merge window"
[ This pull request itself wasn't actually sent late at all by Arnd, but
I waited on the branches that it used to be pulled first, so it ends
up being merged much later than the other ARM SoC pull requests this
merge window - Linus ]
* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (57 commits)
ARM: dts: dir685: Drop spi-cpol from the display
ARM: dts: aspeed: Add AST2600 pinmux nodes
ARM: dts: aspeed: Add AST2600 and EVB
ARM: exynos: Enable support for ARM architected timers
ARM: samsung: Fix system restart on S3C6410
ARM: dts: mmp2: add OLPC XO 1.75 machine
ARM: dts: mmp2: rename the USB PHY node
ARM: dts: mmp2: specify reg-shift for the UARTs
ARM: dts: mmp2: add camera interfaces
ARM: dts: mmp2: fix the SPI nodes
ARM: dts: mmp2: trivial whitespace fix
arm64: dts: marvell: add DTS for Turris Mox
dt-bindings: marvell: document Turris Mox compatible
arm64: dts: marvell: armada-37xx: add SPI CS1 pinctrl
arm64: dts: ti: k3-j721e-main: Fix gic-its node unit-address
arm64: dts: ti: k3-am65-main: Fix gic-its node unit-address
arm64: dts: ti: k3-j721e-main: Add hwspinlock node
arm64: dts: ti: k3-am65-main: Add hwspinlock node
arm64: dts: k3-j721e: Add gpio-keys on common processor board
dt-bindings: pinctrl: k3: Introduce pinmux definitions for J721E
...
clk registration by clk providers and debugfs "nice to haves" for rate
constraints. I'll highlight that we're now setting the clk_init_data pointer
inside struct clk_hw to NULL during clk_register(), which may break some
drivers that thought they could use that pointer during normal operations. That
change has been sitting in next for a while now but maybe something is still
broken. We'l see. Other than that the core framework changes aren't invasive
and they're fixing bugs, simplifying, and making things better.
On the clk driver side we got the usual addition of new SoC support, new
features for existing drivers, and bug fixes scattered throughout. The biggest
diffstat is the Amlogic driver that gained CPU clk support in addition to
migrating to the new way of specifying clk parents. After that the Qualcomm,
i.MX, Mediatek, and Rockchip clk drivers got support for various new SoCs and
clock controllers from those vendors.
Core:
- Drop NULL checks in clk debugfs
- Add min/max rates to clk debugfs
- Set clk_init_data pointer inside clk_hw to NULL after registration
- Make clk_bulk_get_all() return an 'id' corresponding to clock-names
- Evict parents from parent cache when they're unregistered
New Drivers:
- Add clock driver for i.MX8MN SoCs
- Support aspeed AST2600 SoCs
- Support for Mediatek MT6779 SoCs
- Support qcom SM8150 GCC and RPMh clks
- Support qcom QCS404 WCSS clks
- Add CPU clock support for Armada 7K/8K (specifically AP806 and AP807)
- Addition of clock driver for Rockchip rk3308 SoCs
Updates:
- Add regulator support to the cdce925 clk driver
- Add support for Raspberry Pi 4 bcm2711 SoCs
- Add SDIO gate support to aspeed driver
- Add missing of_node_put() calls in various clk drivers
- Migrate Amlogic driver to new clock parent description method
- Add DVFS support to Amlogic Meson g12
- Add Amlogic Meson g12a reset support to the axg audio clock controller
- Add sm1 support to the Amlogic Meson g12a clock controller
- Switch i.MX8MM clock driver to platform driver
- Add Hifi4 DSP related clocks for i.MX8QXP SoC
- Fix Audio PLL setting and parent clock for USB
- Misc i.MX8 clock driver improvements and corrections
- Set floor ops for Qualcomm SD clks so that rounding works
- Fix "always-on" Clock Domains on Renesas R-Car M1A, RZ/A1, RZ/A2, and RZ/N1
- Enable the Allwinner V3 SoC and fix the i2s clock for H6
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAl2FQEMRHHNib3lkQGtl
cm5lbC5vcmcACgkQrQKIl8bklSXHQw//XHnT5DPphpP8ua4x8wuJARdf0n58Vcdb
8fZxxs4QN7uuKhg6aMI4kgwBn+9tgIr65hvN0Gn9Wm5Bsbs3XZvdIo7DvQDrYg7W
NE7192iy2Dg+m+C24YLO7ceZgqVepbjeN+6oeUK88Ui+H+XlOKfJvjfnJ+HxN9Ip
sHnLakIxqlaWvzwTUOHOcsrHyQD2OXupbfNMxLnmr8T/kBh/nqwNEG3aYCppICsg
LpJL9Bv2V3QSk8uBszTgKK5ybWo14aDQPx4rrhgsneD0h7DSnx6M3jvngxMra6W0
fnare4FQlkbPmgAj+XtB7RdCzsuwoke/7TJsvDLQrEbyOYTGnl7bYS8NOSrIg5Tp
w4UPpXrMTQK7e/6okL1OJYAXXYurxep8QjsjpF3nahxC3IVzAZ9uio6ehJrDNEPC
ErqOSPQTMkjOA2npovsQKCH3Mv/yGzAigpsQassPneWwp//NupMLKmmIm6645Xw2
6kqSlVFYz81lhzIylGEQKIoiLcszpB6qqWUzGVt0B94joRbvg0m//8BDaZbHeTqP
m/acRYHRC1utpkAZEnBZRsd79cI+EeuARROUfGsoUMfOueTc4+qQ7Yrjbj4rTvnC
lLM9Qz9h1QkfyRF1IHHPw/fS5twpNTUdO9c1+3qzS3AQfl5dZWpChoF9Um+ycVPR
nQrpk05pHEY=
=z8wK
-----END PGP SIGNATURE-----
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"We have a small collection of core framework updates this time, mostly
around clk registration by clk providers and debugfs "nice to haves"
for rate constraints. I'll highlight that we're now setting the
clk_init_data pointer inside struct clk_hw to NULL during
clk_register(), which may break some drivers that thought they could
use that pointer during normal operations. That change has been
sitting in next for a while now but maybe something is still broken.
We'l see. Other than that the core framework changes aren't invasive
and they're fixing bugs, simplifying, and making things better.
On the clk driver side we got the usual addition of new SoC support,
new features for existing drivers, and bug fixes scattered throughout.
The biggest diffstat is the Amlogic driver that gained CPU clk support
in addition to migrating to the new way of specifying clk parents.
After that the Qualcomm, i.MX, Mediatek, and Rockchip clk drivers got
support for various new SoCs and clock controllers from those vendors.
Core:
- Drop NULL checks in clk debugfs
- Add min/max rates to clk debugfs
- Set clk_init_data pointer inside clk_hw to NULL after registration
- Make clk_bulk_get_all() return an 'id' corresponding to clock-names
- Evict parents from parent cache when they're unregistered
New Drivers:
- Add clock driver for i.MX8MN SoCs
- Support aspeed AST2600 SoCs
- Support for Mediatek MT6779 SoCs
- Support qcom SM8150 GCC and RPMh clks
- Support qcom QCS404 WCSS clks
- Add CPU clock support for Armada 7K/8K (specifically AP806 and AP807)
- Addition of clock driver for Rockchip rk3308 SoCs
Updates:
- Add regulator support to the cdce925 clk driver
- Add support for Raspberry Pi 4 bcm2711 SoCs
- Add SDIO gate support to aspeed driver
- Add missing of_node_put() calls in various clk drivers
- Migrate Amlogic driver to new clock parent description method
- Add DVFS support to Amlogic Meson g12
- Add Amlogic Meson g12a reset support to the axg audio clock controller
- Add sm1 support to the Amlogic Meson g12a clock controller
- Switch i.MX8MM clock driver to platform driver
- Add Hifi4 DSP related clocks for i.MX8QXP SoC
- Fix Audio PLL setting and parent clock for USB
- Misc i.MX8 clock driver improvements and corrections
- Set floor ops for Qualcomm SD clks so that rounding works
- Fix "always-on" Clock Domains on Renesas R-Car M1A, RZ/A1, RZ/A2, and RZ/N1
- Enable the Allwinner V3 SoC and fix the i2s clock for H6"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (137 commits)
clk: Drop !clk checks in debugfs dumping
clk: imx: imx8mn: fix pll mux bit
clk: imx: imx8mm: fix pll mux bit
clk: imx: clk-pll14xx: unbypass PLL by default
clk: imx: pll14xx: avoid glitch when set rate
clk: mvebu: ap80x: add AP807 clock support
clk: mvebu: ap806: Prepare the introduction of AP807 clock support
clk: mvebu: ap806: add AP-DCLK (hclk) to system controller driver
clk: mvebu: ap806: be more explicit on what SaR is
clk: mvebu: ap80x-cpu: add AP807 CPU clock support
clk: mvebu: ap806-cpu: prepare mapping of AP807 CPU clock
dt-bindings: ap806: Document AP807 clock compatible
dt-bindings: ap80x: Document AP807 CPU clock compatible
clk: sprd: add missing kfree
clk: at91: allow 24 Mhz clock as input for PLL
clk: Make clk_bulk_get_all() return a valid "id"
clk: actions: Fix factor clk struct member access
clk: qcom: rcg: Return failure for RCG update
clk: remove extra ---help--- tags in Kconfig
clk: add include guard to clk-conf.h
...
- Support qcom SM8150 RPMh clks
- Set floor ops for qcom sd clks
- Support qcom QCS404 WCSS clks
- Support for Mediatek MT6779 SoCs
- Add CPU clock support for Armada 7K/8K (specifically AP806 and AP807)
* clk-qcom:
clk: qcom: rcg: Return failure for RCG update
clk: qcom: fix QCS404 TuringCC regmap
clk: qcom: clk-rpmh: Add support for SM8150
dt-bindings: clock: Document SM8150 rpmh-clock compatible
clk: qcom: clk-rpmh: Convert to parent data scheme
dt-bindings: clock: Document the parent clocks
clk: qcom: gcc: Use floor ops for SDCC clocks
clk: qcom: gcc-qcs404: Use floor ops for sdcc clks
clk: qcom: gcc-sdm845: Use floor ops for sdcc clks
clk: qcom: define probe by index API as common API
clk: qcom: Add WCSS gcc clock control for QCS404
clk: qcom: msm8916: Don't build by default
clk: qcom: gcc: Add global clock controller driver for SM8150
dt-bindings: clock: Document gcc bindings for SM8150
clk: qcom: clk-alpha-pll: Add support for Trion PLLs
clk: qcom: clk-alpha-pll: Remove post_div_table checks
clk: qcom: clk-alpha-pll: Remove unnecessary cast
* clk-mtk:
clk: mediatek: Runtime PM support for MT8183 mcucfg clock provider
clk: mediatek: Register clock gate with device
clk: mediatek: add pericfg clocks for MT8183
dt-bindings: clock: mediatek: add pericfg for MT8183
clk: mediatek: Add MT6779 clock support
clk: mediatek: Add dt-bindings for MT6779 clocks
dt-bindings: mediatek: bindings for MT6779 clk
clk: reset: Modify reset-controller driver
* clk-armada:
clk: mvebu: ap80x: add AP807 clock support
clk: mvebu: ap806: Prepare the introduction of AP807 clock support
clk: mvebu: ap806: add AP-DCLK (hclk) to system controller driver
clk: mvebu: ap806: be more explicit on what SaR is
clk: mvebu: ap80x-cpu: add AP807 CPU clock support
clk: mvebu: ap806-cpu: prepare mapping of AP807 CPU clock
dt-bindings: ap806: Document AP807 clock compatible
dt-bindings: ap80x: Document AP807 CPU clock compatible
clk: mvebu: ap806: Fix clock name for the cluster
clk: mvebu: add CPU clock driver for Armada 7K/8K
clk: mvebu: add helper file for Armada AP and CP clocks
dt-bindings: ap806: add the cluster clock node in the syscon file
* clk-ingenic:
clk: ingenic: Use CLK_OF_DECLARE_DRIVER macro
clk: ingenic/jz4740: Fix "pll half" divider not read/written properly
* clk-meson: (23 commits)
clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocks
clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clock
clk: meson: g12a: add support for SM1 GP1 PLL
dt-bindings: clk: meson: add sm1 periph clock controller bindings
clk: meson: axg-audio: add g12a reset support
dt-bindings: clock: meson: add resets to the audio clock controller
clk: meson: g12a: expose CPUB clock ID for G12B
clk: meson: g12a: add notifiers to handle cpu clock change
clk: meson: add g12a cpu dynamic divider driver
clk: core: introduce clk_hw_set_parent()
clk: meson: remove clk input helper
clk: meson: remove ee input bypass clocks
clk: meson: clk-regmap: migrate to new parent description method
clk: meson: meson8b: migrate to the new parent description method
clk: meson: axg: migrate to the new parent description method
clk: meson: gxbb: migrate to the new parent description method
clk: meson: g12a: migrate to the new parent description method
clk: meson: remove ao input bypass clocks
clk: meson: axg-aoclk: migrate to the new parent description method
clk: meson: gxbb-aoclk: migrate to the new parent description method
...
- A bunch of DT binding conversions to DT schema format
- Clean-ups of the Arm idle-states binding
- Support a default number of cells in of_for_each_phandle() when the
cells name is missing
- Expose dtbs_check and dt_binding_check in the make help
- Convert writting-schema.md to ReST
- HiSilicon reset controller binding updates
- Add documentation for MT8516 RNG
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEEktVUI4SxYhzZyEuo+vtdtY28YcMFAl2Dj38QHHJvYmhAa2Vy
bmVsLm9yZwAKCRD6+121jbxhw4qcEACE16/eR0h9FSnhN0QpyFlGrfUTy86K5Z4N
IoJsGind4G7+TrNA6GGZwQkNRt3roWdrkqnLLvcted+8IVaXOFm0n12w2u0yoYvk
C4pqxH2HRUC9U9eBjyDxdiplH9yYZPuy8bFwLPSQk0bkCd6D3I8iDe6qHm1arin3
sYIQ03jbZKowHixOuMNvu9rBiun79Lm5FfGUSi7EYab3KZ4Zt9HX1IiySRYVOWZT
z6bjWbVfFe7HgbImwaB+WUYumUyNu5dh4AyqIidb9o6BB6ZENfnBNWPi0VDFuSGT
4wVc8XrcU3d7bt6Sstt+g3WZjn+JBMLNBkNnMjZ+nlp3OoR5F6Tf1RO6mrZtsENa
sAspr18zNQK7CNBy0uKzBT32Z0oN1wXnsKRS5P1o5/8aEjRr0m8stxes3hOQhtuJ
Y6rKLN9kGrQIeSY7nagWuGFaJ1uunGXCSgam+kb6YI8nDa3DUbzeIhYMIcqgz/Sx
Gx2txPzKMHXgzF7Zc+5db9X3E7pg8Y1zrhk7o2oKiFVWrnwlEJivMcRHq9n3anOr
RGAJPjrRfzwZNIQgYNflYHAdxVLyKKhpxEQDdo/5PXeMRYtghOH+rIxwoS31FHSs
u/4nf0uHFQfkmSg7nSKicfSWt5ORR5G/H9cc83SRoix35kfPubirkawJ/tkcVuO4
3n0NeGERtA==
=ZO6c
-----END PGP SIGNATURE-----
Merge tag 'devicetree-for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull Devicetree updates from Rob Herring:
- a bunch of DT binding conversions to DT schema format
- clean-ups of the Arm idle-states binding
- support a default number of cells in of_for_each_phandle() when the
cells name is missing
- expose dtbs_check and dt_binding_check in the make help
- convert writting-schema.md to ReST
- HiSilicon reset controller binding updates
- add documentation for MT8516 RNG
* tag 'devicetree-for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (46 commits)
of: restore old handling of cells_name=NULL in of_*_phandle_with_args()
bus: qcom: fix spelling mistake "ambigous" -> "ambiguous"
of: Let of_for_each_phandle fallback to non-negative cell_count
iommu: pass cell_count = -1 to of_for_each_phandle with cells_name
dt-bindings: arm: Convert Realtek board/soc bindings to json-schema
dt-bindings: arm: Convert Actions Semi bindings to jsonschema
dt-bindings: Correct spelling in example schema
dt-bindings: cpu: Add a support cpu type for cortex-a55
dt-bindings: gpu: mali-midgard: Add samsung exynos5250 compatible
dt-bindings: arm: idle-states: Move exit-latency-us explanation
dt-bindings: arm: idle-states: Add punctuation to improve readability
dt-bindings: arm: idle-states: Correct "constraint guarantees"
dt-bindings: arm: idle-states: Correct references to wake-up delay
dt-bindings: arm: idle-states: Use "e.g." and "i.e." consistently
pinctrl-mcp23s08: Fix property-name in dt-example
dt-bindings: Clarify interrupts-extended usage
dt-bindings: Convert Arm Mali Utgard GPU to DT schema
dt-bindings: Convert Arm Mali Bifrost GPU to DT schema
dt-bindings: Convert Arm Mali Midgard GPU to DT schema
dt-bindings: irq: Convert Allwinner NMI Controller to a schema
...
Here is the big char/misc driver pull request for 5.4-rc1.
As has been happening in previous releases, more and more individual
driver subsystem trees are ending up in here. Now if that is good or
bad I can't tell, but hopefully it makes your life easier as it's more
of an aggregation of trees together to one merge point for you.
Anyway, lots of stuff in here:
- habanalabs driver updates
- thunderbolt driver updates
- misc driver updates
- coresight and intel_th hwtracing driver updates
- fpga driver updates
- extcon driver updates
- some dma driver updates
- char driver updates
- android binder driver updates
- nvmem driver updates
- phy driver updates
- parport driver fixes
- pcmcia driver fix
- uio driver updates
- w1 driver updates
- configfs fixes
- other assorted driver updates
All of these have been in linux-next for a long time with no reported
issues.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-----BEGIN PGP SIGNATURE-----
iG0EABECAC0WIQT0tgzFv3jCIUoxPcsxR9QN2y37KQUCXYIT1g8cZ3JlZ0Brcm9h
aC5jb20ACgkQMUfUDdst+ym9lwCgrHZlMMvfYNVm6GQ5ge58JJsVTL4AoNatTcL4
hfVMA6pCHWBjV65xVSf6
=Tijw
-----END PGP SIGNATURE-----
Merge tag 'char-misc-5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull char/misc driver updates from Greg KH:
"Here is the big char/misc driver pull request for 5.4-rc1.
As has been happening in previous releases, more and more individual
driver subsystem trees are ending up in here. Now if that is good or
bad I can't tell, but hopefully it makes your life easier as it's more
of an aggregation of trees together to one merge point for you.
Anyway, lots of stuff in here:
- habanalabs driver updates
- thunderbolt driver updates
- misc driver updates
- coresight and intel_th hwtracing driver updates
- fpga driver updates
- extcon driver updates
- some dma driver updates
- char driver updates
- android binder driver updates
- nvmem driver updates
- phy driver updates
- parport driver fixes
- pcmcia driver fix
- uio driver updates
- w1 driver updates
- configfs fixes
- other assorted driver updates
All of these have been in linux-next for a long time with no reported
issues"
* tag 'char-misc-5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (200 commits)
misc: mic: Use PTR_ERR_OR_ZERO rather than its implementation
habanalabs: correctly cast variable to __le32
habanalabs: show correct id in error print
habanalabs: stop using the acronym KMD
habanalabs: display card name as sensors header
habanalabs: add uapi to retrieve aggregate H/W events
habanalabs: add uapi to retrieve device utilization
habanalabs: Make the Coresight timestamp perpetual
habanalabs: explicitly set the queue-id enumerated numbers
habanalabs: print to kernel log when reset is finished
habanalabs: replace __le32_to_cpu with le32_to_cpu
habanalabs: replace __cpu_to_le32/64 with cpu_to_le32/64
habanalabs: Handle HW_IP_INFO if device disabled or in reset
habanalabs: Expose devices after initialization is done
habanalabs: improve security in Debug IOCTL
habanalabs: use default structure for user input in Debug IOCTL
habanalabs: Add descriptive name to PSOC app status register
habanalabs: Add descriptive names to PSOC scratch-pad registers
habanalabs: create two char devices per ASIC
habanalabs: change device_setup_cdev() to be more generic
...
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQUwxxKyE5l/npt8ARiEGxRG/Sl2wUCXYAIeQAKCRBiEGxRG/Sl
2/SzAQDEnoNxzV/R5kWFd+2kmFeY3cll0d99KMrWJ8om+kje6QD/cXxZHzFm+T1L
UPF66k76oOODV7cyndjXnTnRXbeCRAM=
=Szby
-----END PGP SIGNATURE-----
Merge tag 'leds-for-5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/j.anaszewski/linux-leds
Pull LED updates from Jacek Anaszewski:
"In this cycle we've finally managed to contribute the patch set
sorting out LED naming issues. Besides that there are many changes
scattered among various LED class drivers and triggers.
LED naming related improvements:
- add new 'function' and 'color' fwnode properties and deprecate
'label' property which has been frequently abused for conveying
vendor specific names that have been available in sysfs anyway
- introduce a set of standard LED_FUNCTION* definitions
- introduce a set of standard LED_COLOR_ID* definitions
- add a new {devm_}led_classdev_register_ext() API with the
capability of automatic LED name composition basing on the
properties available in the passed fwnode; the function is
backwards compatible in a sense that it uses 'label' data, if
present in the fwnode, for creating LED name
- add tools/leds/get_led_device_info.sh script for retrieving LED
vendor, product and bus names, if applicable; it also performs
basic validation of an LED name
- update following drivers and their DT bindings to use the new LED
registration API:
- leds-an30259a, leds-gpio, leds-as3645a, leds-aat1290, leds-cr0014114,
leds-lm3601x, leds-lm3692x, leds-lp8860, leds-lt3593, leds-sc27xx-blt
Other LED class improvements:
- replace {devm_}led_classdev_register() macros with inlines
- allow to call led_classdev_unregister() unconditionally
- switch to use fwnode instead of be stuck with OF one
LED triggers improvements:
- led-triggers:
- fix dereferencing of null pointer
- fix a memory leak bug
- ledtrig-gpio:
- GPIO 0 is valid
Drop superseeded apu2/3 support from leds-apu since for apu2+ a newer,
more complete driver exists, based on a generic driver for the AMD
SOCs gpio-controller, supporting LEDs as well other devices:
- drop profile field from priv data
- drop iosize field from priv data
- drop enum_apu_led_platform_types
- drop superseeded apu2/3 led support
- add pr_fmt prefix for better log output
- fix error message on probing failure
Other misc fixes and improvements to existing LED class drivers:
- leds-ns2, leds-max77650:
- add of_node_put() before return
- leds-pwm, leds-is31fl32xx:
- use struct_size() helper
- leds-lm3697, leds-lm36274, leds-lm3532:
- switch to use fwnode_property_count_uXX()
- leds-lm3532:
- fix brightness control for i2c mode
- change the define for the fs current register
- fixes for the driver for stability
- add full scale current configuration
- dt: Add property for full scale current.
- avoid potentially unpaired regulator calls
- move static keyword to the front of declarations
- fix optional led-max-microamp prop error handling
- leds-max77650:
- add of_node_put() before return
- add MODULE_ALIAS()
- Switch to fwnode property API
- leds-as3645a:
- fix misuse of strlcpy
- leds-netxbig:
- add of_node_put() in netxbig_leds_get_of_pdata()
- remove legacy board-file support
- leds-is31fl319x:
- simplify getting the adapter of a client
- leds-ti-lmu-common:
- fix coccinelle issue
- move static keyword to the front of declaration
- leds-syscon:
- use resource managed variant of device register
- leds-ktd2692:
- fix a typo in the name of a constant
- leds-lp5562:
- allow firmware files up to the maximum length
- leds-an30259a:
- fix typo
- leds-pca953x:
- include the right header"
* tag 'leds-for-5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/j.anaszewski/linux-leds: (72 commits)
leds: lm3532: Fix optional led-max-microamp prop error handling
led: triggers: Fix dereferencing of null pointer
leds: ti-lmu-common: Move static keyword to the front of declaration
leds: lm3532: Move static keyword to the front of declarations
leds: trigger: gpio: GPIO 0 is valid
leds: pwm: Use struct_size() helper
leds: is31fl32xx: Use struct_size() helper
leds: ti-lmu-common: Fix coccinelle issue in TI LMU
leds: lm3532: Avoid potentially unpaired regulator calls
leds: syscon: Use resource managed variant of device register
leds: Replace {devm_}led_classdev_register() macros with inlines
leds: Allow to call led_classdev_unregister() unconditionally
leds: lm3532: Add full scale current configuration
dt: lm3532: Add property for full scale current.
leds: lm3532: Fixes for the driver for stability
leds: lm3532: Change the define for the fs current register
leds: lm3532: Fix brightness control for i2c mode
leds: Switch to use fwnode instead of be stuck with OF one
leds: max77650: Switch to fwnode property API
led: triggers: Fix a memory leak bug
...
Add pericfg clocks for MT8183, it's used when support USB
remote wakeup
Cc: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Link: https://lkml.kernel.org/r/1566980533-28282-2-git-send-email-chunfeng.yun@mediatek.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The new BCM2711 supports an additional clock for the emmc2 block.
So we need an additional compatible.
Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
Add documentation for the mt8183 gce.
Add gce header file defined the gce hardware event,
subsys number and constant for mt8183.
Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
This is another huge branch with close to 450 changessets related to
devicetree files, roughly half of this for 32-bit and 64-bit respectively.
There are lots of cleanups and additional hardware support for platforms
we already support based on SoCs from Renesas, ST-Microelectronics,
Intel/Altera, Rockchips, Allwinner, Broadcom and other manufacturers.
A total of 6 new SoCs and 37 new boards gets added this time, one more
SoC will come in a follow-up branch. Most of the new boards are for
64-bit ARM SoCs, the others are typically for the 32-bit Cortex-A7.
Going more into details for SoC platforms with new hardware support:
The Snapdragon 855 (SM8150) is Qualcomm's current high-end phone platform,
usually paired with an external 5G modem. So far we only support the
Qualcomm SM8150 MTP reference platform, but no actual products.
For the slightly older Qualcomm platforms, support for several interesting
products is getting added: Three laptops based on Snapdragon 835/MSM8998
(Asus NovaGo, HP Envy X2 and Lenovo Miix 630), one laptop based on
Snapdragon 850/sdm850 (Lenovo Yoga C630) and several phones based on
the older Snapdragon 410/MSM8916 (Samsung A3 and A5, Longcheer L8150
aka Android One 2nd gen "seed" aka Wileyfox Swift).
Mediatek MT7629 is a new wireless network router chip, similar to
the older MT7623. It gets added together with the reference board
implementation.
Allwinner V3 is a repackaged version of the existing low-end V3s chip,
and is used in the tiny Lichee Pi Zero plus, also added here. There is
also a new TV set-top box based on Allwinner H6, the Tanix TX6, and the
eMMC variant of the Olimex A64-Olinuxino development board.
NXP i.MX8M Nano is a new member of the ever-expanding i.MX SoC family,
similar to the i.MX8M Mini. As usual, there is a large number of new
boards for i.MX SoCs: Einfochips i.MX8QXP AI_ML, SolidRun Hummingboard
Pulse baseboard and System-on-Module, Boundary Devices i.MX8MQ Nitrogen8M,
and TechNexion PICO-PI-IMX8M-DEV for the 64-bit i.MX8 line. For 32-bit,
we get the Kontron i.MX6UL N6310 SoM with two baseboards, the PHYTEC
phyBOARD-Segin SoM with three baseboards, and the Zodiac Inflight
Innovations i.MX7 RMU2 board.
In a different NXP product line, the Layerscape LS1046A "Freeway"
reference board gets added.
Amlogic SM1 (S905X3) and G12B (S922X, A311D) are updated chips from their
set-top-box line and smart speaker with newer CPU and GPU cores compared
to their predecessors. Both are now also supported by the Khadas VIM3
development board series, and the dts files for that get reorganized a
bit to better deal with all variants. Another board based on SM1 that
gets added is the SEI Robotics SEI610.
There are a handful of new x86 and Power9 server boards using Aspeed BMC
chips that are gaining support for running Linux on the BMC through the
OpenBMC project: Facebook Minipack/Wedge100/Wedge40, Lenovo Hr855xg2,
and Mihawk. Notably these are still new machines using SoCs based on
the ARM9 and ARM11 CPU cores, as support for the new Cortex-A7 based
AST2600 is still ramping up.
There are three new end-user products using 32-bit Rockchips SoCs:
Mecer Xtreme Mini S6 is an Android "mini PC" box based on the low-end
RK3229 chip, while the two AOpen products Chromebox Mini (Fievel) and
Chromebase Mini (Tiger) run ChromeOS and are meant for commercial settings
(digital signage, PoS, ...).
One more single-board computer based on the popular 64-bit RK3399 is
added: the Leez RK3399 P710.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABCAAGBQJdf6StAAoJEJpsee/mABjZDfEP/3h0GusRkoQ6PJ5FHsj4nIR6
NJK8RxmX4B4ctXxBc+Rbt8bHp1d/IdHL4Jcqe7xgR2OIVQPloJz1lFrLaF0wn4Mu
G1EP2DzcLym3K0lBwhByvXfU1s2lhaTYdT594J8kTEVgcPXe79LKqH42A1T+1IlC
7+xAh9sU++NLo64w+Iam3d3T72ugyeO7THWiie7Rb9wACS94i7cZwvasur35aHxf
Ut5nOQYPbTuVVvN1FfZAdrHJpK9r7pbJLVwHLMdHnUYup2XDmoC6iuDrKlsWxqjs
SBL0u+dO5pkdKQp17RZFQZwrx2Y97E9KLWaT9Cqb7nwJ+ftYf419TUioQvmyJRZd
DEsCz6GVCCOs2zFcGj+9iGRr5wA2O3I42dOZkkkTciztksFwSmomrSlwAgVBT2ms
In6K3g2DrN31aDGFW9dZnxBXHVHWXkqr/TN4UIO2h0jfR4bazAvPzBiDpJdkz1NY
KPpDrdTRA2k4UnSimot/7Pw8y2NtsTDVJeQS1KydSe44PiLLumO8hg+FfnhJoW5s
oaSjX89549JvUIrA7TbXPxpyGS8oo7a1XkQyzfWZs8l7JMWoR5oK/VdiuDBL7YDE
XFlcZmCmB+kUgtSgXjw9FflkoMn06usVZBo1rnWFApYmzZ3htnniNSgz/zjMJpXn
OtQTQnP2LzS+ioxqB2Se
=Bm5T
-----END PGP SIGNATURE-----
Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM DT updates from Arnd Bergmann:
"This is another huge branch with close to 450 changessets related to
devicetree files, roughly half of this for 32-bit and 64-bit
respectively. There are lots of cleanups and additional hardware
support for platforms we already support based on SoCs from Renesas,
ST-Microelectronics, Intel/Altera, Rockchips, Allwinner, Broadcom and
other manufacturers.
A total of 6 new SoCs and 37 new boards gets added this time, one more
SoC will come in a follow-up branch. Most of the new boards are for
64-bit ARM SoCs, the others are typically for the 32-bit Cortex-A7.
Going more into details for SoC platforms with new hardware support:
- The Snapdragon 855 (SM8150) is Qualcomm's current high-end phone
platform, usually paired with an external 5G modem. So far we only
support the Qualcomm SM8150 MTP reference platform, but no actual
products.
- For the slightly older Qualcomm platforms, support for several
interesting products is getting added: Three laptops based on
Snapdragon 835/MSM8998 (Asus NovaGo, HP Envy X2 and Lenovo Miix
630), one laptop based on Snapdragon 850/sdm850 (Lenovo Yoga C630)
and several phones based on the older Snapdragon 410/MSM8916
(Samsung A3 and A5, Longcheer L8150 aka Android One 2nd gen "seed"
aka Wileyfox Swift).
- Mediatek MT7629 is a new wireless network router chip, similar to
the older MT7623. It gets added together with the reference board
implementation.
- Allwinner V3 is a repackaged version of the existing low-end V3s
chip, and is used in the tiny Lichee Pi Zero plus, also added here.
There is also a new TV set-top box based on Allwinner H6, the Tanix
TX6, and the eMMC variant of the Olimex A64-Olinuxino development
board.
- NXP i.MX8M Nano is a new member of the ever-expanding i.MX SoC
family, similar to the i.MX8M Mini. As usual, there is a large
number of new boards for i.MX SoCs: Einfochips i.MX8QXP AI_ML,
SolidRun Hummingboard Pulse baseboard and System-on-Module,
Boundary Devices i.MX8MQ Nitrogen8M, and TechNexion
PICO-PI-IMX8M-DEV for the 64-bit i.MX8 line. For 32-bit, we get the
Kontron i.MX6UL N6310 SoM with two baseboards, the PHYTEC
phyBOARD-Segin SoM with three baseboards, and the Zodiac Inflight
Innovations i.MX7 RMU2 board.
- In a different NXP product line, the Layerscape LS1046A "Freeway"
reference board gets added.
- Amlogic SM1 (S905X3) and G12B (S922X, A311D) are updated chips from
their set-top-box line and smart speaker with newer CPU and GPU
cores compared to their predecessors. Both are now also supported
by the Khadas VIM3 development board series, and the dts files for
that get reorganized a bit to better deal with all variants.
Another board based on SM1 that gets added is the SEI Robotics
SEI610.
- There are a handful of new x86 and Power9 server boards using
Aspeed BMC chips that are gaining support for running Linux on the
BMC through the OpenBMC project: Facebook
Minipack/Wedge100/Wedge40, Lenovo Hr855xg2, and Mihawk. Notably
these are still new machines using SoCs based on the ARM9 and ARM11
CPU cores, as support for the new Cortex-A7 based AST2600 is still
ramping up.
- There are three new end-user products using 32-bit Rockchips SoCs:
Mecer Xtreme Mini S6 is an Android "mini PC" box based on the
low-end RK3229 chip, while the two AOpen products Chromebox Mini
(Fievel) and Chromebase Mini (Tiger) run ChromeOS and are meant for
commercial settings(digital signage, PoS, ...).
- One more single-board computer based on the popular 64-bit RK3399
is added: the Leez RK3399 P710"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (467 commits)
arm64: dts: qcom: Add Lenovo Yoga C630
ARM: dts: aspeed-g5: Fixe gpio-ranges upper limit
ARM; dts: aspeed: mihawk: File should not be executable
ARM: dts: aspeed: swift: Change power supplies to version 2
ARM: dts: aspeed: vesnin: Add secondary SPI flash chip
ARM: dts: aspeed: vesnin: Add wdt2 with alt-boot option
ARM: dts: aspeed-g4: Add all flash chips
ARM: dts: exynos: Enable GPU/Mali T604 on Arndale board
ARM: dts: exynos: Enable GPU/Mali T604 on Chromebook Snow
ARM: dts: exynos: Add GPU/Mali T604 node to Exynos5250
ARM: dts: exynos: Fix min/max buck4 for GPU on Arndale board
ARM: dts: exynos: Mark LDO10 as always-on on Peach Pit/Pi Chromebooks
ARM: dts: exynos: Remove not accurate secondary ADC compatible
arm64: dts: rockchip: limit clock rate of MMC controllers for RK3328
arm64: dts: meson-sm1-sei610: add stdout-path property back
arm64: dts: meson-sm1-sei610: enable DVFS
arm64: dts: khadas-vim3: add support for the SM1 based VIM3L
dt-bindings: arm: amlogic: add Amlogic SM1 based Khadas VIM3L bindings
arm64: dts: khadas-vim3: move common nodes into meson-khadas-vim3.dtsi
arm64: dts: meson: g12a: add reset to tdm formatters
...
The branch contains driver changes that are tightly
connected to SoC specific code. Aside from smaller
cleanups and bug fixes, here is a list of the notable
changes.
New device drivers:
- The Turris Mox router has a new "moxtet" bus driver
for its on-board pluggable extension bus. The
same platform also gains a firmware driver.
- The Samsung Exynos family gains a new Chipid driver
exporting using the soc device sysfs interface
- A similar socinfo driver for Qualcomm Snapdragon
chips.
- A firmware driver for the NXP i.MX DSP IPC protocol
using shared memory and a mailbox
Other changes:
- The i.MX reset controller driver now supports the
NXP i.MX8MM chip
- Amlogic SoC specific drivers gain support for
the S905X3 and A311D chips
- A rework of the TI Davinci framebuffer driver to
allow important cleanups in the platform code
- A couple of device drivers for removed ARM SoC
platforms are removed. Most of the removals were
picked up by other maintainers, this contains
whatever was left.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABCAAGBQJdf6SUAAoJEJpsee/mABjZAfwP/01bXBOlGVusNH2zuh8IUSHb
//5sTdWpwa2ugRekLOJUOjo2p9Fu70yH6xr4RUHI0rcRjZA0xR3bZPx45gI8LRHQ
tfb25LaKqfgZjWMCJ8due1Lh7B6ffOQukryMtM/LoiCtqsy7b6aThEKaLpM9/Owl
t53o4wKaVQJK5He9JQom9NOZidkl7tYLHmDQTOXhX2UEA/i45vtfjdsEBvoFPbTx
+bYvlqs+SWlpDJk29j+oBOeKadPF+TFboLDiUCxH44MC3OsH51zjtKVBRTtbNMkb
ek/ci5x9hCeHcYSEigNq2EMzEln09Yxyvjk8U/jLiJ1h1kz3p5MjqJbVMF1rYXpe
ALuAwinM8Zv2o5/UOCkiQTWq79PtpOKHZKpNBXkaJ8kyqBLMSy8Fs3hCvXrDnjnQ
TC8jX7UBqHRV2rbQIYehAQAxTvcRgTbqusQGLkUJInlux6go57LoMYHPABpHftJV
kRdVeT0KzdCz1pvQwyekIog5hPLNTBi4jw6eQcOgeENvAea1MJa8lMMfKcVbIdS0
ZVvxLl+K6noEKAv5lSeHAzjXq+cQFr3zDCsWy351mJETDHmE8zjsaHN1SgbRYLEk
ZqzNwUYaPYBis38g85qaY/TSsJrWJ+jP8u7s9HTw3Oywg8SRy5vtW177s00/9VOd
PYZ2UpqUeX8cdvggqUUU
=lxFi
-----END PGP SIGNATURE-----
Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC driver updates from Arnd Bergmann:
"This contains driver changes that are tightly connected to SoC
specific code. Aside from smaller cleanups and bug fixes, here is a
list of the notable changes.
New device drivers:
- The Turris Mox router has a new "moxtet" bus driver for its
on-board pluggable extension bus. The same platform also gains a
firmware driver.
- The Samsung Exynos family gains a new Chipid driver exporting using
the soc device sysfs interface
- A similar socinfo driver for Qualcomm Snapdragon chips.
- A firmware driver for the NXP i.MX DSP IPC protocol using shared
memory and a mailbox
Other changes:
- The i.MX reset controller driver now supports the NXP i.MX8MM chip
- Amlogic SoC specific drivers gain support for the S905X3 and A311D
chips
- A rework of the TI Davinci framebuffer driver to allow important
cleanups in the platform code
- A couple of device drivers for removed ARM SoC platforms are
removed. Most of the removals were picked up by other maintainers,
this contains whatever was left"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (123 commits)
bus: uniphier-system-bus: use devm_platform_ioremap_resource()
soc: ti: ti_sci_pm_domains: Add support for exclusive and shared access
dt-bindings: ti_sci_pm_domains: Add support for exclusive and shared access
firmware: ti_sci: Allow for device shared and exclusive requests
bus: imx-weim: remove incorrect __init annotations
fbdev: remove w90x900/nuc900 platform drivers
spi: remove w90x900 driver
net: remove w90p910-ether driver
net: remove ks8695 driver
firmware: turris-mox-rwtm: Add sysfs documentation
firmware: Add Turris Mox rWTM firmware driver
dt-bindings: firmware: Document cznic,turris-mox-rwtm binding
bus: moxtet: fix unsigned comparison to less than zero
bus: moxtet: remove set but not used variable 'dummy'
ARM: scoop: Use the right include
dt-bindings: power: add Amlogic Everything-Else power domains bindings
soc: amlogic: Add support for Everything-Else power domains controller
fbdev: da8xx: use resource management for dma
fbdev: da8xx-fb: drop a redundant if
fbdev: da8xx-fb: use devm_platform_ioremap_resource()
...
Including:
- Batched unmap support for the IOMMU-API
- Support for unlocked command queueing in the ARM-SMMU driver
- Rework the ATS support in the ARM-SMMU driver
- More refactoring in the ARM-SMMU driver to support hardware
implemention specific quirks and errata
- Bounce buffering DMA-API implementatation in the Intel VT-d driver
for untrusted devices (like Thunderbolt devices)
- Fixes for runtime PM support in the OMAP iommu driver
- MT8183 IOMMU support in the Mediatek IOMMU driver
- Rework of the way the IOMMU core sets the default domain type for
groups. Changing the default domain type on x86 does not require two
kernel parameters anymore.
- More smaller fixes and cleanups
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEr9jSbILcajRFYWYyK/BELZcBGuMFAl1/pdoACgkQK/BELZcB
GuMvCw/+K1GPyyZbPWAuXcnclraSZTHXS1lV0yilBXXyT2omFRQpRJYZGN/8NTbE
SqD2FtzTKGuGSy2jA0drd3RcMKK/zZsFYnJShiM3FHLXatZdaFrnkK7vRHuzKlHf
dvOlH7gHKtjIPPXodUEb0xd/oRAEIVsKjJyq1fBMARPPAluhU7mIFUI/xbGvX17g
LM00hIxEhVNsSPemU2kTVISNBPVneecNVLlKXySjp0YPW/+sf8R7tTvwlSXX6h3I
JM6wOU479O8mBvIcpAjfZlanHCHtqLk0ybaPx666DjdgYx6cUBHbDCF0P57XnGJA
HNeVGtBwGQb8VWgbPLJKrStSOzYudDG8ndctqfKYN7uiPDjYM2/sqXcwQSVXR9vX
AjT2s0GFEWT/AJhgBSeg9PJilEX1hPtomGKcQhKfR0wRGycixeZJFbwToQqzJrZN
7XoORbZPH1S5W6sjXsXH3eVPW3EGnKipulJSPGDqFLa2aIUG+PXuu/A+iJS6sADh
mqzVfcEs3/NYsro40eA/iQc0t99ftJXgpX18KxYprjyL6VWcwC/xeHcT/Zw9abxz
r7dYDGTR0z6RIew0GOaeZVdZJh/J6yraKCNDS0ARZgol6JPaU7HGHhh6Ohdmmu8L
Gtsgdxp4NeLEgp4mQiRvvpQ5pPJ/YR+oCOx3v+PPnKRLhMTxymQ=
=UF08
-----END PGP SIGNATURE-----
Merge tag 'iommu-updates-v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull iommu updates from Joerg Roedel:
- batched unmap support for the IOMMU-API
- support for unlocked command queueing in the ARM-SMMU driver
- rework the ATS support in the ARM-SMMU driver
- more refactoring in the ARM-SMMU driver to support hardware
implemention specific quirks and errata
- bounce buffering DMA-API implementatation in the Intel VT-d driver
for untrusted devices (like Thunderbolt devices)
- fixes for runtime PM support in the OMAP iommu driver
- MT8183 IOMMU support in the Mediatek IOMMU driver
- rework of the way the IOMMU core sets the default domain type for
groups. Changing the default domain type on x86 does not require two
kernel parameters anymore.
- more smaller fixes and cleanups
* tag 'iommu-updates-v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (113 commits)
iommu/vt-d: Declare Broadwell igfx dmar support snafu
iommu/vt-d: Add Scalable Mode fault information
iommu/vt-d: Use bounce buffer for untrusted devices
iommu/vt-d: Add trace events for device dma map/unmap
iommu/vt-d: Don't switch off swiotlb if bounce page is used
iommu/vt-d: Check whether device requires bounce buffer
swiotlb: Split size parameter to map/unmap APIs
iommu/omap: Mark pm functions __maybe_unused
iommu/ipmmu-vmsa: Disable cache snoop transactions on R-Car Gen3
iommu/ipmmu-vmsa: Move IMTTBCR_SL0_TWOBIT_* to restore sort order
iommu: Don't use sme_active() in generic code
iommu/arm-smmu-v3: Fix build error without CONFIG_PCI_ATS
iommu/qcom: Use struct_size() helper
iommu: Remove wrong default domain comments
iommu/dma: Fix for dereferencing before null checking
iommu/mediatek: Clean up struct mtk_smi_iommu
memory: mtk-smi: Get rid of need_larbid
iommu/mediatek: Fix VLD_PA_RNG register backup when suspend
memory: mtk-smi: Add bus_sel for mt8183
memory: mtk-smi: Invoke pm runtime_callback to enable clocks
...
Introduce support for AUX2 channel found in ADC hardware present on
Ingenic JZ4770 SoC.
Signed-off-by: Artur Rojek <contact@artur-rojek.eu>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
The ast2600 is a new BMC SoC from ASPEED. It contains many more clocks
than the previous iterations, so support is broken out into it's own
driver.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://lkml.kernel.org/r/20190825141848.17346-3-joel@jms.id.au
[sboyd@kernel.org: Mark arrays const]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add the dt-bindings header for the rk3308, that gets shared between
the clock controller and the clock references in the dts.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
TISCI protocol supports for enabling the device either with exclusive
permissions for the requesting host or with sharing across the hosts.
There are certain devices which are exclusive to Linux context and
there are certain devices that are shared across different host contexts.
So add support for getting this information from DT by increasing
the power-domain cells to 2.
Acked-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add support for Turris Mox board (Armada 3720 SoC based)
-----BEGIN PGP SIGNATURE-----
iF0EABECAB0WIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCXW5eNQAKCRALBhiOFHI7
1aqnAJsGU/B3GFbhiuwI4+l3In7TMVVpIgCbB1T/eo1RJhvh9kH9zMj641Rmsk0=
=B8dQ
-----END PGP SIGNATURE-----
Merge tag 'mvebu-dt64-5.4-2' of git://git.infradead.org/linux-mvebu into arm/late
mvebu dt64 for 5.4 (part 2)
Add support for Turris Mox board (Armada 3720 SoC based)
* tag 'mvebu-dt64-5.4-2' of git://git.infradead.org/linux-mvebu: (53 commits)
arm64: dts: marvell: add DTS for Turris Mox
dt-bindings: marvell: document Turris Mox compatible
arm64: dts: marvell: armada-37xx: add SPI CS1 pinctrl
arm64: dts: marvell: Add cpu clock node on Armada 7K/8K
arm64: dts: marvell: Convert 7k/8k usb-phy properties to phy-supply
arm64: dts: marvell: Add 7k/8k PHYs in PCIe nodes
arm64: dts: marvell: Add 7k/8k PHYs in USB3 nodes
arm64: dts: marvell: Add 7k/8k per-port PHYs in SATA nodes
arm64: dts: marvell: Add CP110 COMPHY clocks
arm64: dts: marvell: armada-37xx: add mailbox node
dt-bindings: gpio: Document GPIOs via Moxtet bus
drivers: gpio: Add support for GPIOs over Moxtet bus
bus: moxtet: Add sysfs and debugfs documentation
dt-bindings: bus: Document moxtet bus binding
bus: Add support for Moxtet bus
reset: Add support for resets provided by SCMI
firmware: arm_scmi: Add RESET protocol in SCMI v2.0
dt-bindings: arm: Extend SCMI to support new reset protocol
firmware: arm_scmi: Make use SCMI v2.0 fastchannel for performance protocol
firmware: arm_scmi: Add discovery of SCMI v2.0 performance fastchannels
...
Link: https://lore.kernel.org/r/87h85two0r.fsf@FE-laptop
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Typo fixes for gic-its unit addresses for both am654 and j721e
- HW spinlock nodes added for both am654 and j721e
- GPIO support for j721e
- power-domain cells update for both am654 / j721e for exclusive only
access
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEEtQ6szHmfiBT7fujkyvq9MXlQGhEFAl1pFzsQHHQta3Jpc3Rv
QHRpLmNvbQAKCRDK+r0xeVAaERL3D/44Xth2Ti/UIZIzZrM7t6R2t84UYoYF2AFu
129ehlVk7k6pqiv1FRHG4SQpRV09DRmUX1JIoukoNtfrQMmF1C1/ryLaHGf/4vV6
sj/tbIPs1LxrTomCOuoLG2quhu6JBHDWE8ZjRJnOFo7rHOTo1w0orOnnnx6S0ES8
5WyFAecfI34noroFcHZ0mKcZmG2/AkzY6pDQGSMOnugbCjq2EteFwoKcVssKdcsA
tlT5KkqAwehS4CdZxObikE3y5rYALinFcZYATzX1eHkd4Jqo0PchunXSLj0A5y7i
7tVSslCaCZKKFg7BYpXbKA/vAhMXfpKjpL3hosHb7qPQ84GsCl1WIfH4HKtqkOXA
81jbOZu7Dgqx7J11Dtj7h46G84pxaO/78izEoineheIfKheYePyG1rRcJAHkxebF
hGZE/KbXyx5Uj8sjVtrCg4/xdrnD17JT/GGelw83vPIxf49rWvq1Rt+njIDCcIyq
GpWwjjJWnKbLx75Dr480YEU6Klp4YuyBOOL9X+/8dQLTOhtlmR2jq4TzkqtDsqWW
DFp2HQSCv7jsFag50qYrUCwcvI9Ru8MMNIX9laXVKPINqVB0aMa00EdvpBDY2eMh
mOXeurMY7jQ907oymSw7rx6DhjlQx9qcNqHgpyTJ7k9xSVW5NqQoTBnmm06pviC6
55xzDSjBAw==
=OoxU
-----END PGP SIGNATURE-----
Merge tag 'ti-k3-soc-for-v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux into arm/late
Texas Instruments K3 SoC family changes for 5.4
- Typo fixes for gic-its unit addresses for both am654 and j721e
- HW spinlock nodes added for both am654 and j721e
- GPIO support for j721e
- power-domain cells update for both am654 / j721e for exclusive only
access
* tag 'ti-k3-soc-for-v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux:
arm64: dts: ti: k3-j721e-main: Fix gic-its node unit-address
arm64: dts: ti: k3-am65-main: Fix gic-its node unit-address
arm64: dts: ti: k3-j721e-main: Add hwspinlock node
arm64: dts: ti: k3-am65-main: Add hwspinlock node
arm64: dts: k3-j721e: Add gpio-keys on common processor board
dt-bindings: pinctrl: k3: Introduce pinmux definitions for J721E
arm64: dts: ti: k3-j721e-common-proc-board: Disable unused gpio modules
arm64: dts: ti: k3-j721e: Add gpio nodes in wakeup domain
arm64: dts: ti: k3-j721e: Add gpio nodes in main domain
arm64: dts: ti: k3-j721e: Update the power domain cells
arm64: dts: ti: k3-am654: Update the power domain cells
soc: ti: ti_sci_pm_domains: Add support for exclusive and shared access
dt-bindings: ti_sci_pm_domains: Add support for exclusive and shared access
firmware: ti_sci: Allow for device shared and exclusive requests
Link: https://lore.kernel.org/r/b838d666-ab3b-7d41-67d4-09d606c732da@ti.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
*) Add a new PHY driver for Lantiq VRX200/ARX300 PCIe PHY
*) Add missing of_node_put() to a bunch of drivers using
for_each_available_child_of_node()
*) Add RXAUI/PCIe/SATA/USB3 support in Marvell's Armada
CP110 COMPHY
*) Other misc fixes and cleanup
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
-----BEGIN PGP SIGNATURE-----
iQJCBAABCgAsFiEEUXMr/TfP2p4suIY5Dlx4XIBNgtkFAl1lQAIOHGtpc2hvbkB0
aS5jb20ACgkQDlx4XIBNgtmG9w//Te50DQemUjryStFT9dcKx0GE0+fC4tStkdsD
nkn1+PaYrHHrB9DU5fjYZNrI1QPGxMXX3bP1B3+rjCp8yBOEoM/UcdlZPGch93NU
pa4i+it63bT4WJ/b9OGlWqJHZCwsg+uq/XkpLGW/RJiHfJMv+bNdL32q+NK3aLUB
RC3/jhdHbZmXLWgcb4c12PuO4U29mZtHviK9EKTYUbc6ilfAXfFlR/+HwOX8a8Kf
wlg++9/tqE8LBD3LNLUiOYOGfl2HFEhmuS4J+b71Yujx3Jh+ME6idqJepCMiQEnv
nbzMxw8TrYapqB/+4a4Asb9gxY95hTtlsAlNy0qxGS+7LBrj1epFTqmdFNfhv2n7
SMXpQOc3++yN1ultXmJmt4G1pyP2hi1M1d2l++rJ4c3bNZ229gkXpvTgdw0zBMum
JA9fK1+sHrJDjcvvOQ+5WcrQ7e9XyB/98mH2jBIEsybWTz7AQrmlqnKy2CEenUIj
hGQRIM+Z22UBIW9OsJGj2c3xvI0Rz7EnvyJmEjCDBoVjrG+e/omOi7YXvF0cL72S
jdMNTs3rErRnFldq9safwNLrIHiTeel70Lytsl44go9n6f5EO/xT+voOX6Wl3LGB
hjnBb+3P1X/cJb6+rHclx+Fo7ZKlv69oxUv1NBDLqbn3l66QdKfRTnQVAdBSxJ0H
gNkt8ew=
=FzqB
-----END PGP SIGNATURE-----
Merge tag 'phy-for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into char-misc-next
Kishon writes:
phy: for 5.4
*) Add a new PHY driver for Lantiq VRX200/ARX300 PCIe PHY
*) Add missing of_node_put() to a bunch of drivers using
for_each_available_child_of_node()
*) Add RXAUI/PCIe/SATA/USB3 support in Marvell's Armada
CP110 COMPHY
*) Other misc fixes and cleanup
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* tag 'phy-for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy: (30 commits)
phy: marvell: phy-mvebu-cp110-comphy: rename instances of DLT
phy: marvell: phy-mvebu-cp110-comphy: implement RXAUI support
dt-bindings: pci: add PHY properties to Armada 7K/8K controller bindings
dt-bindings: phy: Add Marvell COMPHY clocks
phy: mvebu-cp110-comphy: Update comment about powering off all lanes at boot
phy: mvebu-cp110-comphy: Add PCIe support
phy: mvebu-cp110-comphy: Cosmetic change in a helper
phy: mvebu-cp110-comphy: Add SATA support
phy: mvebu-cp110-comphy: Add USB3 host/device support
phy: mvebu-cp110-comphy: Allow non-Ethernet modes to be configured
phy: mvebu-cp110-comphy: Rename the macro handling only Ethernet modes
phy: mvebu-cp110-comphy: Add RXAUI support
phy: mvebu-cp110-comphy: List already supported Ethernet modes
phy: mvebu-cp110-comphy: Add SMC call support
phy: mvebu-cp110-comphy: Explicitly initialize the lane submode
phy: mvebu-cp110-comphy: Add clocks support
phy-rockchip-inno-hdmi: Fix RK3328_TERM_RESISTOR_CALIB_SPEED_7_0's third value
phy: qcom-qmp: Correct ready status, again
phy: qualcomm: phy-qcom-qmp: Add of_node_put() before return
phy: renesas: rcar-gen3-usb2: Disable clearing VBUS in over-current
...
- A series from Anson Huang to add i.MX8MN SoC and DDR4 EVK board
device tree support.
- Add DSP device tree support for i.MX8QXP SoC.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJdYom7AAoJEFBXWFqHsHzOVG8H/RTfCTmRCBaClVZ031GWl/Q2
2NP+AY1l8UE0NKsvEuoMf/VY1atvFNgDvbm4gV1PW5KOBbgZmB3M32lHvXfqbLOu
vACCc8b7JY/8scWUgQBNbE5xAiZjPkLPuIYNJTLmrgVrYkYhtkB/4pwAk9YjVlYt
eHF3SWizKmam8vV3yp6KUNKvEYPBiMBfjSHDUvgT0GHUB4SHpPm/ERruTdKxP0Zm
c730yvV320XiKvxuErdvNfsw6FWs8Bhp8xCIhvF4Wbm0w4c5ucuqHKSV1v63lbbj
GVfdi0cH/eKlugNhfhIH7RsYL5TYjCDwzEyBSnqGCaBW+gnTpRnFkEricgvB+yY=
=3nO3
-----END PGP SIGNATURE-----
Merge tag 'imx-dt-clkdep-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt
i.MX device tree update with new clocks:
- A series from Anson Huang to add i.MX8MN SoC and DDR4 EVK board
device tree support.
- Add DSP device tree support for i.MX8QXP SoC.
* tag 'imx-dt-clkdep-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: imx8qxp: Add DSP DT node
arm64: dts: imx8mn: Add cpu-freq support
arm64: dts: imx8mn-ddr4-evk: Add rohm,bd71847 PMIC support
arm64: dts: imx8mn-ddr4-evk: Add i2c1 support
arm64: dts: freescale: Add i.MX8MN DDR4 EVK board support
arm64: dts: imx8mn: Add gpio-ranges property
arm64: dts: freescale: Add i.MX8MN dtsi support
clk: imx8: Add DSP related clocks
clk: imx: Add support for i.MX8MN clock driver
clk: imx: Add API for clk unregister when driver probe fail
clk: imx8mm: Make 1416X/1443X PLL macro definitions common for usage
dt-bindings: imx: Add clock binding doc for i.MX8MN
Link: https://lore.kernel.org/r/20190825153237.28829-4-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This patch adds decriptions for mt8183 IOMMU and SMI.
mt8183 has only one M4U like mt8173 and is also MTK IOMMU gen2 which
uses ARM Short-Descriptor translation table format.
The mt8183 M4U-SMI HW diagram is as below:
EMI
|
M4U
|
----------
| |
gals0-rx gals1-rx
| |
| |
gals0-tx gals1-tx
| |
------------
SMI Common
------------
|
+-----+-----+--------+-----+-----+-------+-------+
| | | | | | | |
| | gals-rx gals-rx | gals-rx gals-rx gals-rx
| | | | | | | |
| | | | | | | |
| | gals-tx gals-tx | gals-tx gals-tx gals-tx
| | | | | | | |
larb0 larb1 IPU0 IPU1 larb4 larb5 larb6 CCU
disp vdec img cam venc img cam
All the connections are HW fixed, SW can NOT adjust it.
Compared with mt8173, we add a GALS(Global Async Local Sync) module
between SMI-common and M4U, and additional GALS between larb2/3/5/6
and SMI-common. GALS can help synchronize for the modules in different
clock frequency, it can be seen as a "asynchronous fifo".
GALS can only help transfer the command/data while it doesn't have
the configuring register, thus it has the special "smi" clock and it
doesn't have the "apb" clock. From the diagram above, we add "gals0"
and "gals1" clocks for smi-common and add a "gals" clock for smi-larb.
>From the diagram above, IPU0/IPU1(Image Processor Unit) and CCU(Camera
Control Unit) is connected with smi-common directly, we can take them
as "larb2", "larb3" and "larb7", and their register spaces are
different with the normal larb.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Add the bindings for the Amlogic Everything-Else power domains,
controlling the Everything-Else peripherals power domains.
The bindings targets the Amlogic G12A and SM1 compatible SoCs,
support for earlier SoCs will be added later.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add pinctrl macros for J721E SoC. These macro definitions are
similar to that of AM6, but adding new definitions to avoid
any naming confusions in the soc dts files.
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
TISCI protocol supports for enabling the device either with exclusive
permissions for the requesting host or with sharing across the hosts.
There are certain devices which are exclusive to Linux context and
there are certain devices that are shared across different host contexts.
So add support for getting this information from DT by increasing
the power-domain cells to 2.
Acked-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
Looks like we have sgx clock missing currently so let's add it.
Cc: Adam Ford <aford173@gmail.com>
Cc: Filip Matijević <filip.matijevic.pz@gmail.com>
Cc: "H. Nikolaus Schaller" <hns@goldelico.com>
Cc: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com>
Cc: moaz korena <moaz@korena.xyz>
Cc: Merlijn Wajer <merlijn@wizzup.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com>
Cc: Philipp Rossak <embed3d@gmail.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: linux-clk@vger.kernel.org
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Update the documentation to support clock driver for the Amlogic SM1 SoC
and expose the GP1, DSU and the CPU 1, 2 & 3 clocks.
SM1 clock tree is very close, the main differences are :
- each CPU core can achieve a different frequency, albeit a common PLL
- a similar tree as the clock tree has been added for the DynamIQ Shared
Unit
- has a new GP1 PLL used for the DynamIQ Shared Unit
- SM1 has additional clocks like for CSI, NanoQ an other components
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Add the bindings for the PCIe PHY on Lantiq VRX200 and ARX300 SoCs.
The IP block contains settings for the PHY and a PLL.
The PLL mode is configurable through a dedicated #phy-cell in .dts.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This adds basic support for MT7629 reference board.
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This is required to bring Mali450 gpu out of reset.
Cc: David Airlie <airlied@linux.ie>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: dri-devel@lists.freedesktop.org
Cc: devicetree@vger.kernel.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Add the documentation and bindings for the resets provided by the g12a
audio clock controller
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
This is enabled by default but if it's not explicitly defined and marked
as critical then its parent might get turned off.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add documentation for act8865 regulator modes and suspend states.
Add active-semi,8865-regulator.h file for device tree binding constants
for act8865 regulators.
Signed-off-by: Raag Jadav <raagjadav@gmail.com>
Link: https://lore.kernel.org/r/1565721176-8955-3-git-send-email-raagjadav@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
On the Turris Mox router different modules can be connected to the main
CPU board: currently a module with a SFP cage, a module with MiniPCIe
connector, a PCIe pass-through MiniPCIe connector module, a 4-port
switch module, an 8-port switch module, and a 4-port USB3 module.
For example:
[CPU]-[PCIe-pass-through]-[PCIe]-[8-port switch]-[8-port switch]-[SFP]
Each of this modules has an input and output shift register, and these
are connected via SPI to the CPU board.
Via SPI we are able to discover which modules are connected, in which
order, and we can also read some information about the modules (eg.
their interrupt status), and configure them.
From each module 8 bits can be read (of which low 4 bits identify the
module) and 8 bits can be written.
For example from the module with a SFP cage we can read the LOS,
TX-FAULT and MOD-DEF0 signals, while we can write TX-DISABLE and
RATE-SELECT signals.
This driver creates a new bus type, called "moxtet". For each Mox module
it finds via SPI, it creates a new device on the moxtet bus so that
drivers can be written for them.
It also implements a virtual interrupt controller for the modules which
send their interrupt status over the SPI shift register. These modules
do this in addition to sending their interrupt status via the shared
interrupt line. When the shared interrupt is triggered, we read from the
shift register and handle IRQs for all devices which are in interrupt.
The topology of how Mox modules are connected can then be read by
listing /sys/bus/moxtet/devices.
Link: https://lore.kernel.org/r/20190812161118.21476-2-marek.behun@nic.cz
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The Qualcomm QCS404 platform has several buses that could be controlled
and tuned according to the bandwidth demand.
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Add the appropriate SPDX license identifier to the common
TI sysc bindings header file.
Signed-off-by: Suman Anna <s-anna@ti.com>
Acked-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Allwinner V3 has the same main die with V3s, but with more pins wired.
There's a I2S bus on V3 that is not available on V3s.
Add the V3-only peripheral's clocks and reset to the V3s CCU driver,
bound to a new V3 compatible string. The driver name is not changed
because it's part of the device tree binding (the header file name).
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Expose the CPUB clock id to add DVFS to the second CPU cluster of
the Amlogic G12B SoC.
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Add the missing TCU clock to the list of clocks supplied by the CGU for
the JZ4740 SoC.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: Mathieu Malaterre <malat@debian.org>
Tested-by: Artur Rojek <contact@artur-rojek.eu>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-doc@vger.kernel.org
Cc: linux-mips@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: od@zcrc.me
This header provides clock numbers for the ingenic,tcu
DT binding.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: Mathieu Malaterre <malat@debian.org>
Tested-by: Artur Rojek <contact@artur-rojek.eu>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-doc@vger.kernel.org
Cc: linux-mips@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: od@zcrc.me
Set reset signal by a register and
clear reset signal by another register for 8183.
Signed-off-by: yong.liang <yong.liang@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add support for the WCSS QDSP gcc clock control used on qcs404
based devices. This would allow wcss remoteproc driver to control
the required gcc clocks to bring the subsystem out of reset.
Signed-off-by: Govind Singh <govinds@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Document the global clock controller found on SM8150.
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
[vkoul: port to upstream and add external clocks
split binding to this patch]]
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lkml.kernel.org/r/20190722074348.29582-5-vkoul@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Some of the mipi dsi resets were called
IMX8MQ_RESET_MIPI_DIS__
instead of
IMX8MQ_RESET_MIPI_DSI__
Since they're DSI related this looks like a typo. This fixes the
only in tree user as well to not break bisecting.
Signed-off-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
i.MX8MM can reuse i.MX8MQ's reset driver, update the compatible
property and related info to support i.MX8MM.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Add initial set of common LED function definitions.
Signed-off-by: Jacek Anaszewski <jacek.anaszewski@gmail.com>
Cc: Baolin Wang <baolin.wang@linaro.org>
Cc: Daniel Mack <daniel@zonque.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Oleh Kravchenko <oleg@kaa.org.ua>
Cc: Sakari Ailus <sakari.ailus@linux.intel.com>
Cc: Simon Shields <simon@lineageos.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Pavel Machek <pavel@ucw.cz>
Reviewed-by: Dan Murphy <dmurphy@ti.com>
Add common LED color identifiers.
Signed-off-by: Jacek Anaszewski <jacek.anaszewski@gmail.com>
Cc: Baolin Wang <baolin.wang@linaro.org>
Cc: Daniel Mack <daniel@zonque.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Oleh Kravchenko <oleg@kaa.org.ua>
Cc: Sakari Ailus <sakari.ailus@linux.intel.com>
Cc: Simon Shields <simon@lineageos.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Pavel Machek <pavel@ucw.cz>
Reviewed-by: Dan Murphy <dmurphy@ti.com>
We continue to see a lot of new material. I've highlighted some of it
below, but there's been more beyond that as well.
One of the sweeping changes is that many boards have seen their ARM Mali
GPU devices added to device trees, since the DRM drivers have now been
merged.
So, with the caveat that I have surely missed several great
contributions, here's a collection of the material this time around:
New SoCs:
- Mediatek mt8183 (4x Cortex-A73 + 4x Cortex-A53)
- TI J721E (2x Cortex-A72 + 3x Cortex-R5F + 3 DSPs + MMA)
- Amlogic G12B (4x Cortex-A73 + 2x Cortex-A53)
New Boards / platforms:
- Aspeed BMC support for a number of new server platforms
- Kontron SMARC SoM (several i.MX6 versions)
- Novtech's Meerkat96 (i.MX7)
- ST Micro Avenger96 board
- Hardkernel ODROID-N2 (Amlogic G12B)
- Purism Librem5 devkit (i.MX8MQ)
- Google Cheza (Qualcomm SDM845)
- Qualcomm Dragonboard 845c (Qualcomm SDM845)
- Hugsun X99 TV Box (Rockchip RK3399)
- Khadas Edge/Edge-V/Captain (Rockchip RK3399)
Updated / expanded boards and platforms:
- Renesas r7s9210 has a lot of new peripherals added
- Polish and fixes for Rockchip-based Chromebooks
- Amlogic G12A has a lot of peripherals added
- Nvidia Jetson Nano sees various fixes and improvements, and is now at
feature parity with TX1
-----BEGIN PGP SIGNATURE-----
iQJDBAABCAAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAl0yUswPHG9sb2ZAbGl4
b20ubmV0AAoJEIwa5zzehBx3BrEP/2Hrqr9MHWSZ65iLmRkrMIMQ0nxxngN5//Jt
AlrmyBixwnV3l1eP5lpZT9VlXQL8lo7fkx+03fHPUaKxBihl6DN8LGsSnsT7Wnzu
aGA8SiJmdZhk8f1C30gGNssBBvOdJeTmc0vQzeKXJA6g4ra3+bmwn+T6OLEEGZlO
g0pl7BXST9lNLFlSBEG6DcjNL7m1mqCWpaRmWe70zjbFT86KKb/5YISY61fC7Qkf
AHccunoSXFBM6ttoIubxCInTkhfhKalJyZ2cUPZ6MRxhoE0+ABVOk2lw1oMmF3er
OOz8Qs9AcZcsC6k+WAxJgMjT8snTc8wRh273Df8drGfTzSgGkuXj0Uimmgmaqsts
3xPKu+6+UY+HxDt52NOQ4p/eo8yPMgVutfG7ciGynHZSgsklscLXMvUL7EGH67hR
AfJQFWJ3K+Jk/KeyyGgi1pa2C4BoJ1VmPw1P9oLHRMuuCLrY1B2XzG7nySX81uNG
2uTbLL236o2oUX3E/yaLN1k2tkreddG1G48HVw/srcIImAxD5Dl1sysRzMQRUWBw
tN5ZecSuz/JMQj5HaieZ8zL/v9dXzq6Gielee8SAJaO38nbnmxv3DfTHLLEoy3nv
mS/1OtySzbzI9obMZIsw+bpxDokvb525k89gthxBfWybm6KCRGJO119zc5nZ9r8G
PX5wvaPi
=sHZs
-----END PGP SIGNATURE-----
Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM Devicetree updates from Olof Johansson:
"We continue to see a lot of new material. I've highlighted some of it
below, but there's been more beyond that as well.
One of the sweeping changes is that many boards have seen their ARM
Mali GPU devices added to device trees, since the DRM drivers have now
been merged.
So, with the caveat that I have surely missed several great
contributions, here's a collection of the material this time around:
New SoCs:
- Mediatek mt8183 (4x Cortex-A73 + 4x Cortex-A53)
- TI J721E (2x Cortex-A72 + 3x Cortex-R5F + 3 DSPs + MMA)
- Amlogic G12B (4x Cortex-A73 + 2x Cortex-A53)
New Boards / platforms:
- Aspeed BMC support for a number of new server platforms
- Kontron SMARC SoM (several i.MX6 versions)
- Novtech's Meerkat96 (i.MX7)
- ST Micro Avenger96 board
- Hardkernel ODROID-N2 (Amlogic G12B)
- Purism Librem5 devkit (i.MX8MQ)
- Google Cheza (Qualcomm SDM845)
- Qualcomm Dragonboard 845c (Qualcomm SDM845)
- Hugsun X99 TV Box (Rockchip RK3399)
- Khadas Edge/Edge-V/Captain (Rockchip RK3399)
Updated / expanded boards and platforms:
- Renesas r7s9210 has a lot of new peripherals added
- Fixes and polish for Rockchip-based Chromebooks
- Amlogic G12A has a lot of peripherals added
- Nvidia Jetson Nano sees various fixes and improvements, and is now
at feature parity with TX1"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (586 commits)
ARM: dts: gemini: Set DIR-685 SPI CS as active low
ARM: dts: exynos: Adjust buck[78] regulators to supported values on Arndale Octa
ARM: dts: exynos: Adjust buck[78] regulators to supported values on Odroid XU3 family
ARM: dts: exynos: Move Mali400 GPU node to "/soc"
ARM: dts: exynos: Fix imprecise abort on Mali GPU probe on Exynos4210
arm64: dts: qcom: qcs404: Add missing space for cooling-cells property
arm64: dts: rockchip: Fix USB3 Type-C on rk3399-sapphire
arm64: dts: rockchip: Update DWC3 modules on RK3399 SoCs
arm64: dts: rockchip: enable rk3328 watchdog clock
ARM: dts: rockchip: add display nodes for rk322x
ARM: dts: rockchip: fix vop iommu-cells on rk322x
arm64: dts: rockchip: Add support for Hugsun X99 TV Box
arm64: dts: rockchip: Define values for the IPA governor for rock960
arm64: dts: rockchip: Fix multiple thermal zones conflict in rk3399.dtsi
arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs
arm64: dts: rockchip: improve rk3328-roc-cc rgmii performance.
Revert "ARM: dts: rockchip: set PWM delay backlight settings for Minnie"
ARM: dts: rockchip: Configure BT_DEV_WAKE in on rk3288-veyron
arm64: dts: qcom: sdm845-cheza: add initial cheza dt
ARM: dts: msm8974-FP2: Add vibration motor
...
Various driver updates for platforms and a couple of the small driver
subsystems we merge through our tree:
- A driver for SCU (system control) on NXP i.MX8QXP
- Qualcomm Always-on Subsystem messaging driver (AOSS QMP)
- Qualcomm PM support for MSM8998
- Support for a newer version of DRAM PHY driver for Broadcom (DPFE)
- Reset controller support for Bitmain BM1880
- TI SCI (System Control Interface) support for CPU control on AM654
processors
- More TI sysc refactoring and rework
-----BEGIN PGP SIGNATURE-----
iQJDBAABCAAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAl0yK3YPHG9sb2ZAbGl4
b20ubmV0AAoJEIwa5zzehBx3WdUQAJEFRzY4+8VfsUspKmGwzHsrk7t1038JUEDE
VL3yYlvSGeHg5a58AI5PCR5ZCsyPK7Yw9cAcYexd0frFR7BCwKWrjqem0Lb5ovdK
CYM517DRtYPSBMF08Xw4pbZlT0yg65F1e9cf6BlUpkUZ6lJn4gUy8Y4BE6Aw/zuF
QKtQNs6Q8BUZqS3uoOpJ/PY4JiUmLPQPO4Lry7Lud8Z7qgArCC326paC3wwqjLoC
TpoMqb6izt7Vzo4BtTo5TUCyiEFZDlb/thhDySVlYRE7DQJusHBvRO9qgjI2ahOo
1/935q1fJO7S6+Yvc8DIzrD/DrIUOvOshi31F/J6iWKkQkTUxtQwsVReZKaiOfSD
fYxNVCgTcMS6ailKQSMQ0SYgXDa2gWdV3tS9XU8qML3tnDthi1nDmZks0QAAnFPS
bXRcWGtgqeQJ+QJ7yyKrsD9POeaq3Hc5/f1DN34H//Cyn0ip/fD6fkLCMIfUDwmu
TmO2Mnj6/fG/iBK+ToF+DaJ0/u3RiV2MC2vCE+0m3cVI9jtq9iA1y3UlmoaKUhhC
t9znA+u8/Jc5S2zNQriI2Ja5q8nKfihL7Jf68ENvGzLc7YuAqP6yx1LMg1g6Wshc
nLT+kHOF6DCUC3W7a8VuNyaxCwVtTbNTti+nvQVOmV6eaGiD5vzpXkHBWMbOJ7Lh
YOBwGyb4
=ek+j
-----END PGP SIGNATURE-----
Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC-related driver updates from Olof Johansson:
"Various driver updates for platforms and a couple of the small driver
subsystems we merge through our tree:
- A driver for SCU (system control) on NXP i.MX8QXP
- Qualcomm Always-on Subsystem messaging driver (AOSS QMP)
- Qualcomm PM support for MSM8998
- Support for a newer version of DRAM PHY driver for Broadcom (DPFE)
- Reset controller support for Bitmain BM1880
- TI SCI (System Control Interface) support for CPU control on AM654
processors
- More TI sysc refactoring and rework"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (84 commits)
reset: remove redundant null check on pointer dev
soc: rockchip: work around clang warning
dt-bindings: reset: imx7: Fix the spelling of 'indices'
soc: imx: Add i.MX8MN SoC driver support
soc: aspeed: lpc-ctrl: Fix probe error handling
soc: qcom: geni: Add support for ACPI
firmware: ti_sci: Fix gcc unused-but-set-variable warning
firmware: ti_sci: Use the correct style for SPDX License Identifier
soc: imx8: Use existing of_root directly
soc: imx8: Fix potential kernel dump in error path
firmware/psci: psci_checker: Park kthreads before stopping them
memory: move jedec_ddr.h from include/memory to drivers/memory/
memory: move jedec_ddr_data.c from lib/ to drivers/memory/
MAINTAINERS: Remove myself as qcom maintainer
soc: aspeed: lpc-ctrl: make parameter optional
soc: qcom: apr: Don't use reg for domain id
soc: qcom: fix QCOM_AOSS_QMP dependency and build errors
memory: tegra: Fix -Wunused-const-variable
firmware: tegra: Early resume BPMP
soc/tegra: Select pinctrl for Tegra194
...
side. The two main highlights in the core framework are the addition of an bulk
clk_get API that handles optional clks and an extra debugfs file that tells the
developer about the current parent of a clk.
The driver updates are dominated by i.MX in the diffstat, but that is mostly
because that SoC has started converting to the clk_hw style of clk
registration. The next big update is in the Amlogic meson clk driver that
gained some support for audio, cpu, and temperature clks while fixing some PLL
issues. Finally, the biggest thing that stands out is the conversion of a large
part of the Allwinner sunxi-ng driver to the new clk parent scheme that uses
less strings and more pointer comparisons to match clk parents and children up.
In general, it looks like we have a lot of little fixes and tweaks here and
there to clk data along with the normal addition of a handful of new drivers
and a couple new core framework features.
Core:
- Add a 'clk_parent' file in clk debugfs
- Add a clk_bulk_get_optional() API (with devm too)
New Drivers:
- Support gated clk controller on MIPS based BCM63XX SoCs
- Support SiLabs Si5341 and Si5340 chips
- Support for CPU clks on Raspberry Pi devices
- Audsys clock driver for MediaTek MT8516 SoCs
Updates:
- Convert a large portion of the Allwinner sunxi-ng driver to new clk parent scheme
- Small frequency support for SiLabs Si544 chips
- Slow clk support for AT91 SAM9X60 SoCs
- Remove dead code in various clk drivers (-Wunused)
- Support for Marvell 98DX1135 SoCs
- Get duty cycle of generic pwm clks
- Improvement in mmc phase calculation and cleanup of some rate defintions
- Switch i.MX6 and i.MX7 clock drivers to clk_hw based APIs
- Add GPIO, SNVS and GIC clocks for i.MX8 drivers
- Mark imx6sx/ul/ull/sll MMDC_P1_IPG and imx8mm DRAM_APB as critical clock
- Correct imx7ulp nic1_bus_clk and imx8mm audio_pll2_clk clock setting
- Add clks for new Exynos5422 Dynamic Memory Controller driver
- Clock definition for Exynos4412 Mali
- Add CMM (Color Management Module) clocks on Renesas R-Car H3, M3-N, E3, and D3
- Add TPU (Timer Pulse Unit / PWM) clocks on Renesas RZ/G2M
- Support for 32 bit clock IDs in TI's sci-clks for J721e SoCs
- TI clock probing done from DT by default instead of firmware
- Fix Amlogic Meson mpll fractional part and spread sprectrum issues
- Add Amlogic meson8 audio clocks
- Add Amlogic g12a temperature sensors clocks
- Add Amlogic g12a and g12b cpu clocks
- Add TPU (Timer Pulse Unit / PWM) clocks on Renesas R-Car H3, M3-W, and M3-N
- Add CMM (Color Management Module) clocks on Renesas R-Car M3-W
- Add Clock Domain support on Renesas RZ/N1
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAl0uBEERHHNib3lkQGtl
cm5lbC5vcmcACgkQrQKIl8bklSWucw/9ELKlfvdxrc8mdIuzt+CpKdNiSG88shXY
hF+vnuE6Jhv5hmlbA/DbplPTAnHT/FQF65/GPQMAYy2wYO6CjleNxQyepiVv4h8/
tWoXu5vYZXubtQyMnYTffREzjYFPBNAscLUhXNwJKRno7nT0qKCk62WgOMfaW/KN
lP5dKmrL7rdJDUvxHEStrwP515Lg5Wkhj3+XzgbgFUKGuGlvHfwUOEZucT++kqhu
Z1vMjPv2ksHQf3r15BsbX/6jMIONEt2Xd6jA3Lm7ebDXJl2hjX4Gq0Kkl5pmkj2w
F0V7Tw4XYk6DkSl7HQaOBgQ8KV0Mw2L8Vj6eEDhUwx6wPGlQ5YTKkUCJkjs0mUyb
UpO3TuPFN2W0hsTNDzwYpjqcfodDn159XJcduv1/ZpIanUvHgx0uVzQ7iwwYwW+l
VR4SipY5AEn9hpief30X7TAUSKsE4do58imYeoGBrq78zdsJaEcDAMX7AcYdXVQ9
ahBS8ME/d1JEBNdRsSW7eTAfu8dZdI08uR8/T37GRG59XyZSjsyVmZ6kHCYrBygF
AyLNMsXMCbW1rOoIpWkuGMD86XZy40laLg8T7WWTaq28t1VQ0BaBTGM4/eEexs3p
FhZ1M7aH+PsDLrI2IGTBt/4xAMv+dhDS7HnxRlOONbWnLWVqmR+tYzF0aCkqJCmd
O2zWCGffeYs=
=mK0C
-----END PGP SIGNATURE-----
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"This round of clk driver and framework updates is heavy on the driver
update side. The two main highlights in the core framework are the
addition of an bulk clk_get API that handles optional clks and an
extra debugfs file that tells the developer about the current parent
of a clk.
The driver updates are dominated by i.MX in the diffstat, but that is
mostly because that SoC has started converting to the clk_hw style of
clk registration. The next big update is in the Amlogic meson clk
driver that gained some support for audio, cpu, and temperature clks
while fixing some PLL issues. Finally, the biggest thing that stands
out is the conversion of a large part of the Allwinner sunxi-ng driver
to the new clk parent scheme that uses less strings and more pointer
comparisons to match clk parents and children up.
In general, it looks like we have a lot of little fixes and tweaks
here and there to clk data along with the normal addition of a handful
of new drivers and a couple new core framework features.
Core:
- Add a 'clk_parent' file in clk debugfs
- Add a clk_bulk_get_optional() API (with devm too)
New Drivers:
- Support gated clk controller on MIPS based BCM63XX SoCs
- Support SiLabs Si5341 and Si5340 chips
- Support for CPU clks on Raspberry Pi devices
- Audsys clock driver for MediaTek MT8516 SoCs
Updates:
- Convert a large portion of the Allwinner sunxi-ng driver to new clk parent scheme
- Small frequency support for SiLabs Si544 chips
- Slow clk support for AT91 SAM9X60 SoCs
- Remove dead code in various clk drivers (-Wunused)
- Support for Marvell 98DX1135 SoCs
- Get duty cycle of generic pwm clks
- Improvement in mmc phase calculation and cleanup of some rate defintions
- Switch i.MX6 and i.MX7 clock drivers to clk_hw based APIs
- Add GPIO, SNVS and GIC clocks for i.MX8 drivers
- Mark imx6sx/ul/ull/sll MMDC_P1_IPG and imx8mm DRAM_APB as critical clock
- Correct imx7ulp nic1_bus_clk and imx8mm audio_pll2_clk clock setting
- Add clks for new Exynos5422 Dynamic Memory Controller driver
- Clock definition for Exynos4412 Mali
- Add CMM (Color Management Module) clocks on Renesas R-Car H3, M3-N, E3, and D3
- Add TPU (Timer Pulse Unit / PWM) clocks on Renesas RZ/G2M
- Support for 32 bit clock IDs in TI's sci-clks for J721e SoCs
- TI clock probing done from DT by default instead of firmware
- Fix Amlogic Meson mpll fractional part and spread sprectrum issues
- Add Amlogic meson8 audio clocks
- Add Amlogic g12a temperature sensors clocks
- Add Amlogic g12a and g12b cpu clocks
- Add TPU (Timer Pulse Unit / PWM) clocks on Renesas R-Car H3, M3-W, and M3-N
- Add CMM (Color Management Module) clocks on Renesas R-Car M3-W
- Add Clock Domain support on Renesas RZ/N1"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (190 commits)
clk: consoldiate the __clk_get_hw() declarations
clk: sprd: Add check for return value of sprd_clk_regmap_init()
clk: lochnagar: Update DT binding doc to include the primary SPDIF MCLK
clk: Add Si5341/Si5340 driver
dt-bindings: clock: Add silabs,si5341
clk: clk-si544: Implement small frequency change support
clk: add BCM63XX gated clock controller driver
devicetree: document the BCM63XX gated clock bindings
clk: at91: sckc: use dedicated functions to unregister clock
clk: at91: sckc: improve error path for sama5d4 sck registration
clk: at91: sckc: remove unnecessary line
clk: at91: sckc: improve error path for sam9x5 sck register
clk: at91: sckc: add support to free slow clock osclillator
clk: at91: sckc: add support to free slow rc oscillator
clk: at91: sckc: add support to free slow oscillator
clk: rockchip: export HDMIPHY clock on rk3228
clk: rockchip: add watchdog pclk on rk3328
clk: rockchip: add clock id for hdmi_phy special clock on rk3228
clk: rockchip: add clock id for watchdog pclk on rk3328
clk: at91: sckc: add support for SAM9X60
...
- Support gated clk controller on MIPS based BCM63XX SoCs
- Small frequency support for SiLabs Si544 chips
- Support SiLabs Si5341 and Si5340 chips
* clk-bcm63xx:
clk: add BCM63XX gated clock controller driver
devicetree: document the BCM63XX gated clock bindings
* clk-silabs:
clk: Add Si5341/Si5340 driver
dt-bindings: clock: Add silabs,si5341
clk: clk-si544: Implement small frequency change support
* clk-lochnagar:
clk: lochnagar: Update DT binding doc to include the primary SPDIF MCLK
clk: lochnagar: Use new parent_data approach to register clock parents
* clk-rockchip:
clk: rockchip: export HDMIPHY clock on rk3228
clk: rockchip: add watchdog pclk on rk3328
clk: rockchip: add clock id for hdmi_phy special clock on rk3228
clk: rockchip: add clock id for watchdog pclk on rk3328
clk: rockchip: convert pclk_wdt boilerplat to new SGRF_GATE macro
clk: rockchip: add a type from SGRF-controlled gate clocks
clk: rockchip: Remove 48 MHz PLL rate from rk3288
clk: rockchip: add 1.464GHz cpu-clock rate to rk3228
clk: rockchip: Slightly more accurate math in rockchip_mmc_get_phase()
clk: rockchip: Don't yell about bad mmc phases when getting
clk: rockchip: Use clk_hw_get_rate() in MMC phase calculation
* clk-ti:
clk: ti: Use int to check return value from of_property_count_elems_of_size()
firmware: ti_sci: extend clock identifiers from u8 to u32
clk: keystone: sci-clk: extend clock IDs to 32 bits
clk: keystone: sci-clk: probe clocks from DT instead of firmware
clk: keystone: sci-clk: split out the fw clock parsing to own function
clk: keystone: sci-clk: cut down the clock name length
* clk-samsung:
clk: samsung: Add bus clock for GPU/G3D on Exynos4412
clk: samsung: add new clocks for DMC for Exynos5422 SoC
clk: samsung: add BPLL rate table for Exynos 5422 SoC
clk: samsung: add needed IDs for DMC clocks in Exynos5420
clk: samsung: exynos5433: Use of_clk_get_parent_count()
* clk-imx: (38 commits)
clk: imx8mq: Keep uart clocks on during system boot
clk: imx: Remove __init for imx_register_uart_clocks() API
clk: imx6q: fix section mismatch warning
clk: imx8mq: Use devm_platform_ioremap_resource() instead of of_iomap()
clk: imx8mq: Use imx_check_clocks() API directly
clk: imx: Remove __init for imx_check_clocks() API
clk: imx6sll: Switch to clk_hw based API
clk: imx7d: Switch to clk_hw based API
clk: imx6ul: Switch to clk_hw based API
clk: imx6sx: Switch to clk_hw based API
clk: imx6q: Switch to clk_hw based API
clk: imx6sl: Switch to clk_hw based API
clk: imx: Switch wrappers to clk_hw based API
clk: imx: clk-fixup-mux: Switch to clk_hw based API
clk: imx: clk-fixup-div: Switch to clk_hw based API
clk: imx: clk-gate-exclusive: Switch to clk_hw based API
clk: imx: clk-pfd: Switch to clk_hw based API
clk: imx: clk-pllv3: Switch to clk_hw based API
clk: imx: clk-gate2: Switch to clk_hw based API
clk: imx: clk-cpu: Switch to clk_hw based API
...
* clk-allwinner: (29 commits)
clk: Simplify debugfs printing and add a newline
clk: sunxi-ng: sun8i-r: Use local parent references for SUNXI_CCU_GATE
clk: sunxi-ng: a80-usb: Use local parent references for SUNXI_CCU_GATE
clk: sunxi-ng: gate: Add macros for referencing local clock parents
clk: sunxi-ng: h6-r: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: h6: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a64: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: f1c100s: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: sun8i-r: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: v3s: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: r40: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: h3: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a33: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a23: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a31: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: sun5i: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: a10: Use local parent references for CLK_FIXED_FACTOR
clk: sunxi-ng: sun8i-r: Use local parent references for CLK_HW_INIT_*
clk: sunxi-ng: switch to of_clk_hw_register() for registering clks
clk: fixed-factor: Add CLK_FIXED_FACTOR_FW_NAME for DT clock-names parent
...
Pull networking updates from David Miller:
"Some highlights from this development cycle:
1) Big refactoring of ipv6 route and neigh handling to support
nexthop objects configurable as units from userspace. From David
Ahern.
2) Convert explored_states in BPF verifier into a hash table,
significantly decreased state held for programs with bpf2bpf
calls, from Alexei Starovoitov.
3) Implement bpf_send_signal() helper, from Yonghong Song.
4) Various classifier enhancements to mvpp2 driver, from Maxime
Chevallier.
5) Add aRFS support to hns3 driver, from Jian Shen.
6) Fix use after free in inet frags by allocating fqdirs dynamically
and reworking how rhashtable dismantle occurs, from Eric Dumazet.
7) Add act_ctinfo packet classifier action, from Kevin
Darbyshire-Bryant.
8) Add TFO key backup infrastructure, from Jason Baron.
9) Remove several old and unused ISDN drivers, from Arnd Bergmann.
10) Add devlink notifications for flash update status to mlxsw driver,
from Jiri Pirko.
11) Lots of kTLS offload infrastructure fixes, from Jakub Kicinski.
12) Add support for mv88e6250 DSA chips, from Rasmus Villemoes.
13) Various enhancements to ipv6 flow label handling, from Eric
Dumazet and Willem de Bruijn.
14) Support TLS offload in nfp driver, from Jakub Kicinski, Dirk van
der Merwe, and others.
15) Various improvements to axienet driver including converting it to
phylink, from Robert Hancock.
16) Add PTP support to sja1105 DSA driver, from Vladimir Oltean.
17) Add mqprio qdisc offload support to dpaa2-eth, from Ioana
Radulescu.
18) Add devlink health reporting to mlx5, from Moshe Shemesh.
19) Convert stmmac over to phylink, from Jose Abreu.
20) Add PTP PHC (Physical Hardware Clock) support to mlxsw, from
Shalom Toledo.
21) Add nftables SYNPROXY support, from Fernando Fernandez Mancera.
22) Convert tcp_fastopen over to use SipHash, from Ard Biesheuvel.
23) Track spill/fill of constants in BPF verifier, from Alexei
Starovoitov.
24) Support bounded loops in BPF, from Alexei Starovoitov.
25) Various page_pool API fixes and improvements, from Jesper Dangaard
Brouer.
26) Just like ipv4, support ref-countless ipv6 route handling. From
Wei Wang.
27) Support VLAN offloading in aquantia driver, from Igor Russkikh.
28) Add AF_XDP zero-copy support to mlx5, from Maxim Mikityanskiy.
29) Add flower GRE encap/decap support to nfp driver, from Pieter
Jansen van Vuuren.
30) Protect against stack overflow when using act_mirred, from John
Hurley.
31) Allow devmap map lookups from eBPF, from Toke Høiland-Jørgensen.
32) Use page_pool API in netsec driver, Ilias Apalodimas.
33) Add Google gve network driver, from Catherine Sullivan.
34) More indirect call avoidance, from Paolo Abeni.
35) Add kTLS TX HW offload support to mlx5, from Tariq Toukan.
36) Add XDP_REDIRECT support to bnxt_en, from Andy Gospodarek.
37) Add MPLS manipulation actions to TC, from John Hurley.
38) Add sending a packet to connection tracking from TC actions, and
then allow flower classifier matching on conntrack state. From
Paul Blakey.
39) Netfilter hw offload support, from Pablo Neira Ayuso"
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (2080 commits)
net/mlx5e: Return in default case statement in tx_post_resync_params
mlx5: Return -EINVAL when WARN_ON_ONCE triggers in mlx5e_tls_resync().
net: dsa: add support for BRIDGE_MROUTER attribute
pkt_sched: Include const.h
net: netsec: remove static declaration for netsec_set_tx_de()
net: netsec: remove superfluous if statement
netfilter: nf_tables: add hardware offload support
net: flow_offload: rename tc_cls_flower_offload to flow_cls_offload
net: flow_offload: add flow_block_cb_is_busy() and use it
net: sched: remove tcf block API
drivers: net: use flow block API
net: sched: use flow block API
net: flow_offload: add flow_block_cb_{priv, incref, decref}()
net: flow_offload: add list handling functions
net: flow_offload: add flow_block_cb_alloc() and flow_block_cb_free()
net: flow_offload: rename TCF_BLOCK_BINDER_TYPE_* to FLOW_BLOCK_BINDER_TYPE_*
net: flow_offload: rename TC_BLOCK_{UN}BIND to FLOW_BLOCK_{UN}BIND
net: flow_offload: add flow_block_cb_setup_simple()
net: hisilicon: Add an tx_desc to adapt HI13X1_GMAC
net: hisilicon: Add an rx_desc to adapt HI13X1_GMAC
...
This tag adds support for the Bitmain BM1880 reset controller to the
reset-simple driver and fixes a spelling mistake in the i.MX7 reset
controller binding document.
-----BEGIN PGP SIGNATURE-----
iI0EABYIADUWIQRRO6F6WdpH1R0vGibVhaclGDdiwAUCXR3SoxcccC56YWJlbEBw
ZW5ndXRyb25peC5kZQAKCRDVhaclGDdiwEb6AP4i9FSRodn9AFs8jKcgUC63SPyL
L5loesyFpiTVpunMsQEAlexZ6wSY2zdfVrDXh1lLHmuACc8AuebItcdpaRwc3As=
=Zp5w
-----END PGP SIGNATURE-----
Merge tag 'reset-for-v5.3' of git://git.pengutronix.de/git/pza/linux into arm/drivers
Reset controller changes for v5.3
This tag adds support for the Bitmain BM1880 reset controller to the
reset-simple driver and fixes a spelling mistake in the i.MX7 reset
controller binding document.
* tag 'reset-for-v5.3' of git://git.pengutronix.de/git/pza/linux:
dt-bindings: reset: imx7: Fix the spelling of 'indices'
reset: Add reset controller support for BM1880 SoC
dt-bindings: reset: Add devicetree binding for BM1880 reset controller
Link: https://lore.kernel.org/r/1562236632.6641.14.camel@pengutronix.de
Signed-off-by: Olof Johansson <olof@lixom.net>
for rk3288-veyron boards.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAl0Z0DEQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgbHRB/40x1DBDesIZnjpbnFPTBGcqhMXgc/tfawK
jtU7fwFiToyvXXzauY877+njhC54MCwF9JhtRfxn0c5O7WRBCnZnzRIfQpqKxdXD
VmIx5cKMI057oG0p4RB9tSDTHNAfg0lw9M9DQVw4f/Yl2M0kY/yk3TnL2vReMxMQ
mGd0j8KDAHnpdBgYpKQPSxQdbV8i5EFkb0RcvrEZ/VPHrikg74y91nbgSjBu3EgI
+NecSglseOG+SVzPzxbnU1kZ4E7Z/zXq6UQmpoVw2710MNn+QWrd1+F7bAcnszaO
KJCdHRM8Icpx9mNnekjonzYuNWOAEZf+LFS2FncR6qjrzFgBWi7c
=8Tz/
-----END PGP SIGNATURE-----
Merge tag 'v5.3-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt
Display support for rk3228/rk3229 (up to hdmi output) and more love
for rk3288-veyron boards.
* tag 'v5.3-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: add display nodes for rk322x
ARM: dts: rockchip: fix vop iommu-cells on rk322x
clk: rockchip: add clock id for hdmi_phy special clock on rk3228
clk: rockchip: add clock id for watchdog pclk on rk3328
Revert "ARM: dts: rockchip: set PWM delay backlight settings for Minnie"
ARM: dts: rockchip: Configure BT_DEV_WAKE in on rk3288-veyron
ARM: dts: rockchip: Configure BT_HOST_WAKE as wake-up signal on veyron
Signed-off-by: Olof Johansson <olof@lixom.net>
The fixes have no functional impact:
- Fix some comment text in the memory management vmalloc_fault path.
- Fix some warnings from the DT compiler in our newly-added DT files.
- Change the newly-added DT bindings such that SoC IP blocks with
external I/O are marked as "disabled" by default, then enable them
explicitly in board DT files when the devices are used on the board.
This aligns the bindings with existing upstream practice.
- Add the MIT license as an option for a minor header file, at the
request of one of the U-Boot maintainers.
The RISC-V defconfig update builds the SiFive SPI driver and the
MMC-SPI driver by default. The intention here is to make v5.2 more
usable for testers and users with RISC-V hardware.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEElRDoIDdEz9/svf2Kx4+xDQu9KksFAl0WljgACgkQx4+xDQu9
KksbXQ//fohS8vHCMCkqj3rtKM3fuf9DRdZZbZf0WdPL5463JxTTK8JULrrawjL5
j57Ve/EFRQFVSELBtWd0u/4sgAcgGmyJWnfexk3LYISNMZCjBe6Zuz+7Q9Ykbhoa
YKpjOreDeO+fbQpGqMHK2suD5WFVXsDfiI3TmHE6xGIm0sWdpANawpz2K4CzBkEO
XOaOsmVPT8HfN2f0XodCmzo2VrGNeEutqyxc9+X1Ah0nxBecj56t9TK9wnseTWrE
hWjnMw2KMZFTnmtOOQ8kB0EfcRDZ8AvXymAb1BHwuWwmxLFrGELsGKRWzrH+qhyT
4mlexMjdyz69N1uYWieO6FWGMqbIm+ncR7cMwIl2hOErtJiSoUf5cwGhflXMk9ph
b/oWmNzLGE/7ib/Uo1tfaBmdEYzlzziEtkB0DDWIf16wqMVK5zyoPknnHC7WPIBa
7WyN+2FKA7b0440Kqfywgq9CMZ3odvhXCLAEmFBdwaa9wyKGsOR6sUZhPXGUSjyL
oKe4oszbKmqaUboxTo/YzDYHpD4BPGoBMievY8kCO+TcewN2ARczJngQyc2FLS+B
BUMFZmTUr85pt1pcnNqK84D5N6alldLqLbKwczYq3PvtHzIR2kFUfZGMwQ0DlEh2
IOJMDcmHehuCmCAz4jnNykOlJPDIMIYiVLeUtGp+1IwZjcvLfxg=
=+HL9
-----END PGP SIGNATURE-----
Merge tag 'riscv-for-v5.2/fixes-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V fixes from Paul Walmsley:
"Minor RISC-V fixes and one defconfig update.
The fixes have no functional impact:
- Fix some comment text in the memory management vmalloc_fault path.
- Fix some warnings from the DT compiler in our newly-added DT files.
- Change the newly-added DT bindings such that SoC IP blocks with
external I/O are marked as "disabled" by default, then enable them
explicitly in board DT files when the devices are used on the
board. This aligns the bindings with existing upstream practice.
- Add the MIT license as an option for a minor header file, at the
request of one of the U-Boot maintainers.
The RISC-V defconfig update builds the SiFive SPI driver and the
MMC-SPI driver by default. The intention here is to make v5.2 more
usable for testers and users with RISC-V hardware"
* tag 'riscv-for-v5.2/fixes-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
riscv: mm: Fix code comment
dt-bindings: clock: sifive: add MIT license as an option for the header file
dt-bindings: riscv: resolve 'make dt_binding_check' warnings
riscv: dts: Re-organize the DT nodes
RISC-V: defconfig: enable MMC & SPI for RISC-V
The new route handling in ip_mc_finish_output() from 'net' overlapped
with the new support for returning congestion notifications from BPF
programs.
In order to handle this I had to take the dev_loopback_xmit() calls
out of the switch statement.
The aquantia driver conflicts were simple overlapping changes.
Signed-off-by: David S. Miller <davem@davemloft.net>
- Do a DT/firmware lookup in clk_core_get() even when the DT index is a
nonsensical value
- Fix some clk data typos in the Amlogic DT headers/code
- Avoid returning junk in the TI clk driver when an invalid clk is
looked for
- Fix dividers for the emac clks on Stratix10 SoCs
- Fix default HDA rates on Tegra210 to correct distorted audio
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAl0VIHcRHHNib3lkQGtl
cm5lbC5vcmcACgkQrQKIl8bklSU0Ww//XVDS0JqiWcEopLc8dLrjxn2n7W3qlbB9
8RqkrvFK/yv9Hrd1OqTSJLnrDQKb0zYnzjzU0g7Isdk81uecRQDJksjWQ/laR5i4
ut5QOwV8IBSRl6Mu4XoMHvt9apysXX9od8B6Iu1fhbgmQeKlVkX/PYuT+mcQtMjc
2Zg6ILQpkFaXhB9vQxVZwwmGZyR4/pfNCltl8A1Zg9ZkWgpOvv+7wHo/5AYNIBYM
JbynlCdOii9gNXwoXPnayNvqwKNi0NEEfzOX/RuSarwrRVKdbqbWKhKlHTRv3LwC
myo+dh/7l1l+1ANhBedzbnSa5YHSUyZXjkO+pKBctJEOGMV9+fbGEOvxt1LPBr7X
IrSevXYwPfgHdxxnoMM+S5OTWYyv9jOTTXEwIc3rAoDnAJWcLsg6V8MEGL/CGQ7T
yrSRARGCowU73rJXwfTayMKSqQgaTGmB00x4lewQK29DA0uMunQTzRU7qjOAe919
ECgdYV6WJcRCThrAfknARD/FS+J07fMqyLD9IFd2bFQuGWCq8EFT7Ky2t89bXULG
SMvLUe9CUpURtfdrDjz8h+VzmAStoAWck63EffgymPILRhRI4xY+Mr/YyfQ07rMu
BTSsj9wd8AywhmOgi42TVOFZS39bDCAytJ9LMaxDyNXsDVi/REC3O43z9kyHoUQB
JIyQyHFSRD0=
=3QYB
-----END PGP SIGNATURE-----
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"A handful of clk driver fixes and one core framework fix
- Do a DT/firmware lookup in clk_core_get() even when the DT index is
a nonsensical value
- Fix some clk data typos in the Amlogic DT headers/code
- Avoid returning junk in the TI clk driver when an invalid clk is
looked for
- Fix dividers for the emac clks on Stratix10 SoCs
- Fix default HDA rates on Tegra210 to correct distorted audio"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: socfpga: stratix10: fix divider entry for the emac clocks
clk: Do a DT parent lookup even when index < 0
clk: tegra210: Fix default rates for HDA clocks
clk: ti: clkctrl: Fix returning uninitialized data
clk: meson: meson8b: fix a typo in the VPU parent names array variable
clk: meson: fix MPLL 50M binding id typo
Add the needed clock id to enable clock settings from devicetree.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Justin Swartz <justin.swartz@risingedge.co.za>
At Bin Meng's request, add the MIT license as an option for the SiFive
FU540 PRCI header file.
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
The madera driver was merged too late to catch Thomas Gleixner's cleanup
of the SPDX headers tree wide. Update the headers to match what was done
in that patch.
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
The nand_clk is actually called the nand_x_clk and the parent is the
l4_mp_clk, not the l4_main_clk. The nand_clk is a child of the
nand_x_clk and has a fixed divider of 4. The same is true for the
nand_ecc_clk.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* Add ACPI support to Qualcomm GENI SE
* Update Qualcomm Maintainers entry to remove David Brown as maintainer and
fixup typos and incorrect DT file entry
* Fixup APR domain id usage and making callbacks in non-atomic context
* Add AOSS QMP driver and bindings
* Add power domains for MSM8998 and QCS404 in QCOM RPMPD
* Add corner macros, max state support, and fixups for setting performance state
for Qcom RPMPD
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJdCeKEAAoJEFKiBbHx2RXVwvsP/3SBUTeyDP7HsD1+D9f8ojhC
8TDQIpQw9jB+txczdnnoF5vewALpwc3E+intuUZd3oOPB6Nw/g6VU73HDGSDOBHc
nbAf5UjpJgyo7XI+tJk9/m27Ee7y+MIzrk2qtDoboOv0/PZzfrAoFpm75mFJsylw
luf3TMCTDd23aj6HxVe6dzz5F0gHVxF8hldlDkgiQZXGK0h/yInHEYgRe8vBdQGD
wRkU8jKBU49n3OOY7qqD9PKKNSREC6nYxWIK/EJdjaMSNlwmzNJYUXANgtJj4/6G
WmNBA84EplqDJIz6GJ6u5oTYQYISxNlvk0w0USmtXFTktv4wP1IsXb9swZGsYD2B
lD825pM72tO3YqS14HHZ/GvxNsZvn5THPlUrp5Z5s5o+l4HL88FxHOfd6vk/H5mF
dP/MO3xSIRD65FHZMOoSevAJkXtxZhAYNcaTBWWCPpJwgb6iPOY4q17R5ODATJgA
5qJmebzWEn0AoseVEx6PTiejInf6yoDeC5iwcYEjIXqESZrLTvs0+kuZ/nbsD5v4
1yUWGpw1fhVctYmesJk7CfQ2tFLbTtSH+1XTxHnqltriy1I01meTIA5azSaAumzx
YGzVhmsAp0RxmNPjB41L8B5A3V1LfqXcQwauT5pCzGif9uQKxpjUoS6gSwvAa8Da
QAuwPgQEH5ISDat755pO
=JunO
-----END PGP SIGNATURE-----
Merge tag 'qcom-drivers-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers
Qualcomm ARM Based Driver Updates for v5.3
* Add ACPI support to Qualcomm GENI SE
* Update Qualcomm Maintainers entry to remove David Brown as maintainer and
fixup typos and incorrect DT file entry
* Fixup APR domain id usage and making callbacks in non-atomic context
* Add AOSS QMP driver and bindings
* Add power domains for MSM8998 and QCS404 in QCOM RPMPD
* Add corner macros, max state support, and fixups for setting performance state
for Qcom RPMPD
* tag 'qcom-drivers-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
soc: qcom: geni: Add support for ACPI
MAINTAINERS: Remove myself as qcom maintainer
soc: qcom: apr: Don't use reg for domain id
soc: qcom: fix QCOM_AOSS_QMP dependency and build errors
soc: qcom: Add AOSS QMP driver
dt-bindings: soc: qcom: Add AOSS QMP binding
qcom: apr: Make apr callbacks in non-atomic context
soc: qcom: rpmpd: Add MSM8998 power-domains
dt-bindings: power: Add rpm power domain bindings for msm8998
soc: qcom: rpmpd: Add QCS404 power-domains
dt-bindings: power: Add rpm power domain bindings for qcs404
soc: qcom: rpmpd: Modify corner defining macros
soc: qcom: rpmpd: Add support to set rpmpd state to max
soc: qcom: rpmpd: fixup rpmpd set performance state
MAINTAINER: Fix Qualcomm ETHQOS ethernet DT file
MAINTAINERS: fix typo in file name
Signed-off-by: Olof Johansson <olof@lixom.net>
- This is a set of device tree changes with new clocks - adding
clock info for i.MX8 GPIO and SNVS RTC device.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJdEY9IAAoJEFBXWFqHsHzONzkH/iQWmmauxY3ONsDhCOiq2xkz
agKfN77pgM0005NJl8bP/+wyl6JXozpq31PJrbWPvdZCwElEzBykmWZzyG2cl6Bx
ajwsldhBzMoYKvjVH0MD3ldPXoANsvfIQiAyVzPHY/tCBHI6hnaJKWCaQ0fsqg5M
vZ0lf5Adqh9MN7lBKWBz1tbOgqCNAVdhRrvLdrTuoQ/asjivqzl3oXXMWzzrc4lK
pUGPg1+iqf/MSBVoX8F3ETO9W+GjdjHE0qoGttXf90w2epQZqO5Ta2mfhzyF4fkE
pcPGKQTASi+zOcUuzgM97TGfWbeOYhd0kRmInZVZt+Wce2Ju4MO5M0Iyxp6xvJI=
=GaZH
-----END PGP SIGNATURE-----
Merge tag 'imx-dt-clkdep-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt
i.MX DT changes with new clock for 5.3:
- This is a set of device tree changes with new clocks - adding
clock info for i.MX8 GPIO and SNVS RTC device.
* tag 'imx-dt-clkdep-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: imx8mq: add clock for SNVS RTC node
arm64: dts: imx8mm: add clock for SNVS RTC node
arm64: dts: imx8mm: add clock for GPIO node
clk: imx8m: Add GIC clock
dt-bindings: clock: imx8m: Add GIC clock
clk: imx8mm: add SNVS clock to clock tree
dt-bindings: clock: imx8mm: Add SNVS clock
clk: imx8mq: add SNVS clock to clock tree
dt-bindings: clock: imx8mq: Add SNVS clock
clk: imx8mm: add GPIO clocks to clock tree
dt-bindings: clock: imx8mm: Add GPIO clocks
Signed-off-by: Olof Johansson <olof@lixom.net>
This contains the bulk of the Tegra changes this cycle. It has a bunch
of improvements across almost all boards. These are mostly small and not
too exciting additions.
Most notably perhaps is the continuation of Jetson Nano support, which
is now mostly on feature parity with Jetson TX1.
-----BEGIN PGP SIGNATURE-----
iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAl0M7HYTHHRyZWRpbmdA
bnZpZGlhLmNvbQAKCRDdI6zXfz6zoeIUD/9udVMjomFq6udm5zzCazIsg7Aab3/4
ctSLRppFCsiC01BInPTTwSPh0Lv0LJ5EALvIXIDyyel9xApJ66kOCQAVqVCyPUmv
exqGTsKX44EzAYA2DVJR+qFDqPG4RD37PiBPkys7q7+H+sA8mz+dBNDckv76VYP5
04xbv3rWC3NAs31i6NuiPitoSxpKBwfvguSdGS0BII8soI0yhilvqNnZp08XRdx7
0W2AlOZvqFvti7288xeQPk57LJaR6pE7rnb1B5bPJwEzl7zRnu7A20u99xVZclTx
XtHVXj5c52hVO1DKQ1mUL01xiA6Q0Ru+cfhLiEjaBot4MVoDkL0djeZYWG+Z1TWq
NdKOaoi1Qiwpd6YbzyCWMvurFt8ZW2QDbu8hGf/jzI6TIogcajVC9gzm82kFnfu3
1OefivyVx0WiXsTn+yIBI0NAiza5joZgh9fdX7R38l89oOx3VrQwyClJKFNSbkwV
veI7UTLTZ2iKIwTwEoBaP2kO4SZKZ3/uvXdz89Pck8UooIeC9yU3aqcMZCyInXmn
+MQlGiI2n5IIRbmNMKNHeece1gDzuvo9RSqzonwxNG3Zvt4J2bbfv7Q91itAJMjr
mq8vNmVutfS36zgzcfbhfkPVO8hHX4OxOHWISZOtXbyCSzfY3j/HTuPRSLZBU2XZ
xMFsMfefTEtcWA==
=Ea0t
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-5.3-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt
arm64: tegra: Device tree changes for v5.3-rc1
This contains the bulk of the Tegra changes this cycle. It has a bunch
of improvements across almost all boards. These are mostly small and not
too exciting additions.
Most notably perhaps is the continuation of Jetson Nano support, which
is now mostly on feature parity with Jetson TX1.
* tag 'tegra-for-5.3-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (28 commits)
arm64: tegra: Enable PCIe slots in P2972-0000 board
arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT
arm64: tegra: Add PEX DPD states as pinctrl properties
arm64: tegra: Enable ACONNECT, ADMA and AGIC
arm64: tegra: Add ACONNECT, ADMA and AGIC nodes
arm64: tegra: Sort device tree nodes alphabetically
arm64: tegra: Fix Jetson Nano GPU regulator
arm64: tegra: Update Jetson TX1 GPU regulator timings
arm64: tegra: Fix AGIC register range
arm64: tegra: Add INA3221 channel info for Jetson TX2
arm64: tegra: Enable PWM on Jetson Nano
arm64: tegra: Enable CPU sleep on Jetson Nano
arm64: tegra: Add ID EEPROMs on Jetson Nano
arm64: tegra: Add ID EEPROM for Jetson TX2 Developer Kit
arm64: tegra: Add ID EEPROM for Jetson TX2 module
arm64: tegra: Add ID EEPROM for Jetson TX1 Developer Kit
arm64: tegra: Add ID EEPROM for Jetson TX1 module
arm64: tegra: Don't use architected timer for suspend on Tegra210
arm64: tegra: Mark architected timer as always on
arm64: tegra: Add pin control states for I2C on Tegra186
...
Signed-off-by: Olof Johansson <olof@lixom.net>
The Cirrus Logic Madera codecs are a family of related codecs with
extensive digital and analogue I/O, digital mixing and routing,
signal processing and programmable DSPs.
Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Based on 2 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation #
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 4122 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Enrico Weigelt <info@metux.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Based on 1 normalized pattern(s):
gplv2 only
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 4 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Enrico Weigelt <info@metux.net>
Reviewed-by: Armijn Hemel <armijn@tjaldur.nl>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.666840552@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Based on 1 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation this program is
distributed in the hope that it will be useful but without any
warranty without even the implied warranty of merchantability or
fitness for a particular purpose see http www gnu org licenses gpl 2
0 html for more details
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 2 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Enrico Weigelt <info@metux.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081205.243665028@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Based on 1 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation this program is
distributed in the hope that it will be useful but without any
warranty without even the implied warranty of merchantability or
fitness for a particular purpose see the gnu general public license
for more details you should have received a copy of the gnu general
public license along with this program if not see http www gnu org
licenses
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 503 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Enrico Weigelt <info@metux.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190602204653.811534538@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Based on 1 normalized pattern(s):
this software is licensed under the terms of the gnu general public
license version 2 as published by the free software foundation and
may be copied distributed and modified under those terms
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 6 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190602204653.720704315@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Add ID and gate for bus clock for GPU (Mali 400) on Exynos4412.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
The patch on this branch adds bindings for tohdmitx, including a header
to be used in DT bindings which needs to be shared with the arm-soc tree
in order to allow system DTs to be merged.
-----BEGIN PGP SIGNATURE-----
iQFHBAABCgAxFiEEreZoqmdXGLWf4p/qJNaLcl1Uh9AFAl0D6tUTHGJyb29uaWVA
a2VybmVsLm9yZwAKCRAk1otyXVSH0DEzB/4gIkIbWlgOEl1S8fNCh2ZkmTSudsof
8Sf8dsM+ZAQgren2sUg0dVpM2t6sc0Aq4OkNoC51VbxhSXM1Cpka3djDMsb59L4Z
74Lok9kA0S4nZ+qlLGh5KK4vFrVI7DAusxkl6vDVghR78T+FDwe5mVAKffYgRUsa
pswq8IeYrFk1KocIT3y3BFt7qhiERaPNLUtC2RCPaHjNoWPZHGaPG7Y+fWeoZ8gn
blh7FNvSQwiBATEFXpg0pH7ZZHjIHN7pHeCF2ZfnV0pMi0ylYq8bZqM24hbvbHBZ
x+16nYtYpQdMJYxR7TJReARUGb/Koi6nHBNv1oulF0lmsiP1JCNwKZwp
=4nXg
-----END PGP SIGNATURE-----
Merge tag 'asoc-tohdmitx' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into HEAD
ASoC: tohdmitx bindings
The patch on this branch adds bindings for tohdmitx, including a header
to be used in DT bindings which needs to be shared with the arm-soc tree
in order to allow system DTs to be merged.
# gpg: Signature made Fri 14 Jun 2019 11:43:33 AM PDT
# gpg: using RSA key ADE668AA675718B59FE29FEA24D68B725D5487D0
# gpg: issuer "broonie@kernel.org"
# gpg: Good signature from "Mark Brown <broonie@sirena.org.uk>" [full]
# gpg: aka "Mark Brown <broonie@debian.org>" [full]
# gpg: aka "Mark Brown <broonie@kernel.org>" [full]
# gpg: aka "Mark Brown <broonie@tardis.ed.ac.uk>" [full]
# gpg: aka "Mark Brown <broonie@linaro.org>" [unknown]
# gpg: aka "Mark Brown <Mark.Brown@linaro.org>" [unknown]
* tag 'asoc-tohdmitx' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound:
ASoC: meson: add tohdmitx DT bindings
Add the bindings and the related documentation for the audio hdmitx
control glue of the Amlogic g12a SoC family
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Add binding for the QMP based side-channel communication mechanism to
the AOSS, which is used to control resources not exposed through the
RPMh interface.
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add clock ids used by the temperature sensors of the G12A Socs
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> [fixed commit message]
The audio controllers on Meson8, Meson8b and Meson8m2 use similar
(potentially the same) audio clocks as GXBB, GXL and GXM. Add the
CLKID_CTS_AMCLK, CLKID_CTS_MCLK_I958 and CLKID_CTS_I958 clock IDs so
they can be used for the audio controllers.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Enabling PCIe requires several of the PCIe related resets from GCC, so
add them all.
Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Some ISDN files that got removed in net-next had some changes
done in mainline, take the removals.
Signed-off-by: David S. Miller <davem@davemloft.net>
The GPU for msm8998 has its own clock controller. Document it.
Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Define new IDs for clocks used by Dynamic Memory Controller in
Exynos5422 SoC.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Based on 1 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation you should have received a
copy of the gnu general public license along with this program if
not see http www gnu org licenses
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 30 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190531190115.962665879@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Based on 1 normalized pattern(s):
this program is free software you can distribute it and or modify it
under the terms of the gnu general public license version 2 as
published by the free software foundation this program is
distributed in the hope it will be useful but without any warranty
without even the implied warranty of merchantability or fitness for
a particular purpose see the gnu general public license for more
details
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 24 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Armijn Hemel <armijn@tjaldur.nl>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190531190115.872212424@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Based on 1 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license as published by
the free software foundation version 2 of the license
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 315 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Armijn Hemel <armijn@tjaldur.nl>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190531190115.503150771@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Based on 1 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms and conditions of the gnu general public license
version 2 as published by the free software foundation
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 101 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190531190113.822954939@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Based on 1 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms and conditions of the gnu general public license
version 2 as published by the free software foundation this program
is distributed in the hope it will be useful but without any
warranty without even the implied warranty of merchantability or
fitness for a particular purpose see the gnu general public license
for more details
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 263 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190529141901.208660670@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Based on 1 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 and
only version 2 as published by the free software foundation this
program is distributed in the hope that it will be useful but
without any warranty without even the implied warranty of
merchantability or fitness for a particular purpose see the gnu
general public license for more details
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 294 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190529141900.825281744@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Based on 1 normalized pattern(s):
this software is licensed under the terms of the gnu general public
license version 2 as published by the free software foundation and
may be copied distributed and modified under those terms this
program is distributed in the hope that it will be useful but
without any warranty without even the implied warranty of
merchantability or fitness for a particular purpose see the gnu
general public license for more details
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 285 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190529141900.642774971@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The phylink conflict was between a bug fix by Russell King
to make sure we have a consistent PHY interface mode, and
a change in net-next to pull some code in phylink_resolve()
into the helper functions phylink_mac_link_{up,down}()
On the dp83867 side it's mostly overlapping changes, with
the 'net' side removing a condition that was supposed to
trigger for RGMII but because of how it was coded never
actually could trigger.
Signed-off-by: David S. Miller <davem@davemloft.net>
Based on 1 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of version 2 of the gnu general public license as
published by the free software foundation
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 107 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Richard Fontana <rfontana@redhat.com>
Reviewed-by: Steve Winslow <swinslow@gmail.com>
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190528171438.615055994@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Based on 1 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms and conditions of the gnu general public license
version 2 as published by the free software foundation this program
is distributed in the hope it will be useful but without any
warranty without even the implied warranty of merchantability or
fitness for a particular purpose see the gnu general public license
for more details you should have received a copy of the gnu general
public license along with this program if not see http www gnu org
licenses
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 228 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Steve Winslow <swinslow@gmail.com>
Reviewed-by: Richard Fontana <rfontana@redhat.com>
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Based on 1 normalized pattern(s):
license terms gnu general public license gpl version 2
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 161 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com>
Reviewed-by: Steve Winslow <swinslow@gmail.com>
Reviewed-by: Richard Fontana <rfontana@redhat.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190528170027.447718015@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Based on 1 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation this program is
distributed in the hope that it will be useful but without any
warranty without even the implied warranty of merchantability or
fitness for a particular purpose see the gnu general public license
for more details
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 655 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Richard Fontana <rfontana@redhat.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190527070034.575739538@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Based on 3 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license as published by
the free software foundation either version 2 of the license or at
your option any later version this program is distributed in the
hope that it will be useful but without any warranty without even
the implied warranty of merchantability or fitness for a particular
purpose see the gnu general public license for more details
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license as published by
the free software foundation either version 2 of the license or at
your option any later version [author] [kishon] [vijay] [abraham]
[i] [kishon]@[ti] [com] this program is distributed in the hope that
it will be useful but without any warranty without even the implied
warranty of merchantability or fitness for a particular purpose see
the gnu general public license for more details
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license as published by
the free software foundation either version 2 of the license or at
your option any later version [author] [graeme] [gregory]
[gg]@[slimlogic] [co] [uk] [author] [kishon] [vijay] [abraham] [i]
[kishon]@[ti] [com] [based] [on] [twl6030]_[usb] [c] [author] [hema]
[hk] [hemahk]@[ti] [com] this program is distributed in the hope
that it will be useful but without any warranty without even the
implied warranty of merchantability or fitness for a particular
purpose see the gnu general public license for more details
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-or-later
has been chosen to replace the boilerplate/reference in 1105 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Richard Fontana <rfontana@redhat.com>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190527070033.202006027@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Based on 1 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license as published by
the free software foundation either version 2 of the license or at
your option any later version
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-or-later
has been chosen to replace the boilerplate/reference in 3029 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Add RPM power domain bindings for the msm8998 family of SoC
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Jeffrey Hugo <jhugo@codeaurora.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <agross@kernel.org>
Add RPM power domain bindings for the qcs404 family of SoC
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Jeffrey Hugo <jhugo@codeaurora.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
[sibis: Add supported rpmpd states for qcs404]
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <agross@kernel.org>
Based on 1 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license as published by
the free software foundation either version 2 of the license or at
your option any later version this program is distributed in the
hope that it will be useful but without any warranty without even
the implied warranty of merchantability or fitness for a particular
purpose see the gnu general public license for more details you
should have received a copy of the gnu general public license along
with this program if not write to the free software foundation inc
675 mass ave cambridge ma 02139 usa
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-or-later
has been chosen to replace the boilerplate/reference in 441 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Michael Ellerman <mpe@ellerman.id.au> (powerpc)
Reviewed-by: Richard Fontana <rfontana@redhat.com>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190520071858.739733335@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This should be defined in the clock tree so that parents are not
shutdown by accident
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add macro for the SNVS clock of the i.MX8MM.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The clock output is generally only used for testing and development and
not used to daisy-chain PHYs. It's just a source of RF noise afterward.
Add a mux value for "off". I've added it as another enumeration to the
output property. In the actual PHY, the mux and the output enable are
independently controllable. However, it doesn't seem useful to be able
to describe the mux setting when the output is disabled.
Document that PHY's default setting will be left as is if the property
is omitted.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Trent Piepho <tpiepho@impinj.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
Add macro for the SNVS clock of the i.MX8MQ.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Now that all users of the old definitions have been updated to use the
Tegra186 specific prefix, remove the unused definitions.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Based on 2 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license as published by
the free software foundation either version 2 of the license or at
your option any later version this program is distributed in the
hope that it will be useful but without any warranty without even
the implied warranty of merchantability or fitness for a particular
purpose see the gnu general public license for more details you
should have received a copy of the gnu general public license along
with this program if not see http www gnu org licenses
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license as published by
the free software foundation either version 2 of the license or at
your option any later version this program is distributed in the
hope that it will be useful but without any warranty without even
the implied warranty of merchantability or fitness for a particular
purpose see the gnu general public license for more details [based]
[from] [clk] [highbank] [c] you should have received a copy of the
gnu general public license along with this program if not see http
www gnu org licenses
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-or-later
has been chosen to replace the boilerplate/reference in 355 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Jilayne Lovejoy <opensource@jilayne.com>
Reviewed-by: Steve Winslow <swinslow@gmail.com>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190519154041.837383322@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Based on 1 normalized pattern(s):
licensed under gplv2 or later
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-or-later
has been chosen to replace the boilerplate/reference in 118 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Jilayne Lovejoy <opensource@jilayne.com>
Reviewed-by: Steve Winslow <swinslow@gmail.com>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190519154040.961286471@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Based on 2 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license as published by
the free software foundation either version 2 of the license or at
your option any later version this program is distributed in the
hope that it will be useful but without any warranty without even
the implied warranty of merchantability or fitness for a particular
purpose see the gnu general public license for more details you
should have received a copy of the gnu general public license along
with this program if not write to the free software foundation inc
51 franklin street fifth floor boston ma 02110 1301 usa
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license as published by
the free software foundation either version 2 of the license or at
your option [no]_[pad]_[ctrl] any later version this program is
distributed in the hope that it will be useful but without any
warranty without even the implied warranty of merchantability or
fitness for a particular purpose see the gnu general public license
for more details you should have received a copy of the gnu general
public license along with this program if not write to the free
software foundation inc 51 franklin street fifth floor boston ma
02110 1301 usa
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-or-later
has been chosen to replace the boilerplate/reference in 176 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Jilayne Lovejoy <opensource@jilayne.com>
Reviewed-by: Steve Winslow <swinslow@gmail.com>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190519154040.652910950@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
MPLL_5OM (the capital letter o) should indeed be MPLL_50M (the number)
Fix this before it gets used.
Fixes: 25db146aa7 ("dt-bindings: clk: meson: add g12a periph clock controller bindings")
Reported-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Pull thermal soc updates from Eduardo Valentin:
- thermal core has a new devm_* API for registering cooling devices. I
took the entire series, that is why you see changes on drivers/hwmon
in this pull (Guenter Roeck)
- rockchip thermal driver gains support to PX30 SoC (Elaine Zhang)
- the generic-adc thermal driver now considers the lookup table DT
property as optional (Jean-Francois Dagenais)
- Refactoring of tsens thermal driver (Amit Kucheria)
- Cleanups on cpu cooling driver (Daniel Lezcano)
- broadcom thermal driver dropped support to ACPI (Srinath Mannam)
- tegra thermal driver gains support to OC hw throttle and GPU throtle
(Wei Ni)
- Fixes in several thermal drivers.
* 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal: (59 commits)
hwmon: (pwm-fan) Use devm_thermal_of_cooling_device_register
hwmon: (npcm750-pwm-fan) Use devm_thermal_of_cooling_device_register
hwmon: (mlxreg-fan) Use devm_thermal_of_cooling_device_register
hwmon: (gpio-fan) Use devm_thermal_of_cooling_device_register
hwmon: (aspeed-pwm-tacho) Use devm_thermal_of_cooling_device_register
thermal: rcar_gen3_thermal: Fix to show correct trip points number
thermal: rcar_thermal: update calculation formula for R-Car Gen3 SoCs
thermal: cpu_cooling: Actually trace CPU load in thermal_power_cpu_get_power
thermal: rockchip: Support the PX30 SoC in thermal driver
dt-bindings: rockchip-thermal: Support the PX30 SoC compatible
thermal: rockchip: fix up the tsadc pinctrl setting error
thermal: broadcom: Remove ACPI support
thermal: Fix build error of missing devm_ioremap_resource on UM
thermal/drivers/cpu_cooling: Remove pointless field
thermal/drivers/cpu_cooling: Add Software Package Data Exchange (SPDX)
thermal/drivers/cpu_cooling: Fixup the header and copyright
thermal/drivers/cpu_cooling: Remove pointless test in power2state()
thermal: rcar_gen3_thermal: disable interrupt in .remove
thermal: rcar_gen3_thermal: fix interrupt type
thermal: Introduce devm_thermal_of_cooling_device_register
...
Add the bindings and the related documentation for the audio hdmitx
control glue of the Amlogic g12a SoC family
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
around because we've finally gotten around to fixing some long standing issues.
There's still work to do though, so this PR is largely laying down the
foundation for all the driver changes to come in the next merge window.
The first problem we're alleviating is how parents of clks are specified. With
the new method, we should see lots of drivers migrate away from the current
design of string comparisons on the entire clk tree to a more direct method
where they can use clk_hw pointers or more localized names specified in DT or
via clkdev. This should reduce our reliance on string comparisons for all the
topology description logic that we've been using for years and hopefully speed
some things up while avoiding problems we have with generating clk names.
Beyond that we also got rid of the CLK_IS_BASIC flag because it wasn't really
helping anyone and we introduced big-endian versions of the basic clk types so
that we can get rid of clk_{readl,writel}(). Both of these are things that
driver developers have tried to use over the years that I typically bat away
during code reviews because they're not useful. It's great to see these two
things go away so maintainers can save time not worrying about these things.
On the driver side we got the usual collection of new SoC support and
non-critical fixes and updates to existing code. The big topics that stand out
are the new driver support for Mediatek MT8183 and MT8516 SoCs, Amlogic Meson8b
and G12a SoCs, and the SiFive FU540 SoC. The other patches in the driver pile
are mostly fixes for things that are being used for the first time or additions
for clks that couldn't be tested before because there wasn't a consumer driver
that exercised them. Details are below and also in the sub-maintainer tags.
Core:
- Remove clk_readl() and introduce BE versions of basic clk types
- Rewrite how clk parents can be specified to allow DT/clkdev lookups
- Removal of the CLK_IS_BASIC clk flag
- Framework documentation updates and fixes
New Drivers:
- Support for STM32F769
- AT91 sam9x60 PMC support
- SiFive FU540 PRCI and PLL support
- Qualcomm QCS404 CDSP clk support
- Qualcomm QCS404 Turing clk support
- Mediatek MT8183 clock support
- Mediatek MT8516 clock support
- Milbeaut M10V clk controller support
- Support for Cirrus Logic Lochnagar clks
Updates:
- Rework AT91 sckc DT bindings
- Fix slow RC oscillator issue on sama5d3
- Mark UFS clk as critical on Hi-Silicon hi3660 SoCs
- Various static analysis fixes/finds and const markings
- Video Engine (ECLK) support on Aspeed SoCs
- Xilinx ZynqMP Versal platform support
- Convert Xilinx ZynqMP driver to be struct oriented
- Fixes for Rockchip rk3328 and rk3288 SoCs
- Sub-type for Rockchip SoCs where mux and divider aren't a single register
- Remove SNVS clock from i.MX7UPL clock driver and bindings
- Improve i.MX5 clock driver for i.MX50 support
- Addition of ADC clock definition for Exynos 5410 SoC (Odroid XU)
- Export a new clock for the MBUS controller on the A13
- Allwinner H6 fixes to support a finer clocking of the video and VPU engines
- Add g12a support in the Amlogic axg audio clock controller
- Add missing PCI USB clock on Rensas RZ/N1
- Add Z2 (Cortex-A53) clocks on Rensas R-Car E3 and RZ/G2E
- A new helper DIV64_U64_ROUND_CLOSEST() in <linux/math64.h>
- VPU and Video Decoder clocks on Amlogic Meson8b
- Finally remove the wrong ABP Meson8b clock id
- Add Video Decoder, PCIe PLL, and CPU Clocks on Amlogic G12A
- Re-expose SAR_ADC_SEL and CTS_OSCIN on Amlogic G12A AO clock controller
- Un-expose some Amlogic AXG-Audio input clocks IDs
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAlzUabQRHHNib3lkQGtl
cm5lbC5vcmcACgkQrQKIl8bklSUMmBAAr0WrvWa3s1Ue+lPfmehcAfeI2NkBPC/E
uhKD+vHBil/Aha33tFTPtVjsZiaMuUETNGPppEUUrHgu4K3UMJZl0iYql6XNVP77
OObIM5wqXoJ5Yv1e1G0p7X/Qztx7UxEtPwbXJ/9kNN2t6yzg4y8vD2cmXgV5KzHp
yRUDFNbH9JEyWFbrPhPjD3Bk1PCwdmXNFQg/uYk79g3c84js9MCbWvIqVEuU3vps
3/9lsDkhbp/flrSOA7D1eloQ6aPXdkLsFzDkJ+6mCA3zxsW/i2N38ZKVDTYG/5rx
USh3Z0Vyd0f9pKlQqwe1tyr2PBJrYWTtcPBSDcdr4BI1209xseFe4TaqHw1IRKcB
uYX0gtNTTcgx+8Znvp9y+hE8DhbVNpZvblZuab+rbfb/Gte2wC5/zvzEAz1EqPap
43VYdi3JR9iWGsC/r4+5OdVFRgWmXFsn5ysQRLkRgE41fKRn7joGHhPS5xDTI0l/
1rA/8Oh0GMAcSOQ0aSBtavmMCsyJJTjG7s6MpqiO5u/DHnb4MB1Jd0rEWNIjiVmJ
cqS8II+EbaLWZgt9r3W7ePhkfpHlLw+c4mwI9lRF7Zo67Rz9lrlt1l9YxPnJHewN
uTRn2ch5W90Jr289wymDNQZGGvCyr+nxKYlSd+kXjlH6poDn6bxYdKHgJexDYmZR
NVylbizS6lg=
=/uso
-----END PGP SIGNATURE-----
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk framework updates from Stephen Boyd:
"We have a couple new features and changes in the core clk framework
this time around because we've finally gotten around to fixing some
long standing issues. There's still work to do though, so this pull
request is largely laying down the foundation for all the driver
changes to come in the next merge window.
The first problem we're alleviating is how parents of clks are
specified. With the new method, we should see lots of drivers migrate
away from the current design of string comparisons on the entire clk
tree to a more direct method where they can use clk_hw pointers or
more localized names specified in DT or via clkdev. This should reduce
our reliance on string comparisons for all the topology description
logic that we've been using for years and hopefully speed some things
up while avoiding problems we have with generating clk names.
Beyond that we also got rid of the CLK_IS_BASIC flag because it wasn't
really helping anyone and we introduced big-endian versions of the
basic clk types so that we can get rid of clk_{readl,writel}(). Both
of these are things that driver developers have tried to use over the
years that I typically bat away during code reviews because they're
not useful. It's great to see these two things go away so maintainers
can save time not worrying about these things.
On the driver side we got the usual collection of new SoC support and
non-critical fixes and updates to existing code. The big topics that
stand out are the new driver support for Mediatek MT8183 and MT8516
SoCs, Amlogic Meson8b and G12a SoCs, and the SiFive FU540 SoC. The
other patches in the driver pile are mostly fixes for things that are
being used for the first time or additions for clks that couldn't be
tested before because there wasn't a consumer driver that exercised
them. Details are below and also in the sub-maintainer tags.
Core:
- Remove clk_readl() and introduce BE versions of basic clk types
- Rewrite how clk parents can be specified to allow DT/clkdev lookups
- Removal of the CLK_IS_BASIC clk flag
- Framework documentation updates and fixes
New Drivers:
- Support for STM32F769
- AT91 sam9x60 PMC support
- SiFive FU540 PRCI and PLL support
- Qualcomm QCS404 CDSP clk support
- Qualcomm QCS404 Turing clk support
- Mediatek MT8183 clock support
- Mediatek MT8516 clock support
- Milbeaut M10V clk controller support
- Support for Cirrus Logic Lochnagar clks
Updates:
- Rework AT91 sckc DT bindings
- Fix slow RC oscillator issue on sama5d3
- Mark UFS clk as critical on Hi-Silicon hi3660 SoCs
- Various static analysis fixes/finds and const markings
- Video Engine (ECLK) support on Aspeed SoCs
- Xilinx ZynqMP Versal platform support
- Convert Xilinx ZynqMP driver to be struct oriented
- Fixes for Rockchip rk3328 and rk3288 SoCs
- Sub-type for Rockchip SoCs where mux and divider aren't a single register
- Remove SNVS clock from i.MX7UPL clock driver and bindings
- Improve i.MX5 clock driver for i.MX50 support
- Addition of ADC clock definition for Exynos 5410 SoC (Odroid XU)
- Export a new clock for the MBUS controller on the A13
- Allwinner H6 fixes to support a finer clocking of the video and VPU engines
- Add g12a support in the Amlogic axg audio clock controller
- Add missing PCI USB clock on Rensas RZ/N1
- Add Z2 (Cortex-A53) clocks on Rensas R-Car E3 and RZ/G2E
- A new helper DIV64_U64_ROUND_CLOSEST() in <linux/math64.h>
- VPU and Video Decoder clocks on Amlogic Meson8b
- Finally remove the wrong ABP Meson8b clock id
- Add Video Decoder, PCIe PLL, and CPU Clocks on Amlogic G12A
- Re-expose SAR_ADC_SEL and CTS_OSCIN on Amlogic G12A AO clock controller
- Un-expose some Amlogic AXG-Audio input clocks IDs"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (172 commits)
clk: Cache core in clk_fetch_parent_index() without names
clk: imx: correct pfdv2 gate_bit/vld_bit operations
clk: sifive: add a driver for the SiFive FU540 PRCI IP block
clk: analogbits: add Wide-Range PLL library
clk: imx: clk-pllv3: mark expected switch fall-throughs
clk: imx8mq: Add dsi_ipg_div
clk: imx: pllv4: add fractional-N pll support
clk: sunxi-ng: Use the correct style for SPDX License Identifier
clk: sprd: Use the correct style for SPDX License Identifier
clk: renesas: Use the correct style for SPDX License Identifier
clk: qcom: Use the correct style for SPDX License Identifier
clk: davinci: Use the correct style for SPDX License Identifier
clk: actions: Use the correct style for SPDX License Identifier
clk: imx: keep uart clock on during system boot
clk: imx: correct i.MX7D AV PLL num/denom offset
dt-bindings: clk: add documentation for the SiFive PRCI driver
clk: stm32mp1: Add ddrperfm clock
clk: Remove CLK_IS_BASIC clk flag
clock: milbeaut: Add Milbeaut M10V clock controller
dt-bindings: clock: milbeaut: add Milbeaut clock description
...
Nex drivers:
- New driver for Bitmain BM1880 pin controller
- New driver for Mediatek MT8516
- New driver for Cirrus Logich Lochnagar PMIC pins
Updates:
- Incremental development on Renesas SH-PFC
- Incremental development on Intel pin controller and some
particular updates for Cedarfork.
- Pin configuration support in Allwinner SunXi drivers
- Suspend/resume support in the NXP/Freescale i.MX8MQ driver
- Support for more packaging of the ST Micro STM32
-----BEGIN PGP SIGNATURE-----
iQIcBAABAgAGBQJc0ouWAAoJEEEQszewGV1zGe0P/jo3cOjcU1pZ1KUMWOBPdh4p
7Ks3sjjDPpJ5JB8Vv9piXhlglZQMixh2PFsmsWYN35CP+4but1BJ9x2NqAOrKEnY
3IJcaXxjyYLyqMlYTCLNLHcMca1Ku9KcGHMX0/5JKpM84qfrOMQmjzv9RMC9UcFb
3AAZgDHKGdu6kqs6nm5l62z5bg+GKTzjuOZ+a+YsiOLHRHz2loGdP7egZy6VtmuQ
L1bFibfJX6Nexmh/TF0iceX82385aPfU8AMbxdhfMUEI3OJqR4gtSEVOxzW1FJaA
+Ursxeess7QiAyyStOTszccOsJJe6ZjThU25s5kVLPygx0+kv2Z94Vvyb+ii1yU+
UWk1zbOcYkd1mPAA6NGgzrpLgUUrL8Wzz45OwZKFxLWHjNRB2vDI6p8ABL+TRlXA
cHOSpszHbAh/oqEZ45WmqFC0S011xmniOSqHuGHxanKAYKQjdaxO/rHtWkrgsEAJ
NybpV67Ar2UtW2/3VqQHV97FcPzXoUMorn1qFs8aZeFxkqjnEMXP4zCgujLeJNn7
Aa8Q9pWAOspMaudD96BUNsbjavn8PLRtzkOGRtL/Hfzfnt03SDTHUcrlxrwQr1fq
dpw1bn2XIOjWwgzyrYXJhQAVOADuRks7wSVAP+/Vg2Gke8XmzAJ4x9tiLKDy7oyE
DReRSj47xF01ns2AY9Bu
=ovk5
-----END PGP SIGNATURE-----
Merge tag 'pinctrl-v5.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"It is pretty calm and chill in pin control for the moment. Just
incremental development.
There is an odd patch to the Super-H architecture, it's coming from
the maintainers so should be fine.
Summary:
New drivers:
- Bitmain BM1880 pin controller
- Mediatek MT8516
- Cirrus Logich Lochnagar PMIC pins
Updates:
- Incremental development on Renesas SH-PFC
- Incremental development on Intel pin controller and some particular
updates for Cedarfork.
- Pin configuration support in Allwinner SunXi drivers
- Suspend/resume support in the NXP/Freescale i.MX8MQ driver
- Support for more packaging of the ST Micro STM32"
* tag 'pinctrl-v5.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits)
pinctrl: mcp23s08: Do not complain about unsupported params
pinctrl: Rework Kconfig dependency for BM1880 pinctrl driver
MAINTAINERS: Add entry for BM1880 pinctrl
pinctrl: Add pinctrl support for BM1880 SoC
dt-bindings: pinctrl: Add BM1880 pinctrl binding
pinctrl: stm32: check irq controller availability at probe
pinctrl: mediatek: Add MT8516 Pinctrl driver
pinctrl: zte: fix leaked of_node references
pinctrl: intel: Increase readability of intel_gpio_update_pad_mode()
pinctrl: intel: Retain HOSTSW_OWN for requested gpio pin
pinctrl: pistachio: fix leaked of_node references
pinctrl: sunxi: Support I/O bias voltage setting on H6
pinctrl: sunxi: Prepare for alternative bias voltage setting methods
pinctrl: st: fix leaked of_node references
pinctrl: samsung: fix leaked of_node references
pinctrl: stm32: align stm32mp157 pin names
pinctrl: stm32: add package information for stm32mp157c
pinctrl: stm32: introduce package support
dt-bindings: pinctrl: stm32: add new entry for package information
pinctrl: imx8mq: Add suspend/resume ops
...
Here is the big set of USB and PHY driver patches for 5.2-rc1
There is the usual set of:
- USB gadget updates
- PHY driver updates and additions
- USB serial driver updates and fixes
- typec updates and new chips supported
- mtu3 driver updates
- xhci driver updates
- other tiny driver updates
Nothing really interesting, just constant forward progress.
All of these have been in linux-next for a while with no reported
issues. The usb-gadget and usb-serial trees were merged a bit "late",
but both of them had been in linux-next before they got merged here last
Friday.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-----BEGIN PGP SIGNATURE-----
iG0EABECAC0WIQT0tgzFv3jCIUoxPcsxR9QN2y37KQUCXNKuwg8cZ3JlZ0Brcm9h
aC5jb20ACgkQMUfUDdst+ymRUgCfa8Ri7KrCaBR5NHQcLhbdrX90ToQAmgNw7vpo
fqt0XpNM0CSa9O/gOr79
=8HFh
-----END PGP SIGNATURE-----
Merge tag 'usb-5.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
Pull USB/PHY updates from Greg KH:
"Here is the big set of USB and PHY driver patches for 5.2-rc1
There is the usual set of:
- USB gadget updates
- PHY driver updates and additions
- USB serial driver updates and fixes
- typec updates and new chips supported
- mtu3 driver updates
- xhci driver updates
- other tiny driver updates
Nothing really interesting, just constant forward progress.
All of these have been in linux-next for a while with no reported
issues. The usb-gadget and usb-serial trees were merged a bit "late",
but both of them had been in linux-next before they got merged here
last Friday"
* tag 'usb-5.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (206 commits)
USB: serial: f81232: implement break control
USB: serial: f81232: add high baud rate support
USB: serial: f81232: clear overrun flag
USB: serial: f81232: fix interrupt worker not stop
usb: dwc3: Rename DWC3_DCTL_LPM_ERRATA
usb: dwc3: Fix default lpm_nyet_threshold value
usb: dwc3: debug: Print GET_STATUS(device) tracepoint
usb: dwc3: Do core validation early on probe
usb: dwc3: gadget: Set lpm_capable
usb: gadget: atmel: tie wake lock to running clock
usb: gadget: atmel: support USB suspend
usb: gadget: atmel_usba_udc: simplify setting of interrupt-enabled mask
dwc2: gadget: Fix completed transfer size calculation in DDMA
usb: dwc2: Set lpm mode parameters depend on HW configuration
usb: dwc2: Fix channel disable flow
usb: dwc2: Set actual frame number for completed ISOC transfer
usb: gadget: do not use __constant_cpu_to_le16
usb: dwc2: gadget: Increase descriptors count for ISOC's
usb: introduce usb_ep_type_string() function
usb: dwc3: move synchronize_irq() out of the spinlock protected block
...
- Mark UFS clk as critical on Hi-Silicon hi3660 SoCs
- Support for Cirrus Logic Lochnagar clks
* clk-hisi:
clk: hi3660: Mark clk_gate_ufs_subsys as critical
* clk-lochnagar:
clk: lochnagar: Add support for the Cirrus Logic Lochnagar
clk: lochnagar: Add initial binding documentation
* clk-allwinner:
clk: sunxi-ng: sun5i: Export the MBUS clock
clk: sunxi-ng: a83t: Add pll-video0 as parent of csi-mclk
clk: sunxi-ng: h6: Allow video & vpu clocks to change parent rate
clk: sunxi-ng: h6: Preset hdmi-cec clock parent
clk: sunxi: Add Kconfig options
clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset
clk: sunxi-ng: Allow DE clock to set parent rate
* clk-rockchip:
clk: rockchip: undo several noc and special clocks as critical on rk3288
clk: rockchip: add a COMPOSITE_DIV_OFFSET clock-type
clk: rockchip: Turn on "aclk_dmac1" for suspend on rk3288
clk: rockchip: Limit use of USB PHY clock to USB on rk3288
clk: rockchip: Fix video codec clocks on rk3288
clk: rockchip: Make rkpwm a critical clock on rk3288
clk: rockchip: fix wrong clock definitions for rk3328
* clk-qoriq:
clk: qoriq: increase array size of cmux_to_group
dt-bindings: qoriq-clock: Add ls1028a chip compatible string
clk: qoriq: Add ls1028a clock configuration
clk: qoriq: add more PLL divider clocks support
dt-bindings: qoriq-clock: add more PLL divider clocks support
- Remove clk_readl() and introduce BE versions of basic clk types
* clk-doc:
clk: Drop duplicate clk_register() documentation
clk: Document and simplify clk_core_get_rate_nolock()
clk: Remove 'flags' member of struct clk_fixed_rate
clk: nxp: Drop 'flags' on fixed_rate clk macro
clk: Document __clk_mux_determine_rate()
clk: Document CLK_MUX_READ_ONLY mux flag
clk: Document deprecated things
clk: Collapse gpio clk kerneldoc
* clk-more-critical:
clk: highbank: Convert to CLK_IS_CRITICAL
* clk-meson: (21 commits)
clk: meson: axg-audio: add g12a support
clk: meson: axg-audio: don't register inputs in the onecell data
clk: meson: axg_audio: replace prefix axg by aud
dt-bindings: clk: axg-audio: add g12a support
clk: meson: meson8b: add the video decoder clock trees
clk: meson: meson8b: add the VPU clock trees
clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2
clk: meson: meson8b: use a separate clock table for Meson8m2
dt-bindings: clock: meson8b: export the video decoder clocks
clk: meson-g12a: add video decoder clocks
dt-bindings: clock: meson8b: export the VPU clock
clk: meson-g12a: add PCIE PLL clocks
dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCIN
clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLL
dt-bindings: clock: meson8b: drop the "ABP" clock definition
clk: meson: g12a: add cpu clocks
dt-bindings: clk: g12a-clkc: add VDEC clock IDs
dt-bindings: clock: axg-audio: unexpose controller inputs
dt-bindings: clk: g12a-clkc: add PCIE PLL clock ID
clk: g12a-aoclk: re-export CLKID_AO_SAR_ADC_SEL clock id
...
* clk-basic-be:
clk: core: replace clk_{readl,writel} with {readl,writel}
clk: core: remove powerpc special handling
powerpc/512x: mark clocks as big endian
clk: mux: add explicit big endian support
clk: multiplier: add explicit big endian support
clk: gate: add explicit big endian support
clk: fractional-divider: add explicit big endian support
clk: divider: add explicit big endian support
We need this to make the usb-gadget branch merge cleaner. And for
testing to keep from hitting the same issues already fixed.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This series of changes adds a new pinmux instance defines for am335x,
and a new AM33XX_PADCONF macro. And then the rest of the series updates
the dts files to use it.
The reasons for doing this is the pinmux configuration has been hard to
use and read. And we need to do this for eventually for moving to use
values.
This change is done one machine at a time, and can be easily reverted
as needed in case of unexpected trouble. The old macro is still working,
and we're planning to keep it around until we eventually change to use
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAly18IoRHHRvbnlAYXRv
bWlkZS5jb20ACgkQG9Q+yVyrpXPwQA//ajq5abErjoCtPQrf/4bv9NdZQcBkRaHa
k4pZ8hgWvLQYzNDZirQhe174UUCUUIdc7yppRYzgjqYmWLvNHSs4ax9SeBKn1bHd
40gZMzmJeHByRNjK1WHHUBLXtuMRIbOk7k4Lcgqi3en1a9jHnJaq0h/Xde69nrWz
rjcewWEbZeqYvIRZJDv17vbY3DY6gebP3DQzKLEX89vTfMJF0vgTm6YVskhW1Jtx
3Coj/M5e3//gDRBD8bpLdOac1irQe2+MMFMh4GH9ctF9/ZK45cXKz3p8j+em0YgJ
yYXimAFqVY0lQuFNC6L/PfsQ8YDSuVTHqTS6vajZvqoDB4wMsYjw8ivag5S0NpqV
baaft1SyQ1x7YeuKny/jSZ+1vYIe2Omms45Dc3JYLX2EltLDDEzriPpohIcqetOp
XJfxAEFbAU9Mk1tMSS8hvpoj9ezodQz3tYS8Mwc15Dg2SDfT7yya1kDowOpVa9sn
MKvFZ5jIfYdq3es/vDm9sa0qunmQBX1iM5Jzp1u+GUYa5p7kTcojCd++FoR7/do5
R2V96N8NaxUTATCEpMCxCJsSYeQrc4ZmnUWBHRVntQJrPxolTwRpH3yEWMBFN4l1
7XU56mEkDzXQMnHJbrzOyNWa/iAmYqUJXU9WbvrmMOv3ZMro7NqIl5mD46XkBBBK
8BzayzP1QRg=
=QimO
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v5.2/dt-am3-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt
Add am335x pinmux defines and start using them
This series of changes adds a new pinmux instance defines for am335x,
and a new AM33XX_PADCONF macro. And then the rest of the series updates
the dts files to use it.
The reasons for doing this is the pinmux configuration has been hard to
use and read. And we need to do this for eventually for moving to use
values.
This change is done one machine at a time, and can be easily reverted
as needed in case of unexpected trouble. The old macro is still working,
and we're planning to keep it around until we eventually change to use
* tag 'omap-for-v5.2/dt-am3-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (38 commits)
ARM: dts: am335x: wega: Replaced register offsets with defines
ARM: dts: am335x: sl50: Replaced register offsets with defines
ARM: dts: am335x: shc: Replaced register offsets with defines
ARM: dts: am335x: sbc-t335: Replaced register offsets with defines
ARM: dts: am335x: sancloud-bbe: Replaced register offsets with defines
ARM: dts: am335x: phycore-som: Replaced register offsets with defines
ARM: dts: am335x: pepper: Replaced register offsets with defines
ARM: dts: am335x: pdu001: Replaced register offsets with defines
ARM: dts: am335x: pcm-953: Replaced register offsets with defines
ARM: dts: am335x: osd335x-common: Replaced register offsets with defines
ARM: dts: am335x: osd3358-sm-red: Replaced register offsets with defines
ARM: dts: am335x: nano: Replaced register offsets with defines
ARM: dts: am335x: moxa-uc-8100-me-t: Replaced register offsets with defines
ARM: dts: am335x: moxa-uc-2101: Replaced register offsets with defines
ARM: dts: am335x: moxa-uc-2100-common: Replaced register offsets with defines
ARM: dts: am335x: lxm: Replaced register offsets with defines
ARM: dts: am335x: igep0033: Replaced register offsets with defines
ARM: dts: am335x: icev2: Replaced register offsets with defines
ARM: dts: am335x: evmsk: Replaced register offsets with defines
ARM: dts: am335x: evm: Replaced register offsets with defines
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Add binding documentation of apmixedsys for MT8516 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add binding documentation of infracfg for MT8516 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add binding documentation of topckgen for MT8516 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
STM32F769 clocks are derived from STM32746 clocks.
main differences are:
- new source clock for SAI1 and SAI2 (HSI or HSE)
- Add DFSDM & DSI clocks
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
AM654x has two SERDES instances. Each instance has three input clocks
(left input, externel reference clock and right input) and two output
clocks (left output and right output) in addition to a PLL mux clock
which the SERDES uses for Clock Multiplier Unit (CMU refclock).
The PLL mux clock can select from one of the three input clocks.
The right output can select between left input and external reference
clock while the left output can select between the right input and
external reference clock.
The left and right input reference clock of SERDES0 and SERDES1
respectively are connected to the SoC clock. In the case of two lane
SERDES personality card, the left input of SERDES1 is connected to
the right output of SERDES0 in a chained fashion.
See section "Reference Clock Distribution" of AM65x Sitara Processors
TRM (SPRUID7 – April 2018) for more details.
Add dt-binding documentation in order to represent all these different
configurations in device tree.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Add macro for the UDC PHY clock of the JZ4725B.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add devicetree binding for the turing clock controller found in QCS404.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add the clocks and resets need in order to control the Turing
remoteproc.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add MT8183 clock dt-bindings, include topckgen, apmixedsys,
infracfg, mcucfg and subsystem clocks.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The MBUS clock is used by the MBUS controller, so let's export it so that
we can use it in our DT node.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Add preprocessor macros for the important PRCI output clocks
that are needed by both the FU540 PRCI driver and DT data.
Details are available in the FU540 manual in Chapter 7 of
https://static.dev.sifive.com/FU540-C000-v1.0.pdf
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Olof Johansson