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2 Commits

Author SHA1 Message Date
Eugen Hristev db2f44820a clk: at91: sam9x60-pll: adapt PMC_PLL_ACR default value 
Product datasheet recommends different values for UPLL and PLLA analog control
register.
Adapt accordingly.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Link: https://lkml.kernel.org/r/1573478913-19737-1-git-send-email-eugen.hristev@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-01-05 19:06:31 -08:00
Alexandre Belloni a436c2a447 clk: at91: add sam9x60 PLL driver 
The PLLs on the sam9x60 (PLLA and USB PLL) use a different register set and
programming model than the previous SoCs.

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-04-25 12:34:06 -07:00