Commit Graph

200 Commits

Author SHA1 Message Date
Andrzej Hajda fee3103ac3 clk: sunxi: fix handling return value of of_property_match_string
The function can return negative values, so its result should
be assigned to signed variable.

The problem has been detected using proposed semantic patch
scripts/coccinelle/tests/assign_signed_to_unsigned.cocci [1].

[1]: http://permalink.gmane.org/gmane.linux.kernel/2046107

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-12-14 13:54:11 +01:00
Dan Carpenter b1558f168f clk: sunxi: signedness bug in sun8i_h3_bus_gates_init()
"index" needs to be signed for the error handling to work.

Fixes: ab6e23a4e3 ('clk: sunxi: Add H3 clocks support')
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-12-13 22:07:49 +01:00
Chen-Yu Tsai fd9ffd8be0 clk: sunxi: Add CLK_OF_DECLARE support for sun8i-a23-apb0-clk driver
The APBS clock on sun9i is the same as the APB0 clock on sun8i. With
sun9i we are supporting the PRCM clocks by using CLK_OF_DECLARE,
instead of through a PRCM mfd device and subdevices for each clock
and reset control. As such we need a CLK_OF_DECLARE version of
the sun8i-a23-apb0-clk driver.

Also, build it for sun9i/A80, and not just for configurations with
MFD_SUN6I_PRCM enabled.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-12-09 10:17:22 +01:00
Chen-Yu Tsai 3cdd9f5c49 clk: sunxi: Add VE (Video Engine) module clock driver for sun[457]i
The video engine has its own special module clock, consisting of a clock
gate, configurable dividers, and a reset control.

On later (sun[68]i) families, the reset control is moved out of this
piece of hardware and grouped with reset controls of other peripherals.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-12-08 11:05:27 +01:00
Jens Kuske ab6e23a4e3 clk: sunxi: Add H3 clocks support
The H3 clock control unit is similar to the those of other sun8i family
members like the A23.

It adds a new bus gates clock similar to the simple gates, but with a
different parent clock for each single gate.
Some of the gates use the new AHB2 clock as parent, whose clock source
is muxable between AHB1 and PLL6/2. The documentation isn't totally clear
about which devices belong to AHB2 now, especially USB EHIC/OHIC, so it
is mostly based on Allwinner kernel source code.

Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-12-08 09:11:53 +01:00
Chen-Yu Tsai 6d3a47c291 clk: sunxi: Add DRAM gates support for sun4i-a10
The A10/A20 share the same set of DRAM clock gates, which controls
direct memory access for some peripherals.

On the A10, bit 15 controls the system's DRAM clock output (possibly
to the DRAM chips), which we need to keep on.

On the A20 this has been moved to the DRAM controller, becoming a no-op.
However it is still listed in the user manual, so add it anyway.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-12-07 09:58:17 +01:00
Maxime Ripard 59f0ec231f clk: sunxi: pll2: Fix clock running too fast
Contrary to what the datasheet says, the pre divider doesn't seem to be
incremented by one in the PLL2, but just uses the value from the register,
with 0 being a bypass.

This fixes the audio playing too fast.

Since we now have the same pre-divider flags, and the only difference with
the A10 is the post-divider offset, also remove the structure to just pass
the offset as an argument.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Fixes: eb662f8547 ("clk: sunxi: pll2: Add A13 support")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-12-02 23:27:47 -08:00
Chen-Yu Tsai 77d16e2c66 clk: sunxi: Add sun9i A80 cpus (cpu special) clock support
The "cpus" clock is the clock for the embedded processor in the A80.
It is also part of the PRCM clock tree. This clock includes a pre-
divider on one of its inputs. For now we are using a custom clock
driver for it. In the future we may want to develop a generalized
driver for these types of clocks, which also includes the AHB clock
driver on sun[5678]i.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-12-01 14:06:47 +01:00
Chen-Yu Tsai bfcba2ed83 clk: sunxi: Add sun9i A80 apbs gates support
This patch adds support for the PRCM apbs clock gates found on the
Allwinner A80 SoC.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-12-01 12:15:47 +01:00
Reinder de Haan 7bec0200ac clk: sunxi: Add support for the H3 usb phy clocks
The H3 has a usb-phy clk register which is similar to that of earlier
SoCs, but with support for a larger number of phys. So we can simply add
a new set of clk-data and a new compatible and be done with it.

Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Reinder de Haan <patchesrdh@mveas.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-11-20 13:50:19 +01:00
Linus Torvalds 56e0464980 ARM: SoC platform updates for v4.4
New and/or improved SoC support for this release:
 
  - Marvell Berlin:
    * Enable standard DT-based cpufreq
    * Add CPU hotplug support
  - Freescale:
    * Ethernet init for i.MX7D
    * Suspend/resume support for i.MX6UL
  - Allwinner:
    * Support for R8 chipset (used on NTC's $9 C.H.I.P board)
  - Mediatek:
    * SMP support for some platforms
  - Uniphier:
    * L2 support
    * Cleaned up SMP support, etc.
 
 + A handful of other patches around above functionality, and a few other
 smaller changes.
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Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC platform updates from Olof Johansson:
 "New and/or improved SoC support for this release:

  Marvell Berlin:
     - Enable standard DT-based cpufreq
     - Add CPU hotplug support

  Freescale:
     - Ethernet init for i.MX7D
     - Suspend/resume support for i.MX6UL

  Allwinner:
     - Support for R8 chipset (used on NTC's $9 C.H.I.P board)

  Mediatek:
     - SMP support for some platforms

  Uniphier:
     - L2 support
     - Cleaned up SMP support, etc.

  plus a handful of other patches around above functionality, and a few
  other smaller changes"

* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (42 commits)
  ARM: uniphier: rework SMP operations to use trampoline code
  ARM: uniphier: add outer cache support
  Documentation: EXYNOS: Update bootloader interface on exynos542x
  ARM: mvebu: add broken-idle option
  ARM: orion5x: use mac_pton() helper
  ARM: at91: pm: at91_pm_suspend_in_sram() must be 8-byte aligned
  ARM: sunxi: Add R8 support
  ARM: digicolor: select pinctrl/gpio driver
  arm: berlin: add CPU hotplug support
  arm: berlin: use non-self-cleared reset register to reset cpu
  ARM: mediatek: add smp bringup code
  ARM: mediatek: enable gpt6 on boot up to make arch timer working
  soc: mediatek: Fix random hang up issue while kernel init
  soc: ti: qmss: make acc queue support optional in the driver
  soc: ti: add firmware file name as part of the driver
  Documentation: dt: soc: Add description for knav qmss driver
  ARM: S3C64XX: Use PWM lookup table for mach-smartq
  ARM: S3C64XX: Use PWM lookup table for mach-hmt
  ARM: S3C64XX: Use PWM lookup table for mach-crag6410
  ARM: S3C64XX: Use PWM lookup table for smdk6410
  ...
2015-11-10 14:56:23 -08:00
Stephen Boyd 938ce30e29 Allwinner clock additions for 4.4
- Support for the Audio PLL and child clocks
   - Support for the A33 AHB gates
   - New clk-multiplier generic driver
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Merge tag 'sunxi-clocks-for-4.4' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next

Pull Allwinner clock additions for 4.4 from Maxime Ripard:

  - Support for the Audio PLL and child clocks
  - Support for the A33 AHB gates
  - New clk-multiplier generic driver

* tag 'sunxi-clocks-for-4.4' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
  clk: sunxi: mod1 clock support
  clk: sunxi: codec clock support
  clk: sunxi: pll2: Add A13 support
  clk: sunxi: Add a driver for the PLL2
  clk: Add a basic multiplier clock
  clk: sunxi: Add A33 gates support
2015-10-21 16:29:03 -07:00
Emilio López 9b038bc58a clk: sunxi: mod1 clock support
The module 1 type of clocks consist of a gate and a mux and are used on
the audio blocks to mux and gate the PLL2 outputs for AC97, IIS or
SPDIF. This commit adds support for them on the sunxi clock driver.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
2015-10-21 21:51:29 +02:00
Emilio López e2771545f4 clk: sunxi: codec clock support
The codec clock on sun4i, sun5i and sun7i is a simple gate with PLL2 as
parent. Add a driver for such a clock.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
2015-10-21 21:51:28 +02:00
Maxime Ripard eb662f8547 clk: sunxi: pll2: Add A13 support
The A13, unlike the A10 and A20, doesn't use a pass-through exception for
the 0 value in the pre and post dividers, but increments all the values
written in the register by one.

Add an exception for both these cases to handle them nicely.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
2015-10-21 21:51:28 +02:00
Maxime Ripard 460d0d4448 clk: sunxi: Add a driver for the PLL2
The PLL2 on the A10 and later SoCs is the clock used for all the audio
related operations.

This clock has a somewhat complex output tree, with three outputs (2X, 4X
and 8X) with a fixed divider from the base clock, and an output (1X) with a
post divider.

However, we can simplify things since the 1X divider can be fixed, and we
end up by having a base clock not exposed to any device (or at least
directly, since the 4X output doesn't have any divider), and 4 fixed
divider clocks that will be exposed.

This clock seems to have been introduced, at least in this form, in the
revision B of the A10, but we don't have any information on the clock used
on the revision A.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
2015-10-21 21:51:27 +02:00
Maxime Ripard bef6229f36 ARM: sunxi: Add R8 support
The R8 is a new Allwinner SoC based on the A13. While both are very
similar, there's still a few differences. Introduce a new compatible to
deal with them.

In order to have a consistent naming, instead of mentioning the Allwinner
A series as the machine name, switch to sun4i/sun5i like what is done for
the other families.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-17 18:47:28 +02:00
Maxime Ripard 7d6ddad659 clk: sunxi: Add A33 gates support
The A33 gates are different from the A23 ones, add a new hook to simple
gates to handle this clock

Reported-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-09-18 22:02:17 +02:00
Luis de Bethencourt 051ace1020 clk: sunxi: sun9i-mmc: Fix module autoload for OF platform driver
This platform driver has a OF device ID table but the OF module
alias information is not created so module autoloading won't work.

Signed-off-by: Luis de Bethencourt <luis@debethencourt.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-09-16 15:22:31 -07:00
Luis de Bethencourt 6ed5f8e45d clk: sunxi: sun8i-apb0: Fix module autoload for OF platform driver
This platform driver has a OF device ID table but the OF module
alias information is not created so module autoloading won't work.

Signed-off-by: Luis de Bethencourt <luis@debethencourt.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-09-16 15:22:29 -07:00
Luis de Bethencourt ad915483e3 clk: sunxi: sun6i-ar100: Fix module autoload for OF platform driver
This platform driver has a OF device ID table but the OF module
alias information is not created so module autoloading won't work.

Signed-off-by: Luis de Bethencourt <luis@debethencourt.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-09-16 15:22:27 -07:00
Luis de Bethencourt f01745f640 clk: sunxi: sun6i-apb0-gates: Fix module autoload for OF platform driver
This platform driver has a OF device ID table but the OF module
alias information is not created so module autoloading won't work.

Signed-off-by: Luis de Bethencourt <luis@debethencourt.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-09-16 15:22:25 -07:00
Luis de Bethencourt 6853012116 clk: sunxi: sun6i-apb0: Fix module autoload for OF platform driver
This platform driver has a OF device ID table but the OF module
alias information is not created so module autoloading won't work.

Signed-off-by: Luis de Bethencourt <luis@debethencourt.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-09-16 15:22:23 -07:00
Linus Torvalds f36fc04e4c The clk framework changes for 4.3 are mostly updates to existing drivers
and the addition of new clock drivers. Stephen Boyd has also done a lot
 of subsystem-wide driver clean-ups (thanks!). There are also fixes to
 the framework core and changes to better split clock provider drivers
 from clock consumer drivers.
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Merge tag 'clk-for-linus-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Michael Turquette:
 "The clk framework changes for 4.3 are mostly updates to existing
  drivers and the addition of new clock drivers.  Stephen Boyd has also
  done a lot of subsystem-wide driver clean-ups (thanks!).  There are
  also fixes to the framework core and changes to better split clock
  provider drivers from clock consumer drivers"

* tag 'clk-for-linus-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (227 commits)
  clk: s5pv210: add missing call to samsung_clk_of_add_provider()
  clk: pistachio: correct critical clock list
  clk: pistachio: Fix PLL rate calculation in integer mode
  clk: pistachio: Fix override of clk-pll settings from boot loader
  clk: pistachio: Fix 32bit integer overflows
  clk: tegra: Fix some static checker problems
  clk: qcom: Fix MSM8916 prng clock enable bit
  clk: Add missing header for 'bool' definition to clk-conf.h
  drivers/clk: appropriate __init annotation for const data
  clk: rockchip: register pll mux before pll itself
  clk: add bindings for the Ux500 clocks
  clk/ARM: move Ux500 PRCC bases to the device tree
  clk: remove duplicated code with __clk_set_parent_after
  clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)
  clk: Constify clk_hw argument to provider APIs
  clk: Hi6220: add stub clock driver
  dt-bindings: clk: Hi6220: Document stub clock driver
  dt-bindings: arm: Hi6220: add doc for SRAM controller
  clk: atlas7: fix pll missed divide NR in fraction mode
  clk: atlas7: fix bit field and its root clk for coresight_tpiu
  ...
2015-08-31 17:26:48 -07:00
Stephen Boyd 1b14afa64d clk: sunxi: Convert to clk_hw based provider APIs
We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.

Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: "Emilio López" <emilio@elopez.com.ar>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-24 16:48:56 -07:00
Stephen Boyd 98d8a60ecc clk: Convert __clk_get_flags() to clk_hw_get_flags()
Mostly converted with the following snippet:

@@
struct clk_hw *E;
@@

-__clk_get_flags(E->clk)
+clk_hw_get_flags(E)

Acked-by: Tero Kristo <t-kristo@ti.com>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Daniel Thompson <daniel.thompson@linaro.org>
Cc: Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-24 16:48:44 -07:00
Stephen Boyd 497295afb5 clk: Replace __clk_get_num_parents with clk_hw_get_num_parents()
Mostly converted with the following semantic patch:

@@
struct clk_hw *E;
@@

-__clk_get_num_parents(E->clk)
+clk_hw_get_num_parents(E)

Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: Chao Xie <chao.xie@marvell.com>
Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: "Emilio López" <emilio@elopez.com.ar>
Acked-by: Tero Kristo <t-kristo@ti.com>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-24 16:48:43 -07:00
Maxime Ripard ee38b2698a clk: sunxi: Add a simple gates driver
The gates were handled with a common piece of framework that was
registering all gates array, that was not using the CLK_OF_DECLARE logic,
and was not using clock-indices but some private masks that were pretty
much equivalent.

Move this code in a new driver that handles all the gates array and solves
both these issues.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
[sboyd@codeaurora.org: Include clk.h for consumer API usage]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-12 00:59:15 -07:00
Stephen Boyd 9cfad9bc47 Merge branch 'cleanup-clk-h-includes' into clk-next
* cleanup-clk-h-includes: (62 commits)
  clk: Remove clk.h from clk-provider.h
  clk: h8300: Remove clk.h and clkdev.h includes
  clk: at91: Include clk.h and slab.h
  clk: ti: Switch clk-provider.h include to clk.h
  clk: pistachio: Include clk.h
  clk: ingenic: Include clk.h
  clk: si570: Include clk.h
  clk: moxart: Include clk.h
  clk: cdce925: Include clk.h
  clk: Include clk.h in clk.c
  clk: zynq: Include clk.h
  clk: ti: Include clk.h
  clk: sunxi: Include clk.h and remove unused clkdev.h includes
  clk: st: Include clk.h
  clk: qcom: Include clk.h
  clk: highbank: Include clk.h
  clk: bcm: Include clk.h
  clk: versatile: Remove clk.h and clkdev.h includes
  clk: ux500: Remove clk.h and clkdev.h includes
  clk: tegra: Properly include clk.h
  ...
2015-07-28 11:59:09 -07:00
Dinh Nguyen 8a53fb2bce clk: sunxi: make use of of_clk_parent_fill helper function
Use of_clk_parent_fill to fill in the parent clock names' array.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: "Emilio López" <emilio@elopez.com.ar>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28 11:59:05 -07:00
Boris Brezillon 57d866e606 clk: fix some determine_rate implementations
Some determine_rate implementations are not returning an error
when they failed to adapt the rate according to the rate request.
Fix them so that they return an error instead of silently
returning 0.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
CC: Jonathan Corbet <corbet@lwn.net>
CC: Tony Lindgren <tony@atomide.com>
CC: Ralf Baechle <ralf@linux-mips.org>
CC: "Emilio López" <emilio@elopez.com.ar>
CC: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Tero Kristo <t-kristo@ti.com>
CC: Peter De Schrijver <pdeschrijver@nvidia.com>
CC: Prashant Gaikwad <pgaikwad@nvidia.com>
CC: Stephen Warren <swarren@wwwdotorg.org>
CC: Thierry Reding <thierry.reding@gmail.com>
CC: Alexandre Courbot <gnurou@gmail.com>
CC: linux-doc@vger.kernel.org
CC: linux-kernel@vger.kernel.org
CC: linux-arm-kernel@lists.infradead.org
CC: linux-omap@vger.kernel.org
CC: linux-mips@linux-mips.org
CC: linux-tegra@vger.kernel.org
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-27 18:13:32 -07:00
Boris Brezillon 0817b62cc0 clk: change clk_ops' ->determine_rate() prototype
Clock rates are stored in an unsigned long field, but ->determine_rate()
(which returns a rounded rate from a requested one) returns a long
value (errors are reported using negative error codes), which can lead
to long overflow if the clock rate exceed 2Ghz.

Change ->determine_rate() prototype to return 0 or an error code, and pass
a pointer to a clk_rate_request structure containing the expected target
rate and the rate constraints imposed by clk users.

The clk_rate_request structure might be extended in the future to contain
other kind of constraints like the rounding policy, the maximum clock
inaccuracy or other things that are not yet supported by the CCF
(power consumption constraints ?).

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
CC: Jonathan Corbet <corbet@lwn.net>
CC: Tony Lindgren <tony@atomide.com>
CC: Ralf Baechle <ralf@linux-mips.org>
CC: "Emilio López" <emilio@elopez.com.ar>
CC: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
CC: Peter De Schrijver <pdeschrijver@nvidia.com>
CC: Prashant Gaikwad <pgaikwad@nvidia.com>
CC: Stephen Warren <swarren@wwwdotorg.org>
CC: Thierry Reding <thierry.reding@gmail.com>
CC: Alexandre Courbot <gnurou@gmail.com>
CC: linux-doc@vger.kernel.org
CC: linux-kernel@vger.kernel.org
CC: linux-arm-kernel@lists.infradead.org
CC: linux-omap@vger.kernel.org
CC: linux-mips@linux-mips.org
CC: linux-tegra@vger.kernel.org
[sboyd@codeaurora.org: Fix parent dereference problem in
__clk_determine_rate()]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Tested-by: Romain Perier <romain.perier@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[sboyd@codeaurora.org: Folded in fix from Heiko for fixed-rate
clocks without parents or a rate determining op]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-27 18:12:01 -07:00
Stephen Boyd 9dfefe8c76 clk: sunxi: Include clk.h and remove unused clkdev.h includes
This clock provider uses the consumer API, so include clk.h
explicitly. Also remove clkdev.h in files that aren't using it
and include slab.h when clkdev.h was being used to implicitly
include it.

Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-20 11:11:26 -07:00
Kevin Hilman d024bae2c4 Allwinner late changes for 4.2
A bunch of defconfig changes, and some patches to make the Allwinner H3 and
 A33 boot properly.
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Merge tag 'sunxi-late-for-4.2' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into fixes

Merge "Allwinner late changes for 4.2" from Maxime Ripard:

Allwinner late changes for 4.2

A bunch of defconfig changes, and some patches to make the Allwinner H3 and
A33 boot properly.

* tag 'sunxi-late-for-4.2' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
  ARM: sunxi: Enable simplefb in the defconfig
  ARM: Remove deprecated symbol from defconfig files
  ARM: sunxi: Add Machine support for A33
  ARM: sunxi: Introduce Allwinner H3 support
  Documentation: sunxi: Update Allwinner SoC documentation
2015-07-09 15:08:44 -07:00
Vishnu Patekar 159870d241 ARM: sunxi: Add Machine support for A33
Add machine support for the Allwinner A33 quad core cortex-a7 based SoC,
which is similar to the A23 SoC.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Chen-Yu Tsai <wens@csie.org>
2015-07-05 16:33:55 +02:00
Linus Torvalds 75462c8a87 Replace module_platform_driver with builtin_platform driver in non modules.
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Merge tag 'module-builtin_driver-v4.1-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/paulg/linux

Pull module_platform_driver replacement from Paul Gortmaker:
 "Replace module_platform_driver with builtin_platform driver in non
  modules.

  We see an increasing number of non-modular drivers using
  modular_driver() type register functions.  There are several downsides
  to letting this continue unchecked:

   - The code can appear modular to a reader of the code, and they won't
     know if the code really is modular without checking the Makefile
     and Kconfig to see if compilation is governed by a bool or
     tristate.

   - Coders of drivers may be tempted to code up an __exit function that
     is never used, just in order to satisfy the required three args of
     the modular registration function.

   - Non-modular code ends up including the <module.h> which increases
     CPP overhead that they don't need.

   - It hinders us from performing better separation of the module init
     code and the generic init code.

  So here we introduce similar macros for builtin drivers.  Then we
  convert builtin drivers (controlled by a bool Kconfig) by making the
  following type of mapping:

    module_platform_driver()       --->  builtin_platform_driver()
    module_platform_driver_probe() --->  builtin_platform_driver_probe().

  The set of drivers that are converted here are just the ones that
  showed up as relying on an implicit include of <module.h> during a
  pending header cleanup.  So we convert them here vs adding an include
  of <module.h> to non-modular code to avoid compile fails.  Additonal
  conversions can be done asynchronously at any time.

  Once again, an unused module_exit function that is removed here
  appears in the diffstat as an outlier wrt all the other changes"

* tag 'module-builtin_driver-v4.1-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/paulg/linux:
  drivers/clk: convert sunxi/clk-mod0.c to use builtin_platform_driver
  drivers/power: Convert non-modular syscon-reboot to use builtin_platform_driver
  drivers/soc: Convert non-modular soc-realview to use builtin_platform_driver
  drivers/soc: Convert non-modular tegra/pmc to use builtin_platform_driver
  drivers/cpufreq: Convert non-modular s5pv210-cpufreq.c to use builtin_platform_driver
  drivers/cpuidle: Convert non-modular drivers to use builtin_platform_driver
  drivers/platform: Convert non-modular pdev_bus to use builtin_platform_driver
  platform_device: better support builtin boilerplate avoidance
2015-07-02 10:42:13 -07:00
Paul Gortmaker 77459a0fec drivers/clk: convert sunxi/clk-mod0.c to use builtin_platform_driver
This driver builds based on obj-y and hence will not ever be
modular.  Change it to use the non-modular registration so that it
won't suffer a compile fail once a header move places the modular
registration within the module.h file.

Cc: "Emilio López" <emilio@elopez.com.ar>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: linux-clk@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16 14:12:39 -04:00
Hans de Goede ec80749dfd clk: sunxi: Add support for the usb-clk on sun8i a23 and a33 SoCs
The usb-clk on sun8i a23 and a33 SoCs is similar to the ones found
on sun6i-a31 SoCs but instead of a 3th phy the a23 / a33 have a hsic
interface which gets enabled by almost the same bits as used on
the a31 for the 3rd phy, but not exactly the same bits so we need
a new compatible for this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
2015-06-02 10:24:39 +02:00
Maxime Ripard 5ac382c311 clk: sunxi: Fix of_io_request_and_map error check
of_io_request_and map returns an error pointer, but the current code assumes
that on error the returned pointer will be NULL.

Obviously, that makes the check completely useless. Change the test to actually
check for the proper error code.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org
2015-05-05 17:43:57 +02:00
Chen-Yu Tsai f101796966 clk: sunxi: Add pll6 / 4 clock output to sun4i-a10-pll6
The pll6 has a /4 output that is used as an input to the ahb mux clock.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-03-25 11:46:41 -07:00
Chen-Yu Tsai 934fe5f48a clk: sunxi: Make divs clocks specify which output is the base factor clock
The current sunxi clock driver has the base factor clock of divs clocks
as the last clock output of the clock node. This makes it rather difficult
to add new outputs, such as fixed dividers, which were previously unknown.

This patch makes the divs clocks data structure specify which output is
the factor clock, and updates all current divs clocks accordingly.

We can then add new outputs after the factor clocks, at least not breaking
backward compatibility with regards to the devicetree bindings.

Also replace kzalloc with kcalloc in sunxi_divs_clk_setup().

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-03-25 11:46:32 -07:00
Chen-Yu Tsai b712a623bd clk: sunxi: Register divs clocks before factor clocks
We want to reparent AHB clock to PLL6 on sun5i/sun7i using the assigned
clocks properties. AHB is a factor clock, while PLL6 is a divs clock.

Register divs clocks before factor clocks so reparenting works. This
is only needed because we do the reparenting on the clock provider.

The proper way to fix this is to split out all the old sunxi clocks
into separate CLK_OF_DECLARE statements, like we are doing for sun9i.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-03-21 11:49:57 +01:00
Chen-Yu Tsai 946fd40f28 clk: sunxi: Add "cpu" to list of protected clocks for sun5i
Now that the ahb clock on sun5i/sun7i is muxable, ahb is no longer
guaranteed to be a child of the cpu clock. Add the cpu clock to
the list of protected clocks so it doesn't get disabled.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-03-21 11:49:21 +01:00
Chen-Yu Tsai 9f2430973d clk: sunxi: Add muxable ahb factors clock for sun5i and sun7i
The AHB clock on sun5i and sun7i are muxable divider clocks.
Use a factors clock to support them.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-03-21 11:48:40 +01:00
Chen-Yu Tsai 71f32f56cb clk: sunxi: Add support for sun9i A80 USB clocks and resets
The USB controller/phy clocks and reset controls are in a separate
address block, unlike previous SoCs where they were in the clock
controller. Also, access to the address block is controlled by a
clock gate to AHB.

Add support for resets requiring a clock to be enabled when
asserting/deasserting the reset controls, and add the sun9i USB
clocks.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-02-23 09:25:54 +01:00
Chen-Yu Tsai 6089ef19c9 clk: sunxi: Move USB clocks to separate file
The USB clocks originally shared code with the gates clocks, but had
additional reset controllers. Move these to a separate file. This will
allow us to add new support for slightly different USB clocks, such as
on the A80, without affecting gates clocks, and also facilitate the
migration of gates clocks to a generic solution.

This also cleans up the USB clocks code slightly, such as adding
newlines, getting rid of the unused clkdev call, using a simple
u32 instead of BITMAP for the clock masks, using BIT() macro to
declare the clock bitmasks, and using of_io_request_and_map() to
get the I/O address.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-02-23 09:25:54 +01:00
Linus Torvalds 18a8d49973 The clock framework changes for 3.20 contain the usual driver additions,
enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based
 devices. Additionaly the framework core underwent a bit of surgery with
 two major changes. The boundary between the clock core and clock
 providers (e.g clock drivers) is now more well defined with dedicated
 provider helper functions. struct clk no longer maps 1:1 with the
 hardware clock but is a true per-user cookie which helps us tracker
 users of hardware clocks and debug bad behavior. The second major change
 is the addition of rate constraints for clocks. Rate ranges are now
 supported which are analogous to the voltage ranges in the regulator
 framework. Unfortunately these changes to the core created some
 breakeage. We think we fixed it all up but for this reason there are
 lots of last minute commits trying to undo the damage.
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Merge tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux

Pull clock framework updates from Mike Turquette:
 "The clock framework changes contain the usual driver additions,
  enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based
  devices.

  Additionally the framework core underwent a bit of surgery with two
  major changes:

   - The boundary between the clock core and clock providers (e.g clock
     drivers) is now more well defined with dedicated provider helper
     functions.  struct clk no longer maps 1:1 with the hardware clock
     but is a true per-user cookie which helps us tracker users of
     hardware clocks and debug bad behavior.

   - The addition of rate constraints for clocks.  Rate ranges are now
     supported which are analogous to the voltage ranges in the
     regulator framework.

  Unfortunately these changes to the core created some breakeage.  We
  think we fixed it all up but for this reason there are lots of last
  minute commits trying to undo the damage"

* tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux: (113 commits)
  clk: Only recalculate the rate if needed
  Revert "clk: mxs: Fix invalid 32-bit access to frac registers"
  clk: qoriq: Add support for the platform PLL
  powerpc/corenet: Enable CLK_QORIQ
  clk: Replace explicit clk assignment with __clk_hw_set_clk
  clk: Add __clk_hw_set_clk helper function
  clk: Don't dereference parent clock if is NULL
  MIPS: Alchemy: Remove bogus args from alchemy_clk_fgcs_detr
  clkdev: Always allocate a struct clk and call __clk_get() w/ CCF
  clk: shmobile: div6: Avoid division by zero in .round_rate()
  clk: mxs: Fix invalid 32-bit access to frac registers
  clk: omap: compile legacy omap3 clocks conditionally
  clkdev: Export clk_register_clkdev
  clk: Add rate constraints to clocks
  clk: remove clk-private.h
  pci: xgene: do not use clk-private.h
  arm: omap2+ remove dead clock code
  clk: Make clk API return per-user struct clk instances
  clk: tegra: Define PLLD_DSI and remove dsia(b)_mux
  clk: tegra: Add support for the Tegra132 CAR IP block
  ...
2015-02-21 12:30:30 -08:00
Tomeu Vizoso 1c8e600440 clk: Add rate constraints to clocks
Adds a way for clock consumers to set maximum and minimum rates. This
can be used for thermal drivers to set minimum rates, or by misc.
drivers to set maximum rates to assure a minimum performance level.

Changes the signature of the determine_rate callback by adding the
parameters min_rate and max_rate.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
[sboyd@codeaurora.org: set req_rate in __clk_init]
Signed-off-by: Michael Turquette <mturquette@linaro.org>
[mturquette@linaro.org: min/max rate for sun6i_ahb1_clk_determine_rate
                        migrated clk-private.h changes to clk.c]
2015-02-02 14:23:42 -08:00
Hans de Goede 76820fcf7a sunxi: clk: Set sun6i-pll1 n_start = 1
For all pll-s on sun6i n == 0 means use a multiplier of 1, rather then 0 as
it means on sun4i / sun5i / sun7i. n_start = 1 is already correctly set
for sun6i pll6, but was missing for pll1, this commit fixes this.

Cc: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-25 16:55:25 +01:00
Hans de Goede 6424e0aeeb clk: sunxi: rewrite sun9i_a80_get_pll4_factors()
The old implementation of sun9i_a80_get_pll4_factors() has several issues,
it checks against 256 / 512 in various places where it should use 255 / 511,
it does the wrong thing for low frequencies which are an even multiple of
6 MHz, e.g. if you ask it for 72 MHz it will result in 144 Mhz, and it does
not take into account that n must be at least 12. Moreover it is quite hard
to read / follow it.

This commit rewrites it to be correct in all cases, and makes it much easier
to follow the code / to read.

Cc: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-25 16:55:13 +01:00
Chen-Yu Tsai 7a6fca879f clk: sunxi: Add driver for A80 MMC config clocks/resets
On the A80 SoC, the 4 mmc controllers each have a separate register
controlling their register access clocks and reset controls. These
registers in turn share a ahb clock gate and reset control.

This patch adds a platform device driver for these controls. It
requires both clocks and reset controls to be available, so using
CLK_OF_DECLARE might not be the best way.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-20 17:14:38 +01:00
Chen-Yu Tsai 61af4d8dce clk: sunxi: Add mod0 and mmc module clock support for A80
The module 0 style clocks, or storage module clocks as named in the
official SDK, are almost the same as the module 0 clocks on earlier
Allwinner SoCs. The only difference is wider mux register bits.

As with earlier Allwinner SoCs, mmc module clocks are a special case
of mod0 clocks, with phase controls for 2 child clocks, output and
sample.

This patch adds support for both.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-19 22:48:55 +01:00
Chen-Yu Tsai eb378df79e clk: sunxi: Add a common setup function for mmc module clocks
The only difference between module clocks on different platforms is the
width of the mux register bits and the valid values, which are passed in
through struct factors_data. The phase clocks parts are identical.

This patch generalizes the setup function, so most of the code can be
reused when adding sun9i support, which has a wider mux register.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-14 17:26:03 +01:00
Maxime Ripard a7d19057e7 clk: sunxi: Remove custom phase function
Now that we don't have any user left for our custom phase function, we can
safely remove this hack from the code.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Chen-Yu Tsai <wens@csie.org>
2015-01-14 10:45:27 +01:00
Maxime Ripard 6b0b8ccff0 clk: sunxi: Rework MMC phase clocks
Instead of having three different clocks for the main MMC clock and the two
phase sub-clocks, which involved having three different drivers sharing the
same register, rework it to have the same single driver registering three
different clocks.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
2015-01-14 10:39:16 +01:00
Chen-Yu Tsai 3ec72fabcc clk: sunxi: Propagate rate changes to parent for mux clocks
The cpu clock on sunxi machines is just a mux clock, which is normally
fed by the main PLL, but can be muxed to the main or low power oscillator.

Make the mux clock propagate rate changes to its parent, so we can
change the clock rate of the PLL, and thus actually implement rate
changing on the cpu clock.

This patch also removes the no reparenting limit.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-06 17:00:15 +01:00
Hans de Goede 6ea3953da4 clk: sunxi: Make the mod0 clk driver also a platform driver
With the prcm in sun6i (and some later SoCs) some mod0 clocks are instantiated
through the mfd framework, and as such do not work with of_clk_declare, since
they do not have registers assigned to them yet at of_clk_declare init time.

Silence the error on not finding registers in the of_clk_declare mod0 clk
setup method, and also register mod0-clk support as a platform driver to work
properly with mfd instantiated mod0 clocks.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-06 10:31:35 +01:00
Hans de Goede b0f2faa5ca ARM: sunxi: Add "allwinner,sun6i-a31s" to mach-sunxi
So far the A31s is 100% compatible with the A31, still lets do the same
as what we've done for the A13 / A10s and give it its own compatible string,
in case we need to differentiate later.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[Maxime: Removed unusude CPU_OF_DECLARE_METHOD]
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-05 09:50:39 +01:00
Chen-Yu Tsai 66e79cf17e clk: sunxi: Fix factor clocks usage for sun9i core clocks
The sunxi factor clocks usage was changed in

    clk: sunxi: Give sunxi_factors_register a registers parameter

However the sun9i core clocks were not fixed up in that patch,
resulting in breakage. This patch fixes that.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Cc: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-12-21 23:51:37 +01:00
Hans de Goede 7c74c220e9 clk: sunxi: Give sunxi_factors_register a registers parameter
Before this commit sunxi_factors_register uses of_iomap(node, 0) to get
the clk registers. The sun6i prcm has factor clocks, for which we want to
use sunxi_factors_register, but of_iomap(node, 0) does not work for the prcm
factor clocks, because the prcm uses the mfd framework, so the registers
are not part of the dt-node, instead they are added to the platform_device,
as platform_device resources.

This commit makes getting the registers the callers duty, so that
sunxi_factors_register can be used with mfd instantiated platform device too.

While at it also add error checking to the of_iomap calls.

This commit also drops the __init function from sunxi_factors_register since
platform driver probe functions are not __init.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-12-21 23:51:37 +01:00
Chen-Yu Tsai 7954dfaee3 clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-divider
This patch unifies the sun6i AHB1 clock, originally supported
with separate mux and divider clks. It also adds support for
the pre-divider on the PLL6 input, thus allowing the clock to
be muxed to PLL6 with proper clock rate calculation.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-12-21 23:51:37 +01:00
Chen-Yu Tsai 75bd2ec1a6 clk: sunxi: Remove ahb1_sdram from sun6i/sun8i protected clocks list
The ahb1_sdram clock gate is only used for accessing the sdram
controller's registers over the bus. It is not used for actually clock
the controller or the dram, hence it does not need to be protected.

This also gets rid of the problem when the protected ahb1_sdram gate
is prepared/enabled while it is still an orphan, and the operation
is not propagated to the correct parent.

This was confirmed on my A23 tablet and my A31 Hummingbird.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-12-21 23:51:37 +01:00
Tomeu Vizoso 646cafc6aa clk: Change clk_ops->determine_rate to return a clk_hw as the best parent
This is in preparation for clock providers to not have to deal with struct clk.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-12-03 16:21:37 -08:00
Hans de Goede c1ec516030 clk: sunxi: gmac-tx-clk mux is not a CLK_MUX_INDEX_BIT mux
A CLK_MUX_INDEX_BIT mux has one bit per parent, but the sun7i-a20-gmac-clk
has 2 bits selecting between 3 possible parents using values of 0, 1, 2,
which makes it a regular mux which should not have CLK_MUX_INDEX_BIT set in
its flag.

However we do not support parent 1 (an external clock), so use a table to
select parent 0 or 2, which are the 2 parents we support.

Note this has not been causing any issues sofar, because we start with a
parent setting of parent 0, and only ever re-parent to parent 2 (for which
we use an index of 1 as we skip parent 1) and with CLK_MUX_INDEX_BIT set
we write a value of 2 for index 1.

Tested on both a cubietruck (which uses rgmii mode) as well as a cs908
(an a31s board which uses mii mode).

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-11-23 17:02:57 +01:00
Chen-Yu Tsai 95e94c1fad clk: sunxi: Implement A31 PLL6 as a divs clock for 2x output
Some clock modules on the A31 use PLL6x2 as one of their inputs.
This patch changes the PLL6 implementation for A31 to a divs clock,
i.e. clock with multiple outputs that have different dividers.
The first output will be the normal PLL6 output, and the second
will be PLL6x2.

This patch fixes the PLL6 N factor in the clock driver, and removes
any /2 dividers in the PLL6 factors clock part. The N factor counts
from 1 to 32, mapping to values 0 to 31, as shown in the A31 manual.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-11-23 17:02:56 +01:00
Chen-Yu Tsai 13d52f6106 clk: sunxi: Specify number of child clocks for divs clocks
Currently sunxi_divs_clk_setup assumes the number of child clocks
to be the same as the number of clock-output-names, and a maximum
of SUNXI_DIVS_MAX_QTY child clocks.

On sun6i, PLL6 only has 1 child clock, but the parent would be used
as well, thereby also having it's own clock-output-names entry. This
results in an extra bogus clock being registered.

This patch adds an entry for the number of child clocks alongside
the data structures for them.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-11-23 17:02:56 +01:00
Chen-Yu Tsai eaa2e9804e clk: sunxi: Removed unused/incorrect sun6i-a31-apb2-clk driver
This driver does not match the hardware, which is actually compatible
to sun4i-a10-apb1-clk. Since we've switch to the correct one, drop
this driver.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-11-23 17:02:56 +01:00
Emilio López 93746e70be clk: sunxi: unify APB1 clock
This commit unifies the APB1 mux with the APB1 clock, using the new
factors infrastructure.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
[wens@csie.org: Add mux mask bits]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-11-11 15:54:40 +01:00
Chen-Yu Tsai 0b0f08028e clk: sunxi: Add support for bus clock gates on Allwinner A80 SoC
This adds the gate clocks for AHB/APB busses on the A80 SoC.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-10-21 21:47:34 +02:00
Chen-Yu Tsai 3b2bd70f03 clk: sunxi: Add support for A80 basic bus clocks
The A80 SoC has 12 PLL clocks, 3 AHB clocks, 2 APB clocks, and a
new "GT" bus, which I assume is some kind of data bus connecting
the processor cores, memory and various busses. Also there is a
bus clock for a ARM CCI400 module.

As far as I can tell, the GT bus and CCI400 bus clock must be
protected.

This patch adds driver support for peripheral related PLLs and
bus clocks on the A80. The GT and CCI400 clocks are added as well
as these 2 along with the PLLs they are clocked from must not be
disabled.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-10-21 21:45:48 +02:00
Chen-Yu Tsai e94f8cb32d clk: sunxi: make factors clock mux mask configurable
Some of the factors-style clocks on the A80 have different widths
for the mux values in the registers.

Add a .muxmask field to clk_factors_config to make it configurable.
Passing a bitmask instead of a width parameter will allow reuse
in case we support table-based muxes in the future.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-10-21 21:40:56 +02:00
Mike Turquette 4dc7ed32f3 Allwinner Clocks Additions for 3.18
The most important part of this serie is the addition of the phase API to
 handle the MMC clocks in the Allwinner SoCs.
 
 Apart from that, the A23 gained a new mbus driver, and there's a fix for a
 incorrect divider table on the APB0 clock.
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Merge tag 'sunxi-clocks-for-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next

Allwinner Clocks Additions for 3.18

The most important part of this serie is the addition of the phase API to
handle the MMC clocks in the Allwinner SoCs.

Apart from that, the A23 gained a new mbus driver, and there's a fix for a
incorrect divider table on the APB0 clock.
2014-09-27 12:52:33 -07:00
Chen-Yu Tsai 9c8176bfb6 clk: sunxi: Add sun8i MBUS clock support
The MBUS clock on sun8i is slightly different from the old mod0 clocks.
The divider is 3 bits wider, while also needing a divider table for the
higher 4 values, which all set the same divider.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-09-27 09:05:43 +02:00
Maxime Ripard 37e1041f04 clk: sunxi: mod0: Introduce MMC proper phase handling
The MMC clock we thought we had until now are actually not one but three
different clocks.

The main one is unchanged, and will have three outputs:
  - The clock fed into the MMC
  - a sample and output clocks, to deal with when should we output/sample data
    to/from the MMC bus

The phase control we had are actually controlling the two latter clocks, but
the main MMC one is unchanged.

We can adjust the phase with a 3 bits value, from 0 to 7, 0 meaning a 180 phase
shift, and the other values being the number of periods from the MMC parent
clock to outphase the clock of.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-09-27 08:58:04 +02:00
Maxime Ripard eaa18f5d09 clk: sunxi: Move mbus to mod0 file
Move the MBUS clock to the module clocks file. It's pretty trivial, but still
requires to enable the clocks to make sure it won't get disabled.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-09-27 08:58:03 +02:00
Maxime Ripard 992a56e489 clk: sunxi: Move mod0 clock to a file of its own
Since we know have the ability to declare factors clock outside of clk-sunxi,
create a new mod0 driver to deal with the mod0 clocks.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-09-27 08:58:03 +02:00
Maxime Ripard 03e29bbf40 clk: sunxi: Introduce mbus compatible
Even though the mbus clock is a regular module clock, given its nature, it
needs to be enabled all the time.

Introduce a new compatible, to differentiate it from the other module clocks.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-09-27 08:58:02 +02:00
Maxime Ripard 601da9d0a5 clk: sunxi: factors: Invert the probing logic
Until now, the factors clock probing was done directly by sunxi_init_clocks,
with the factors registration being called directly with the clocks data passed
as an argument.

This approch has shown its limits when we added more clocks, since we couldn't
really split code with such a logic in smaller files, and led to a huge file
having all the clocks.

Introduce an intermediate probing function, so that factor clocks will be able
to directly be called by CLK_OF_DECLARE, which will in turn ease the split into
several files.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-09-27 08:58:01 +02:00
Kiran Padwal 59c0621d4d clk: Remove .owner field for driver
There is no need to init .owner field.

Based on the patch from Peter Griffin <peter.griffin@linaro.org>
"mmc: remove .owner field for drivers using module_platform_driver"

This patch removes the superflous .owner field for drivers which
use the module_platform_driver API, as this is overriden in
platform_driver_register anyway."

Signed-off-by: Kiran Padwal <kiran.padwal@smartplayin.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-25 17:43:31 -07:00
Chen-Yu Tsai cfe4c93b58 clk: sunxi: add correct divider table for sun4i-apb0 clock
The sun4i-apb0 clock, as found on all platforms using it, is a
power-of-two-based divider clock, with a special divider of 2
for value 0.

This was causing the clock framework to incorrectly calculate
the clock rate for apb1 and related modules on sun6i and sun8i.
On sun[4/5/7]i, u-boot SPL configures the divider with value 1
for /2 divider, so no suprises there.

This patch adds a proper divider table for it, so the correct
clock rate can be calculated.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-09-13 10:07:24 +02:00
Emilio López 381c1ccd65 clk: sunxi: staticize structures and arrays
There are some structs and arrays on the driver that are not used
anywhere else. Let's mark them as static.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-28 15:39:22 -07:00
Emilio López 89a9456d6e clk: sunxi: add __iomem markings to MMIO pointers
This commit adds __iomem thoughout the sunxi clock driver, in places
where it was ommited. This cleans most of the sparse warnings we
are getting here.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-28 15:39:05 -07:00
Mike Turquette 3cc5aba415 Allwinner clocks additions for 3.17
This pull request adds support for the clocks found in the newly supported
 Allwinner A23 clocks.
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Merge tag 'sunxi-clocks-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next-sunxi

Allwinner clocks additions for 3.17

This pull request adds support for the clocks found in the newly supported
Allwinner A23 clocks.
2014-07-25 17:45:30 -07:00
Chen-Yu Tsai 6c1d66f0da clk: sunxi: sun6i-a31-apb0-gates: Add A23 APB0 support
This patch adds "allwinner,sun8i-a23-apb0-gates-clk", a A23 specific
compatible to the sun6i-a31-apb0-gates clock driver, along with the
gate bitmap.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-07-15 08:53:24 +02:00
Chen-Yu Tsai b72efd0f65 clk: sunxi: sun6i-apb0-gates: use bitmaps for valid gate indices
sun6i-apb0-gates uses the "clock-indices" DT property to indicate
valid gate bits or holes in between. However, the rest of sunxi
clock drivers use bitmaps for this purpose.

This patch modifies sun6i-apb0-gates to use bitmaps as well, to be
consistent with the sunxi platform. Also add the missing call to
clk_register_clkdev, so system clock lookups will work.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-07-15 08:52:11 +02:00
Chen-Yu Tsai cd6eb534fb clk: sunxi: Fix gate indexing for sun6i-a31-apb0-gates
sun6i-a31-apb0-gates supports using clock-indices for holes between
individual gates. However, the driver passes the number of gates
registered in clk_data->clk_num, which of_clk_src_onecell_get uses
to recognize the range of valid indices a consumer can use.

This patch makes the driver pass the maximum gate index + 1, so
of_clk_src_onecell_get does not complain about indices greater
than gates registered.

This was tested on the A23 SoC, which has a similar APB0 clock,
but has holes for gates to removed IP blocks.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-07-07 10:53:52 +02:00
Chen-Yu Tsai 57a1fbf284 clk: sunxi: Add A23 APB0 divider clock support
The A23 has an almost identical PRCM clock tree. The difference in
the APB0 clock is the smallest divisor is 1, instead of 2.

This patch adds a separate sun8i-a23-apb0-clk driver to support it.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-07-07 10:46:21 +02:00
Chen-Yu Tsai 515c1a4bdc clk: sunxi: Add A23 clocks support
The clock control unit on the A23 is similar to the one found on the A31.

The AHB1, APB1, APB2 gates on the A23 are almost identical to the ones
on the A31, but some outputs are missing.

The main CPU PLL (PLL1) however is like that on older Allwinner SoCs,
such as the A10 or A20, but the N factor starts from 1 instead of 0.

This patch adds support for PLL1 and all the basic clock muxes and gates.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-07-04 12:05:17 +02:00
Chen-Yu Tsai ea5671bffb clk: sunxi: Add support for table-based divider clocks
A few of the clock modules have odd dividers, such as
the 2 lowest dividers being the same (2), or have the
same divider when the highest bit is set.

This patch adds support for optional divider tables,
so the clock framework will know about the odd values.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-07-04 12:05:13 +02:00
Chen-Yu Tsai 9a5e6c7eb5 clk: sunxi: Support factor clocks with N factor starting not from 0
The PLLs on newer Allwinner SoC's, such as the A31 and A23, have a
N multiplier factor that starts from 1, not 0.

This patch adds an option to the factor clk driver's config data
structures to specify the base value of N.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-07-04 12:05:12 +02:00
Chen-Yu Tsai 70eab199fa clk: sunxi: move "ahb_sdram" to protected clock list
With sunxi_gates clocks registered with clkdev, we can use the
protected clocks list to enable the "ahb_sdram" clock, instead
of looking for it and adding CLK_IGNORE_UNUSED inline in the
clock setup code.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-07-04 12:05:09 +02:00
Chen-Yu Tsai d14e47056c clk: sunxi: register clock gates with clkdev
The new important clock protect code requires the clocks be
registered with clkdev. This was missing for sunxi_gates
type clocks.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-07-04 12:04:55 +02:00
Himangi Saraogi c3dcac875e clk: sunxi: fix devm_ioremap_resource error detection code
devm_ioremap_resource returns an ERR_PTR value, not NULL, on failure.

A simplified version of the semantic match that finds this problem is as
follows:

// <smpl>
@@
expression e,e1;
statement S;
@@

*e = devm_ioremap_resource(...);
if (!e1) S

// </smpl>

Signed-off-by: Himangi Saraogi <himangi774@gmail.com>
Acked-by: Julia Lawall <julia.lawall@lip6.fr>
Acked-by Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-01 23:37:34 -07:00
Boris BREZILLON c8a76cac19 clk: sunxi: add PRCM (Power/Reset/Clock Management) clks support
The PRCM (Power/Reset/Clock Management) unit provides several clock
devices:
- AR100 clk: used to clock the Power Management co-processor
- AHB0 clk: used to clock the AHB0 bus
- APB0 clk and gates: used to clk peripherals connected to the APB0 bus

Add support for these clks in a separate driver so that they can be probed
as platform devices instead of registered during early init.
This is needed to be able to probe PRCM MFD subdevices.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
2014-06-11 10:25:02 +02:00
Maxime Ripard efb3184c08 clk: sun6i: Protect SDRAM gating bit
Prevent the SDRAM controller from being gated by force-enabling it in the
machine code.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
2014-06-11 10:25:02 +02:00
Maxime Ripard 2df73f40dc clk: sun6i: Protect CPU clock
Right now, AHB is an indirect child clock of the CPU clock. If that
happens to change, since the CPU clock has no other consumers declared
in Linux, it would be shut down, which is not really a good idea.

Prevent this by forcing it enabled.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
2014-06-11 10:25:01 +02:00
Maxime Ripard 134a6690a3 clk: sunxi: Rework clock protection code
Since we start to have a lot of clocks to protect, some of them in a
few SoCs only, it becomes difficult to handle the clock protection
without having to add per machine exceptions.

Add per-SoC data to tell which clock to leave enabled.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
2014-06-11 10:25:01 +02:00
Maxime Ripard 59cb10e32a clk: sunxi: Move the GMAC clock to a file of its own
Since we have a folder of our own, we can actually make use of it by
splitting the huge clock file into several sub drivers.

The gmac clock is pretty easy to deal with, since it's pretty much
isolated and doesn't have any dependency on the other clocks.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
2014-06-11 09:58:44 +02:00
Maxime Ripard ff01df28e5 clk: sunxi: Move the 24M oscillator to a file of its own
Since we have a folder of our own, we can actually make use of it by
splitting the huge clock file into several sub drivers.

The main oscillator is pretty easy to deal with, since it's pretty much
isolated.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
2014-06-11 09:58:44 +02:00
Maxime Ripard 2c6fba1038 clk: sunxi: Remove calls to clk_put
Callers of clk_put must disable the clock first. This also means that
as long as the clock is enabled the driver should hold a reference to
that clock. Hence, the call to clk_put here are bogus and should be
removed.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
2014-06-11 09:58:44 +02:00