Adding CPU Idle state in the device tree for Armada 8040 seems to
breaks boot on some board, so let's revert it waiting for a better
solution.
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Merge tag 'mvebu-fixes-4.20-1' of git://git.infradead.org/linux-mvebu into fixes
mvebu fixes for 4.20
Adding CPU Idle state in the device tree for Armada 8040 seems to
breaks boot on some board, so let's revert it waiting for a better
solution.
* tag 'mvebu-fixes-4.20-1' of git://git.infradead.org/linux-mvebu:
Revert "arm64: dts: marvell: add CPU Idle power state support on Armada 7K/8K"
Signed-off-by: Olof Johansson <olof@lixom.net>
- Introduce protected-clock DT binding to fix breakage on qcom sdm845-mtp
boards where the qspi clks introduced this merge window cause the
firmware on those boards to take down the system if we try to read
the clk registers
- Fix a couple off-by-one errors found by Dan Carpenter
- Handle failure in zynq fixed factor clk driver to avoid using
uninitialized data
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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"A few clk driver fixes this time:
- Introduce protected-clock DT binding to fix breakage on qcom
sdm845-mtp boards where the qspi clks introduced this merge window
cause the firmware on those boards to take down the system if we
try to read the clk registers
- Fix a couple off-by-one errors found by Dan Carpenter
- Handle failure in zynq fixed factor clk driver to avoid using
uninitialized data"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: zynqmp: Off by one in zynqmp_is_valid_clock()
clk: mmp: Off by one in mmp_clk_add()
clk: mvebu: Off by one bugs in cp110_of_clk_get()
arm64: dts: qcom: sdm845-mtp: Mark protected gcc clocks
clk: qcom: Support 'protected-clocks' property
dt-bindings: clk: Introduce 'protected-clocks' property
clk: zynqmp: handle fixed factor param query error
Enable the USB3 peripheral that is wired to CON2 on the Clearfog GT-8K
board.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Add DT support for the Macchiatobin Single Shot board from SolidRun,
which is similar to the Double Shot board, but does not have the
10G 3310 PHYs - the two ethernet ports are instead connected directly
to the SFP+ cages.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
The ESPRESSObin board has a emmc interface available on U11: declare it
and let the bootloader enable it if the emmc is present.
[gregory.clement@bootlin.com: disable the emmc by default]
Signed-off-by: Ding Tao <miyatsu@qq.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
add the qDMA device tree nodes for LS1046A devices.
Signed-off-by: Wen He <wen.he_1@nxp.com>
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
add the qDMA device tree nodes for LS1043A devices.
Signed-off-by: Wen He <wen.he_1@nxp.com>
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
LS1088A has a 48-bit address size so make sure that the
dma-ranges property reflects this.
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The fsl-mc node should sit under the soc node, so move it to
its proper location.
Fixes: ac7c9ff741 ("arm64: dts: ls1088a: add fsl-mc hardware resource manager node")
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.
Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
LS1028A contains two ARM v8 CortexA72 processor cores
with 32 KB L1-D cache and 48 KB L1-I cache
Features summary
Two 32-bit / 64-bit ARM v8 Cortex-A72 CPUs
- Arranged as single clusters of two cores sharing a 1 MB L2 cache
- Speed Up to 1.3 GHz
- Support for cluster power-gating.
Cache coherent interconnect (CCI-400)
- Hardware-managed data coherency
- Up to 400 MHz
32-bit DDR4 SDRAM memory controller with ECC
Two PCIe 3.0 controllers
One serial ATA (SATA 3.0) controller
Two high-speed USB 3.0 controllers with integrated PHY
Following levels of DTSI/DTS files have been created for the LS1028A
SoC family:
- fsl-ls1028a.dtsi:
DTS-Include file for NXP LS1028A SoC.
- fsl-ls1028a-qds.dts:
DTS file for NXP LS1028A QDS board.
- fsl-ls1028a-rdb.dts:
DTS file for NXP LS1028A RDB board
Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Removed the wrong compatible string "snps,dw-pcie", in case
match incorrect driver.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add the status property disable the PCIe, the property will be enable
by bootloader.
Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
LS1012A-FRWY is an ls1012a based SoC board.
Key features of this board are Micro SD, USB 3.0,
upto 1GB DDR, UART
Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
A long running stress test on a custom board shipping an AXG SoCs and a
Realtek RTL8211F PHY revealed that after a few hours the connection
speed would drop drastically, from ~1000Mbps to ~3Mbps. At the same time
the 'macirq' (eth0) IRQ would stop being triggered at all and as
consequence the GMAC IRQs never ACKed.
After a painful investigation the problem seemed to be due to a wrong
defined IRQ type for the GMAC IRQ that should be LEVEL_HIGH instead of
EDGE_RISING.
The change in the macirq IRQ type also solved another long standing
issue affecting this SoC/PHY where EEE was causing the network
connection to die after stressing it with iperf3 (even though much
sooner). It's now possible to remove the 'eee-broken-1000t' quirk as
well.
Fixes: feb3cbea09 ("ARM64: dts: meson-gxbb-odroidc2: fix GbE tx link breakage")
Fixes: 6d28d57751 ("ARM64: dts: meson-axg: fix ethernet stability issue")
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Enable the GPIO interrupt controller for the AXG SoCs.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Now that the GPIO controller has been enabled also on AXG we can hook up
the GPIO interrupt for the PHY.
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Move from dwc3-of-simple to dwc3-qcom glue driver to
support peripheral mode which requires qscratch wrapper
programming on VBUS event.
Fixes: a4333c3a6b ("usb: dwc3: Add Qualcomm DWC3 glue driver")
Signed-off-by: Manu Gautam <mgautam@codeaurora.org>
Tested-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch sets the msm8998 xo clock name back to xo_board. Recent
clock tree changes fixed the clock tree and the change to the xo name
is causing issues where msm8998 boards do not boot properly. Let's
change it back and leave the xo label on it.
Fixes: 634da3307b (arm64: dts: qcom: msm8998: correct xo clock name)
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Jeffrey Hugo <jhugo@codeaurora.org>
Technically the display-hub driver could access registers via the
specified region, though it practice it will do so via the display
controllers' register regions.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Technically the display-hub driver could access registers via the
specified region, though it practice it will do so via the display
controllers' register regions.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The RTC module on the A64 was claimed to be the same as on the A31, when
in fact it is not. It is actually compatible to the H3's RTC. The A64's
RTC has some extra crypto-related registers which the H3's does not, but
the exact function of these is not clear.
This patch fixes the compatible string and clock properties to conform
to the updated bindings. The device node for the internal oscillator is
removed, as it is internalized into the RTC device. Clock references to
the IOSC and LOSC are also fixed.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The RTC module on the H3 was claimed to be the same as on the A31, when
in fact it is not. The A31 does not have an RTC external clock output,
and its internal RC oscillator's average clock rate is not in the same
range. The H5's RTC has some extra crypto-related registers compared to
the H3. Their exact functions are not clear. Also the RTC-VIO regulator
has different settings.
This patch fixes the compatible string and clock properties to conform
to the updated bindings. The device node for the internal oscillator is
removed, as it is internalized into the RTC device. Clock references to
the IOSC and LOSC are also fixed.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The CEC controller found on Tegra194 can be used to control consumer
devices using the HDMI CEC pin.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The HDA controller found on Tegra194 can be used for audio playback over
HDMI.
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The CEC controller found on Tegra186 can be used to control consumer
devices using the HDMI CEC pin.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The rockpro64 does have hdmi support, so add the necessary
devicetree node to enable it.
Signed-off-by: Oskari Lemmela <oskari@lemmela.net>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Rockpro64 is not able boot if GPIO1_C1 pin is pulled high
before loading linux kernel.
In rockpro64 GPIO1_C1 pin is connected vdd_cpu_b regulator
VSEL pin. Pin should be pulled down in normal operation and
pulled high in suspend.
PMIC LDO_REG2 is connected to touch panel connector.
Rename regulator and set it to correct voltage.
PCIe power is controller by GPIO1_D0.
Schematics can be downloaded from:
http://files.pine64.org/doc/rockpro64/rockpro64_v21-SCH.pdf
Signed-off-by: Oskari Lemmela <oskari@lemmela.net>
Acked-by: Akash Gajjar <Akash_Gajjar@mentor.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the Video Processing Unit node for the RK3399 SoC.
Also, fix the VPU IOMMU node, which was disabled and lacking
its power domain property.
Reviewed-by: Tomasz Figa <tfiga@chromium.org>
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the backlight device for the LVDS1 output, in preparation for panel
support.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This adds nodes for all possible UARTs to sdm845.dtsi. By default
only configure the RX/TX lines with pinctrl. Boards that use UARTs
with flow control can overwrite the configuration in the
<board>.dtsi.
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds the device node of the GCE hardware for CMDQ module.
Signed-off-by: Houlong Wei <houlong.wei@mediatek.com>
Signed-off-by: HS Liao <hs.liao@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This adds the Video Engine node for the A64. Since it can map the whole
DRAM range, there is no particular need for a reserved memory node
(unlike platforms preceding the A33).
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Add the description for the SRAM C1 section to the A64 device-tree.
Since there is no entry for this section in the A64 manual, the base
address and size were only verified to be consistent empirically.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
This adds the Video Engine node for the H5. Since it can map the whole
DRAM range, there is no particular need for a reserved memory node
(unlike platforms preceding the A33).
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
The EMAC driver requires a syscon node to access the EMAC clock
configuration register (that is part of the system-control register
range and controlled). For this purpose, a dummy syscon node was
introduced to let the driver access the register freely.
Recently, the EMAC driver was tuned to get access to the register when
the SRAM driver is registered (as used on the A64). As a result, it is
no longer necessary to have a dummy syscon node for that purpose.
Now that we have a proper system-control node for both the H3 and H5,
we can get rid of that dummy syscon node and have the EMAC driver use
the node corresponding to the proper SRAM driver (by switching the
syscon label over to each dtsi). This way, we no longer have two
separate nodes for the same register space.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Add the H5-specific system control node description to its device-tree
with support for the SRAM C1 section, that will be used by the video
codec node later on.
The CPU-side SRAM address was obtained empirically while the size was
taken from the documentation. They may not be entirely accurate.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
This reverts commit 8ed4636877.
This commit breaks boot on Armada 8K based systems. Reverting it makes
affected systems boot again.
Reported-by: Sergey Matyukevich <geomatsi@gmail.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
There is actually no alternate xtal on any of the axg board I have
seen so far. The 32k is actually generated internally, deriving from
the 24MHz main xtal.
Amlogic SoC also have the option to provide the 32k reference externally,
through one of the AO pads, but no platform is using this ATM.
Fixes: 5e395e1466 ("ARM64: dts: meson-axg: add an 32K alt aoclk")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add the watchdog node also on the AXG platforms.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add a node for the Camera Subsystem present on the Qualcomm
MSM8996 SoC.
Signed-off-by: Todor Tomov <todor.tomov@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add pinctrls required for camera sensors:
- power down signal;
- reset signal;
- camera external clock.
Signed-off-by: Todor Tomov <todor.tomov@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add pinctrls required for Camera Control Interface.
Signed-off-by: Todor Tomov <todor.tomov@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add a node for the Camera Subsystem present on the Qualcomm
MSM8916 SoC.
Signed-off-by: Todor Tomov <todor.tomov@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.
Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
- kernelci awaits a working stdout-path.
Fix the path for reference board and bananapi-r64
- general propouse timer has issues with clocks that didn't
get probed early. Delete the DT node as the timer isn't
need, a ARM arch timer exists on the system.
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Merge tag 'v4.19-next-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into fixes
DT mt7622:
- Kernelci awaits a working stdout-path.
Fix the path for reference board and bananapi-r64
- General propouse timer has issues with clocks that didn't
get probed early. Delete the DT node as the timer isn't
need, a ARM arch timer exists on the system.
* tag 'v4.19-next-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
arm64: dts: mt7622: Drop the general purpose timer node
arm64: dts: mt7622: fix no more console output on BPI-R64 board
arm64: dts: mt7622: fix no more console output on rfb1
Signed-off-by: Olof Johansson <olof@lixom.net>
The P2888 processor module contains a TI TMP451 temperature sensor with
two channels. These are used to measure the temperatures at different
locations on the module.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The power and force recovery buttons found on Jetson Xavier are hooked
up to two Tegra GPIOs. The power button can also function as a wake-up
source.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The AON GPIO controller is in an always-on power partition and typically
provides pins for functions that need to always work, such as the power
key for example.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The on-die RTC isn't hooked up to a backup battery, so it isn't useful
to track time across reboots, but as long as power remains enabled, it
keeps track of time accurately and can be used to wake the system from
sleep, for example.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The RTC on Tegra194 is very similar to the RTC on earlier generations.
One notable exception is that the source clock is now the 32 kHz clock
instead of a dedicated RTC clock and the RTC alarm is a wake event and
can be used to wake the system from sleep.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Wake events are a feature that allows the interrupt and GPIO controllers
to be powered off as part of system sleep. The PMC which is always on is
monitoring these wake events and can power up subsequent controllers as
necessary to process them.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The on-die RTC isn't hooked up to a backup battery, so it isn't useful
to track time across reboots, but as long as power remains enabled, it
keeps track of time accurately and can be used to wake the system from
sleep, for example.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The RTC on Tegra186 is very similar to the RTC on earlier generations.
One notable exception is that the source clock is now the 32 kHz clock
instead of a dedicated RTC clock and the RTC alarm is a wake event and
can be used to wake the system from sleep.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Wake events are a feature that allows the interrupt and GPIO controllers
to be powered off as part of system sleep. The PMC which is always on is
monitoring these wake events and can power up subsequent controllers as
necessary to process them.
Signed-off-by: Thierry Reding <treding@nvidia.com>
In order for the correct interrupt type to be configured, the event
action for the power key needs to be "asserted".
Signed-off-by: Thierry Reding <treding@nvidia.com>
Enable these thermal zones to be able to monitor their temperatures and
control the fan to cool down the system if necessary.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add the 5V HDMI regulator and hook up the VDD_1V0 and VDD_1V8HS supplies
from the PMIC to the display block. Also enable the display hub which is
responsible for instantiating the display controllers. Finally, enable
the third SOR that drives the TMDS signals to the HDMI connector.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra194 has a version of VIC that is very similar to that on Tegra186.
Add the device tree node for it that is enabled by default.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra194 contains a display architecture very similar to that found on
the Tegra186. One notable exception is that DSI is no longer a supported
output. Instead there are four display controllers and four SORs (with a
DPAUX associated to each of them) that can drive HDMI or DP.
Signed-off-by: Thierry Reding <treding@nvidia.com>
* Hi3660 SoC and related boards:
- Standardize LED labels and triggers for the hikey960 board
- Add the missing cooling-cells property for the cpu nodes
- Add all cpus into the cooling maps
* Hi3670 SoC and related boards:
- Add clock nodes and update the uart clock
- Add Pinctrl, GPIO and uart nodes
- Enable uart and add GPIO line names for the hikey970 board
* Hi3798 SoC and related boards:
- Standardize LED labels and triggers for the poplar board
* Hi6220 SoC and related boards:
- Standardize LED labels and triggers for the hikey board
- Add all cpus into the cooling maps
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Merge tag 'hisi-arm64-dt-for-4.21' of git://github.com/hisilicon/linux-hisi into next/dt
ARM64: DT: Hisilicon SoCs DT updates for 4.21
* Hi3660 SoC and related boards:
- Standardize LED labels and triggers for the hikey960 board
- Add the missing cooling-cells property for the cpu nodes
- Add all cpus into the cooling maps
* Hi3670 SoC and related boards:
- Add clock nodes and update the uart clock
- Add Pinctrl, GPIO and uart nodes
- Enable uart and add GPIO line names for the hikey970 board
* Hi3798 SoC and related boards:
- Standardize LED labels and triggers for the poplar board
* Hi6220 SoC and related boards:
- Standardize LED labels and triggers for the hikey board
- Add all cpus into the cooling maps
* tag 'hisi-arm64-dt-for-4.21' of git://github.com/hisilicon/linux-hisi:
ARM64: dts: hisilicon: Add all CPUs in cooling maps
arm64: dts: hi3660: Add missing cooling device properties for CPUs
arm64: dts: hisilicon: poplar: Standardize LED labels and triggers
arm64: dts: hisilicon: hikey960: Standardize LED labels and triggers
arm64: dts: hisilicon: hikey: Standardize LED labels and triggers
arm64: dts: hisilicon: hikey970: Add GPIO line names
arm64: dts: hisilicon: hikey970: Enable on-board UARTs
arm64: dts: hisilicon: hi3670: Add UART nodes
arm64: dts: hisilicon: hi3670: Add GPIO controller support
arm64: dts: hisilicon: Add Pinctrl support for HiKey970 board
arm64: dts: hisilicon: Source SoC clock for UART6
arm64: dts: hisilicon: Add clock nodes for Hi3670 SoC
Signed-off-by: Olof Johansson <olof@lixom.net>
This updates the Versatile Express family DTS files to
contain the correct and detailed information required
for the PL11x DRM driver to work properly.
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Merge tag 'vexpress-drm-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/dt
Versatile Express DTS update for DRM:
This updates the Versatile Express family DTS files to
contain the correct and detailed information required
for the PL11x DRM driver to work properly.
* tag 'vexpress-drm-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
ARM: dts: Modernize the Vexpress PL111 integration
Signed-off-by: Olof Johansson <olof@lixom.net>
- Use SPDX license identifier for all SoCFPGA DTS files.
- Remove dma-mask property as it has been deprecated.
- Use tabs in DTS files.
- Use the specific "altr,stratix10-rst-mgr" property for the Stratix10
reset manager.
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Merge tag 'socfpga_dts_updates_for_v5.0' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt
SoCFPGA DTS updates for v5.0
- Use SPDX license identifier for all SoCFPGA DTS files.
- Remove dma-mask property as it has been deprecated.
- Use tabs in DTS files.
- Use the specific "altr,stratix10-rst-mgr" property for the Stratix10
reset manager.
* tag 'socfpga_dts_updates_for_v5.0' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
arm64: dts: stratix10: use "altr,stratix10-rst-mgr" binding
ARM: dts: socfpga: use tabs for indentation
arm: dts: socfpga: remove dma-mask property
arm: dts: socfpga*.dts*: use SPDX-License-Identifier
Signed-off-by: Olof Johansson <olof@lixom.net>
for all Gru devices, rk3399 spi dma properties, some improvements for
the rk3399-sapphire board (fan, chosen, backlight), hs200 mode for the
emmc on the rock64 and declaring all cpu cores in the cooling maps
instead of just cpu0.
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Merge tag 'v4.21-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt
New dts for Gru-Scarlet (tablet device), default backlight brightness
for all Gru devices, rk3399 spi dma properties, some improvements for
the rk3399-sapphire board (fan, chosen, backlight), hs200 mode for the
emmc on the rock64 and declaring all cpu cores in the cooling maps
instead of just cpu0.
* tag 'v4.21-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: Add all CPUs in cooling maps
arm64: dts: rockchip: add Gru Scarlet devicetrees
arm64: dts: rockchip: move backlight from rk3399 sapphire to excavator
arm64: dts: rockchip: Use default brightness table for rk3399-gru
arm64: dts: rockchip: add chosen node on rk3399-sapphire
arm64: dts: rockchip: enable HS200 for eMMC on rock64
arm64: dts: rockchip: add fan on rk3399-sapphire board
arm64: dts: rockchip: add rk3399 SPI DMAs
Signed-off-by: Olof Johansson <olof@lixom.net>
and fixup of the pcie reset polarity on puma-haikou.
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Merge tag 'v4.20-rockchip-dts64fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into fixes
Removal of vdd_log regulator on rk960 to fix a stability issue
and fixup of the pcie reset polarity on puma-haikou.
* tag 'v4.20-rockchip-dts64fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: Fix PCIe reset polarity for rk3399-puma-haikou.
arm64: dts: rockchip: remove vdd_log from rock960 to fix a stability issues
Signed-off-by: Olof Johansson <olof@lixom.net>
Deassert the reset and wireless disable signals on the CON2 mini-PCIe
socket. That allows the host to detect USB devices on the mini-PCIe
socket.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This reset signal controls the Marvell 1512 1G PHY.
Note that current implementation queries the PHY over the MDIO bus
(get_phy_device() call from of_mdiobus_register_phy()) before reset
signal deassert. If the PHY reset signal is asserted at boot time, PHY
registration fails. So current code relies on the bootloader to deassert
the reset signal.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
The fixed regulator driver ignores the gpio flags, so this change has
no practical effect in the current implementation. Fix it anyway to
correct the hardware description.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
The scm binding and driver was updated to rely on the fallback to the
default qcom,scm for any modern SoC and as such both are required. Add
the default compatible to make the scm instance probe.
Fixes: d850156a22 ("arm64: dts: qcom: msm8998: Add firmware node")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
While commit 3b7e7848f0 ("arm64: dts: renesas: r8a7795: Add IPMMU
device nodes") for R-Car H3 ES2.0 did include power-domains properties,
they were forgotten in the counterpart for older R-Car H3 ES1.x SoCs.
Fixes: e4b9a493df ("arm64: dts: renesas: r8a7795-es1: Add IPMMU device nodes")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The R-Car Gen3 HardWare Manual Errata for Rev. 1.00 (Aug 24, 2018)
removed the IPMMU-IR IOMMU instance on R-Car M3-N, as this SoC does not
have an Image Processing Unit (IMP-X5) nor the A3IR power domain.
Fixes: 55697cbb44 ("arm64: dts: renesas: r8a779{65,80,90}: Add IPMMU devices nodes")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
AXP803 ACIN pins are routed from SOM to the DC jack on the baseboard.
AXP803 charger pins BATSENSE, LOADSENSE, N_BATDRV, LX_CHG, VIN_CHG
and IPSOUT are connected via PMOS driver to SOM VBAT pins. VBAT and
AXP803 TS pins are routed to the baseboard 3-pin battery connector.
Signed-off-by: Oskari Lemmela <oskari@lemmela.net>
Reviewed-by: Quentin Schulz <quentin.schulz@bootlin.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Parts of the AXP803 are compatible with their counterparts on the AXP813.
Add DT nodes ADC, GPIO, AC and battery power supplies.
Signed-off-by: Oskari Lemmela <oskari@lemmela.net>
Reviewed-by: Quentin Schulz <quentin.schulz@bootlin.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The SDC2 control pins are typically used to manage sleep.
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The externally accessible SD card slot on the MTP is driven by SDCC2.
Wire it up for use.
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
SDCC2 is typically used as the controller for an external SD card slot.
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The root parent clock of most msm8998 clock is the "xo" clock. The DT node
is incorrectly named "xo_board", which prevents Linux from correctly
parsing the clock tree, resulting in most clocks being unparented and
unable to be manipulated. The end result is that we can't turn on clocks
for peripherals like SD, so init usually fails.
Fixes: 4807c71cc6 (arm64: dts: Add msm8998 SoC and MTP board support)
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The Amlogic Meson GX SoCs embeds a clock measurer IP to measure the internal
clock paths frequencies.
This patch adds the node in the top-level meson-gx dtsi.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.
Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This patch adds support for the Phicomm N1. This device based on P230 reference design.
And this box doesn't have cvbs, so disable related section in device tree.
Signed-off-by: He Yangxuan <yangxuan8282@gmail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
On Amlogic chipsets, the bias set through pinconf applies to the pad
itself, not only the GPIO function. This means that even when we change
the function of the pad from GPIO to anything else, the bias previously
set still applies.
As we have seen with the eMMC, depending on the bias type and the function,
it may trigger problems.
The underlying issue is that we inherit whatever was left by previous user
of the pad (pinconf, u-boot or the ROM code). As a consequence, the actual
setup we will get is undefined.
There is nothing mentioned in the documentation about pad bias and pinmux
function, however leaving it undefined is not an option.
This change consistently disable the pad bias for every pinmux functions.
It seems to work well, we can only assume that the necessary bias (if any)
is already provided by the pin function itself.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
In some cases (such as a boot from SPI) the bootloader or the ROM code may
leave a bias pull-down on the mmc pins. If so the MMC will fail during the
initialisation.
Explicitly disabling the pinmux solves the problem.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
In the pinmux of the mmc clk_gate nodes, we define 2 subnodes. One for
the function definition, the other for the bias. This is not necessary
since we can define the function and the bias in the same subnode.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Olof Johansson