By default we enable CONFIG_I2C_MUX and CONFIG_I2C_MUX_PCA954x,
which are needed on T2080QDS, T4240QDS, B4860QDS, etc.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[scottwood@freescale.com: fixed subject line]
Signed-off-by: Scott Wood <scottwood@freescale.com>
enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based
devices. Additionaly the framework core underwent a bit of surgery with
two major changes. The boundary between the clock core and clock
providers (e.g clock drivers) is now more well defined with dedicated
provider helper functions. struct clk no longer maps 1:1 with the
hardware clock but is a true per-user cookie which helps us tracker
users of hardware clocks and debug bad behavior. The second major change
is the addition of rate constraints for clocks. Rate ranges are now
supported which are analogous to the voltage ranges in the regulator
framework. Unfortunately these changes to the core created some
breakeage. We think we fixed it all up but for this reason there are
lots of last minute commits trying to undo the damage.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJU54D5AAoJEDqPOy9afJhJs6AQAK5YuUwjDchdpNZx9p7OnT1q
+poehuUwE/gYjmdACqYFyaPrI/9f43iNCfFAgKGLQqmB5ZK4sm4ktzfBEhjWINR2
iiCx9QYMQVGiKwC8KU0ddeBciglE2b/DwxB45m9TsJEjowucUeBzwLEIj5DsGxf7
teXRoOWgXdz1MkQJ4pnA09Q3qEPQgmu8prhMfka/v75/yn7nb9VWiJ6seR2GqTKY
sIKL9WbKjN4AzctggdqHnMSIqZoq6vew850bv2C1fPn7GiYFQfWW+jvMlVY40dp8
nNa2ixSQSIXVw4fCtZhTIZcIvZ8puc7WVLcl8fz3mUe3VJn1VaGs0E+Yd3GexpIV
7bwkTOIdS8gSRlsUaIPiMnUob5TUMmMqjF4KIh/AhP4dYrmVbU7Ie8ccvSxe31Ku
lK7ww6BFv3KweTnW/58856ZXDlXLC6x3KT+Fw58L23VhPToFgYOdTxn8AVtE/LKP
YR3UnY9BqFx6WHXVoNvg3Piyej7RH8fYmE9om8tyWc/Ab8Eo501SHs9l3b2J8snf
w/5STd2CYxyKf1/9JLGnBvGo754O9NvdzBttRlygB14gCCtS/SDk/ELG2Ae+/a9P
YgRk2+257h8PMD3qlp94dLidEZN4kYxP/J6oj0t1/TIkERWfZjzkg5tKn3/hEcU9
qM97ZBTplTm6FM+Dt/Vk
=zCVK
-----END PGP SIGNATURE-----
Merge tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux
Pull clock framework updates from Mike Turquette:
"The clock framework changes contain the usual driver additions,
enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based
devices.
Additionally the framework core underwent a bit of surgery with two
major changes:
- The boundary between the clock core and clock providers (e.g clock
drivers) is now more well defined with dedicated provider helper
functions. struct clk no longer maps 1:1 with the hardware clock
but is a true per-user cookie which helps us tracker users of
hardware clocks and debug bad behavior.
- The addition of rate constraints for clocks. Rate ranges are now
supported which are analogous to the voltage ranges in the
regulator framework.
Unfortunately these changes to the core created some breakeage. We
think we fixed it all up but for this reason there are lots of last
minute commits trying to undo the damage"
* tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux: (113 commits)
clk: Only recalculate the rate if needed
Revert "clk: mxs: Fix invalid 32-bit access to frac registers"
clk: qoriq: Add support for the platform PLL
powerpc/corenet: Enable CLK_QORIQ
clk: Replace explicit clk assignment with __clk_hw_set_clk
clk: Add __clk_hw_set_clk helper function
clk: Don't dereference parent clock if is NULL
MIPS: Alchemy: Remove bogus args from alchemy_clk_fgcs_detr
clkdev: Always allocate a struct clk and call __clk_get() w/ CCF
clk: shmobile: div6: Avoid division by zero in .round_rate()
clk: mxs: Fix invalid 32-bit access to frac registers
clk: omap: compile legacy omap3 clocks conditionally
clkdev: Export clk_register_clkdev
clk: Add rate constraints to clocks
clk: remove clk-private.h
pci: xgene: do not use clk-private.h
arm: omap2+ remove dead clock code
clk: Make clk API return per-user struct clk instances
clk: tegra: Define PLLD_DSI and remove dsia(b)_mux
clk: tegra: Add support for the Tegra132 CAR IP block
...
These defconfigs contain the CONFIG_M25P80 symbol, which is now
dependent on the MTD_SPI_NOR symbol. Add CONFIG_MTD_SPI_NOR to satisfy
the new dependency.
At the same time, drop the now-nonexistent CONFIG_MTD_CHAR symbol.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: linuxppc-dev@lists.ozlabs.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Scott Wood <scottwood@freescale.com>
It looks like it's ~4 years since we updated some of these, so do a bulk
update.
Verified that the before and after generated configs are exactly the
same.
Which begs the question why update them? The answer is that it can be
confusing when the stored defconfig drifts too far from the generated
result.
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
As Freescale IFC controller has been moved to driver to driver/memory.
So enable memory driver in powerpc config
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Add CONFIG_NLS_CODEPAGE_437, CONFIG_NLS_CODEPAGE_850,
CONFIG_NLS_ISO8859_1 in default configs for 85xx
and 86xx socs. Required for mounting vfat file-systems
on USB devices
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
The CoreNet Coherency Fabric is part of the memory subsystem on
some Freescale QorIQ chips. It can report coherency violations (e.g.
due to misusing memory that is mapped noncoherent) as well as
transactions that do not hit any local access window, or which hit a
local access window with an invalid target ID.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: Bharat Bhushan <bharat.bhushan@freescale.com>
- remove CONFIG_RTC_DRV_CMOS in corenet32_smp_defconfig(it's unused),
reserve CONFIG_RTC_DRV_CMOS in mpc85xx_defconfig(needed on some CDS boards)
- enable CONFIG_RTC_DRV_DS1307, CONFIG_RTC_DRV_DS1374,
CONFIG_RTC_DRV_DS3232 in mpc85xx_defconfig, mpc85xx_smp_defconfig
- enable RTC support in corenet64_smp_defconfig
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Currently all these boards use the same machine struct and also select
the same kernel options, so it seems a bit of redundant to keep one
separate kernel option for each board. Also update the defconfigs
according to this change.
Signed-off-by: Kevin Hao <haokexin@gmail.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Enable CONFIG_AT803X_PHY to support AR8030/8033/8035 PHY.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
When using recent udev, the /dev node mount requires CONFIG_DEVTMPFS_MOUNT
is enabled in Kernel. The patch enables the option in defconfig of Freescale
QorIQ targets.
Changed defconfig list:
arch/powerpc/configs/85xx/p1023rds_defconfig
arch/powerpc/configs/corenet32_smp_defconfig
arch/powerpc/configs/corenet64_smp_defconfig
arch/powerpc/configs/mpc85xx_smp_defconfig
arch/powerpc/configs/mpc85xx_defconfig
arch/powerpc/configs/mpc83xx_defconfig
Signed-off-by: Zhenhua Luo <zhenhua.luo@freescale.com>
[scottwood@freescale.com: added mpc83xx and non-smp mpc85xx]
Signed-off-by: Scott Wood <scottwood@freescale.com>
While this should be harmless now that distribute_irqs
obeys MPIC_SINGLE_DEST_CPU, there's no reason to enable this
on mpc85xx/mpc86xx since MPIC_SINGLE_DEST_CPU will always be set.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Add support for the Freescale P5040DS Reference Board ("Superhydra"), which
is similar to the P5020DS. Features of the P5040 are listed below, but
not all of these features (e.g. DPAA networking) are currently supported.
Four P5040 single-threaded e5500 cores built
Up to 2.4 GHz with 64-bit ISA support
Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support Up to 1600MT/s
Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
Packet parsing, classification, and distribution (FMAN)
Queue management for scheduling, packet sequencing and
congestion management (QMAN)
Hardware buffer management for buffer allocation and
de-allocation (BMAN)
Cryptography acceleration (SEC 5.0) at up to 40 Gbps SerDes
20 lanes at up to 5 Gbps
Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces
Two 10 Gbps Ethernet MACs
Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Two I2C controllers
Four UARTs
Integrated flash controller supporting NAND and NOR flash
DMA
Dual four channel
Support for hardware virtualization and partitioning enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Yocto (Built by Poky 7.0) 1.2 root filesystems fail to boot,
at least over nfs, with:
Failed to mount /dev: No such device
Configuring DEVTMPFS fixes it.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
run make savedefconfig on fsl defconfigs.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
- Enable NAND support
- Enable CONFIG_PCI_MSI and CONFIG_MMC_SDHCI_OF
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This reverts commit 96cc017c5b.
The P3060 was cancelled before it went into production, so there's no point
in supporting it.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
At least for crypto/IPSec, doing so provides users with a better
performance experience out of the box.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Enable I2C char dev interface for user space testing of I2C controler.
Enable the I2C driver on 64-bit builds (corenet64_smp_defconfig) as it
was missing.
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Commit 7c4b2f09 (powerpc: Update mpc85xx/corenet 32-bit defconfigs)
accidentally disabled the ePAPR byte channel driver in the defconfig for
Freescale CoreNet platforms.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The P3060QDS is a Freescale reference board that hosts the six-core P3060 SOC.
The P3060 Processor combines six e500mc Power Architecture processor cores with
high-performance datapath acceleration architecture(DPAA), CoreNet fabric
infrastructure, as well as network and peripheral interfaces.
P3060QDS Board Overview:
Memory subsystem:
- 2G Bytes unbuffered DDR3 SDRAM SO-DIMM(64bit bus)
- 128M Bytes NOR flash single-chip memory
- 16M Bytes SPI flash
- 8K Bytes AT24C64 I2C EEPROM
Ethernet:
- 4x1G + 4x1G/2.5G Ethernet controllers
- 2xRGMII + 1xMII, three VSC8641 PHYs on board
- Suport multiple Vitesse VSC8234 SGMII Cards in Slot1/2/3
PCIe: Two PCI Express 2.0 controllers/ports
USB: Two USB2.0, USB1(TYPE-A) and USB2(TYPE-AB) on board
I2C: Four I2C controllers
UART: Supports up to four UARTs
RapidIO: Supports two serial RapidIO ports
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Results from updates via make savedefconfig.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
There's only p2041rdb board for official release, but the p2041 silicon
on the board can be converted to p2040 silicon without XAUI and L2 cache
function, then the board becomes p2040rdb board. so we use the file name
p2041_rdb.c to handle P2040RDB board and P2041RDB board which is also
consistent with the board name under U-Boot.
During the rename we make few other minor changes to the device tree:
* Move USB phy setting into p2041si.dtsi as its SoC not board defined
* Convert PCI clock-frequency to decimal to be more readable
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
corenet based SoCs have SEC4 h/w, so enable the SEC4 driver,
caam, and the algorithms it supports, and disable the
SEC2/3 driver, talitos.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
P2040RDB Specification:
-----------------------
2Gbyte unbuffered DDR3 SDRAM SO-DIMM(64bit bus)
128 Mbyte NOR flash single-chip memory
256 Kbit M24256 I2C EEPROM
16 Mbyte SPI memory
SD connector to interface with the SD memory card
dTSEC1: connected to the Vitesse SGMII PHY (VSC8221)
dTSEC2: connected to the Vitesse SGMII PHY (VSC8221)
dTSEC3: connected to the Vitesse SGMII PHY (VSC8221)
dTSEC4: connected to the Vitesse RGMII PHY (VSC8641)
dTSEC5: connected to the Vitesse RGMII PHY (VSC8641)
I2C1: Real time clock, Temperature sensor
I2C2: Vcore Regulator, 256Kbit I2C Bus EEPROM
SATA: Lanes C and Land D of Bank2 are connected to two SATA connectors
UART: supports two UARTs up to 115200 bps for console
USB 2.0: connected via a internal UTMI PHY to two TYPE-A interfaces
PCIe:
- Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT1
- Lanes C and Land D of Bank2 are connected to one x4 PCIe SLOT2
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
CONFIG_PPC_EPAPR_HV_BYTECHAN adds support for the Freescale hypervisor
byte channel tty driver.
CONFIG_VIRT_DRIVERS and CONFIG_FSL_HV_MANAGER add support for the Freescale
hypervisor management driver.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The e500mc and e5500 based cores are only available on corenet based
SoCs. We use this name for the P204x, P3040, P4040, P4080, P50x0 SoCs
and any future processors in these families.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Shengzhou Liu