Commit Graph

737168 Commits

Author SHA1 Message Date
Linus Walleij 76a16885a7 pinctrl: sh-pfc: Updates for v4.17 (take two)
- Add USB pin groups on R-Car M3-N,
   - Add support for the new R-Car V3H SoC,
   - Add EtherAVB pin groups on R-Car V3M,
   - Miscellaneous fixes and cleanups.
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Merge tag 'sh-pfc-for-v4.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v4.17 (take two)

  - Add USB pin groups on R-Car M3-N,
  - Add support for the new R-Car V3H SoC,
  - Add EtherAVB pin groups on R-Car V3M,
  - Miscellaneous fixes and cleanups.
2018-03-23 03:36:48 +01:00
Ulrich Hecht a6fff41f41 pinctrl: sh-pfc: r8a77995: Deduplicate VIN4 pin definitions
Use union vin_data and VIN_DATA_PIN_GROUP() to reduce redundancies
in pin definitions.

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-03-21 18:25:48 +01:00
Ulrich Hecht a5c2949ff7 pinctrl: sh-pfc: r8a7796: Deduplicate VIN4 pin definitions
Use union vin_data and VIN_DATA_PIN_GROUP() to reduce redundancies
in pin definitions.

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-03-21 18:25:48 +01:00
Ulrich Hecht 9942a5b529 pinctrl: sh-pfc: r8a7795: Deduplicate VIN4 pin definitions
Use union vin_data and VIN_DATA_PIN_GROUP() to reduce redundancies
in pin definitions.

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-03-21 18:25:47 +01:00
Ulrich Hecht 4fd82963e1 pinctrl: sh-pfc: r8a77995: Correct VIN4 18-bit pins
RGB666 has a pin assignment that differs from the other formats.

Fixes: fbd452aeb4 ("pinctrl: sh-pfc: r8a77995: Add VIN4 pins, groups and function")
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-03-21 18:25:22 +01:00
Ulrich Hecht a66b68ba7f pinctrl: sh-pfc: r8a7796: Correct VIN4 18-bit pins
RGB666 has a pin assignment that differs from the other formats.

Fixes: 8db6cbabac ("pinctrl: sh-pfc: r8a7796: Add VIN4, VIN5 pins, groups and functions")
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-03-21 18:25:01 +01:00
Ulrich Hecht b538dc5bbb pinctrl: sh-pfc: r8a7795: Correct VIN4 18-bit pins
RGB666 has a pin assignment that differs from the other formats.

Fixes: 6b4de40810 ("pinctrl: sh-pfc: r8a7795: Add VIN4, VIN5 pins, groups and functions")
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-03-21 18:24:16 +01:00
Geert Uytterhoeven 3b047a9597 pinctrl: sh-pfc: r8a77995: Rename EtherAVB "mdc" pin group to "mdio"
On other Renesas SoCs, the pin group for the MDIO bus is named "mdio"
instead of "mdc".  Fix the inconsistency, while retaining backwards
compatibility with old DTBs using a pin group alias.

Fixes: 66abd968d0 ("pinctrl: sh-pfc: r8a77995: Add EthernetAVB pins, groups and functions")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2018-03-21 18:18:32 +01:00
Geert Uytterhoeven f7ce295cfd pinctrl: sh-pfc: r8a77965: Rename EtherAVB "mdc" pin group to "mdio"
On other Renesas SoCs, the pin group for the MDIO bus is named "mdio"
instead of "mdc".  Fix the inconsistency, while retaining backwards
compatibility with old DTBs using a pin group alias.

Fixes: fa3e8b71b9 ("pinctrl: sh-pfc: r8a77965: Add EtherAVB groups/functions")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2018-03-21 18:18:30 +01:00
Geert Uytterhoeven 350aba9a74 pinctrl: sh-pfc: r8a7796: Rename EtherAVB "mdc" pin group to "mdio"
On other Renesas SoCs, the pin group for the MDIO bus is named "mdio"
instead of "mdc".  Fix the inconsistency, while retaining backwards
compatibility with old DTBs using a pin group alias.

Fixes: 41397032c4 ("pinctrl: sh-pfc: r8a7796: Add group for AVB MDIO and MII pins")
Fixes: 9c99a63ec7 ("pinctrl: sh-pfc: r8a7796: Add EtherAVB pins, groups and functions")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2018-03-21 18:18:25 +01:00
Geert Uytterhoeven 24cfe1a970 pinctrl: sh-pfc: r8a7795-es1: Rename EtherAVB "mdc" pin group to "mdio"
On other Renesas SoCs, the pin group for the MDIO bus is named "mdio"
instead of "mdc".  Fix the inconsistency, while retaining backwards
compatibility with old DTBs using a pin group alias.

Fixes: b25719eb93 ("pinctrl: sh-pfc: r8a7795: Add group for AVB MDIO and MII pins")
Fixes: 819fd4bfcc ("pinctrl: sh-pfc: r8a7795: add EtherAVB support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2018-03-21 18:18:23 +01:00
Geert Uytterhoeven cbe0dd9ad5 pinctrl: sh-pfc: r8a7795: Rename EtherAVB "mdc" pin group to "mdio"
On other Renesas SoCs, the pin group for the MDIO bus is named "mdio"
instead of "mdc".  Fix the inconsistency, while retaining backwards
compatibility with old DTBs using a pin group alias.

Fixes: 30c078de6f ("pinctrl: sh-pfc: r8a7795: Add EtherAVB pins, groups and function")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2018-03-21 18:18:18 +01:00
Geert Uytterhoeven 43a51cd5d6 pinctrl: sh-pfc: Add SH_PFC_PIN_GROUP_ALIAS()
Add a macro to refer to another pin group with a different name.

This will be used to rename wrongly-named pin groups, while retaining
backwards compatibility with old DTBs.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2018-03-21 18:18:05 +01:00
Geert Uytterhoeven 66e9fe1ec7 pinctrl: sh-pfc: r8a7790: Add missing TX_ER pin to avb_mii group
The pin controller drivers for all R-Car Gen2 SoCs have entries for the
EtherAVB TX_ER pins in their EtherAVB MII groups, except on R-Car H2.

Add the missing pin to restore consistency.

Note that technically TX_ER is an optional signal in the MII bus, and
thus could have its own group, but this is currently not supported by
any R-Car Gen2 pin controller driver.

Fixes: 19ef697d1e ("sh-pfc: r8a7790: add EtherAVB pin groups")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-03-21 18:16:51 +01:00
Sergei Shtylyov b3cbd8a567 pinctrl: sh-pfc: r8a77970: Add EtherAVB pin groups
Add the EtherAVB pin groups to the R8A77970 PFC driver.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-03-14 14:39:52 +01:00
Sergei Shtylyov f59125248a pinctrl: sh-pfc: Add R8A77980 PFC support
Add the PFC support for the R8A77980 SoC including pin groups for some
on-chip devices such as AVB, CAN-FD, GETHER, [H]SCIF, I2C, INTC-EX, MMC,
MSIOF, PWM, and VIN...

Based on the original (and large) patch by Vladimir Barinov.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-03-09 13:55:30 +01:00
Sergei Shtylyov c21a3e30e8 pinctrl: sh-pfc: Add PORT_GP_CFG_25() helper macro
They follow the style of the existing PORT_GP_CFG_<n>() macros and
will be used by a follow-up patch for the R8A77980 SoC.

Based on the original (and large) patch by Vladimir Barinov.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-03-09 13:55:26 +01:00
Takeshi Kihara c490b28f36 pinctrl: sh-pfc: r8a77965: Add USB3.0 host pins, groups and functions
This patch adds USB30 (USB3.0 host) pin, group and function to
the R8A77965 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-03-05 11:03:47 +01:00
Takeshi Kihara 0d75f8dae3 pinctrl: sh-pfc: r8a77965: Add USB2.0 host pins, groups and functions
This patch adds USB{0,1} (USB2.0 host) pins, groups and functions to
the R8A77965 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-03-05 11:02:32 +01:00
Manivannan Sadhasivam 2ba08d75eb dt-bindings: pinctrl: Add bindings for Actions S900 SoC
Add pinctrl bindings for Actions Semi S900 SoC

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-03-02 14:09:38 +01:00
Linus Walleij e024484a86 pinctrl: sh-pfc: Updates for v4.17
- Add DU and VIN pin groups on R-Car D3,
   - Add HDMI, TMU, and VIN pin groups on R-Car H3 and M3-W,
   - Add support for the new R-Car M3-N SoC,
   - Small fixes and cleanups.
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Merge tag 'sh-pfc-for-v4.17-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v4.17

  - Add DU and VIN pin groups on R-Car D3,
  - Add HDMI, TMU, and VIN pin groups on R-Car H3 and M3-W,
  - Add support for the new R-Car M3-N SoC,
  - Small fixes and cleanups.
2018-03-02 13:38:12 +01:00
Richard Fitzgerald 8b1b2dc7b4 pinctrl: core: Add missing EXPORT on pinctrl_register_mappings
Systems that don't have devicetree need pinctrl_register_mappings.
It should be EXPORT_SYMBOL_GPL so that it can be called from
pinctrl drivers built as modules.

Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-03-02 11:05:35 +01:00
Martin Blumenstingl 55af415b42 pinctrl: meson: meson8b: fix requesting GPIOs greater than GPIOZ_3
Meson8b is a cost reduced variant of the Meson8 SoC. It's package size
is smaller than Meson8.
Unfortunately there are a few key differences which cannot be seen
without close inspection of the code and the public S805 datasheet:
- the GPIOX bank is missing the GPIOX_12, GPIOX_13, GPIOX_14 and
  GPIOX_15 GPIOs
- the GPIOY bank is missing the GPIOY_2, GPIOY_4, GPIOY_5, GPIOY_15 and
  GPIOY_16 GPIOs
- the GPIODV bank is missing all GPIOs except GPIODV_9, GPIODV_24,
  GPIODV_25, GPIODV_26, GPIODV_27, GPIODV_28 and GPIODV_29
- the GPIOZ bank is missing completely
- there is a new GPIO bank called "DIF"

This means that Meson8b only has 83 actual GPIO lines. Without any holes
there would be 130 GPIO lines in total (120 are inherited from Meson8
plus 10 new from the DIF bank).

GPIOs greater GPIOZ_3 (whose ID is 83 - as a reminder: this is exactly
the number of actual GPIO lines on Meson8b and also the value of
meson8b_cbus_pinctrl_data.num_pins) cannot berequested. Using CARD_6
(which used ID 100 prior to this patch, "base of the GPIO controller was
382) as an example:
$ echo 482 > /sys/class/gpio/export
export_store: invalid GPIO 482

This removes all non-existing pins from to dt-bindings header file
(include/dt-bindings/gpio/meson8b-gpio.h). This allows us to have a
consecutive numbering for the GPIO #defines (GPIOY_2 doesn't exist for
example, so previously the GPIOY_3 ID was "GPIOY_1 + 2", after this
patch it is "GPIOY_1 + 1"). As a nice side-effect this means that we get
compile-time (instead of runtime) errors if Meson8b .dts uses a pin that
only exists on Meson8.

Additionally the pinctrl-meson8b driver has to be updated to handle this
new GPIO numbering. By default a struct meson_bank only handles GPIO
banks where the pins are numbered consecutively because it calculates
the bit offsets based on the GPIO IDs.
This is solved by  taking the original BANK() definition and splitting it
into consecutive subsets (X0..11 and X16..21). The bit offsets for each
new bank includes the skipped GPIOs (the definition of the "X0..11" bank
is identical to the old "X" bank apart from the "last IRQ" field, the
definition of the new, split "X16..21" bank takes the original "X" bank
and adds 16 - the start of the new split bank - to the "first IRQ",
pullen bit, pull bit, dir bit, out bit and in bit).

Commit 984cffdeae ("pinctrl: Fix gpio/pin mapping for Meson8b")
fixed the same issue by setting "ngpio" (of the gpio_chip) to 130.
Unfortunately this broke in db80f0e158 ("pinctrl: meson: get rid of
unneeded domain structures").
The solution from this patch was considered to be better than the
previous attempt at fixing this because it provides compile-time error
checking for the GPIOs that exist on Meson8 but don't exist on Meson8b.

The following pins were tested on an Odroid-C1 using the sysfs GPIO
interface checking that their value (high or low) could be read:
- GPIOX_0, GPIOX_1, GPIOX_2, GPIOX_3, GPIOX_4, GPIOX_5, GPIOX_6,
  GPIOX_7, GPIOX_8, GPIOX_9, GPIOX_10, GPIOX_11, GPIOX_18, GPIOX_19,
  GPIOX_20, GPIOX_21
- GPIOY_3, GPIOY_7, GPIOY_8
(some of these had to be pulled up because they were low by default,
others were high by default so these had to be pulled down)

Reported-by: Linus Lüssing <linus.luessing@c0d3.blue>
Suggested-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-03-02 10:46:42 +01:00
Richard Fitzgerald b89405b610 pinctrl: devicetree: Fix dt_to_map_one_config handling of hogs
When dt_to_map_one_config() is called with a pinctrl_dev passed
in, it should only be using this if the node being looked up
is a hog. The code was always using the passed pinctrl_dev
without checking whether the dt node referred to it.

A pin controller can have pinctrl-n dependencies on other pin
controllers in these cases:

- the pin controller hardware is external, for example I2C, so
  needs other pin controller(s) to be setup to communicate with
  the hardware device.

- it is a child of a composite MFD so its of_node is shared with
  the parent MFD and other children of that MFD. Any part of that
  MFD could have dependencies on other pin controllers.

Because of this, dt_to_map_one_config() can't assume that if it
has a pinctrl_dev passed in then the node it looks up must be
a hog. It could be a reference to some other pin controller.

Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-03-02 09:41:21 +01:00
Sean Wang 536836d32c dt-bindings: pinctrl: mediatek: add bindings for I2C2 and SPI2 on MT7623
Add missing pinctrl binding about I2C2 and SPI2 which would be used in
devicetree related files.

Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-03-02 08:44:24 +01:00
Sean Wang fc471710c6 dt-bindings: pinctrl: mediatek: use - instead of _ in examples
It should be good that no use "_" is in examples. Consequently,
those nodes in certain files which have an inappropriate name containing
"_" are all being replaced with "-".

Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-gpio@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-03-02 08:42:59 +01:00
Radoslaw Pietrzyk 430a2a5945 pinctrl: stm32: Optimizes and enhances stm32gpio irqchip
- removes unneeded irq_chip.irq_eoi callback
- adds irq_chip.irq_set_wake callback for possible
  in the future GPIO wakeup
- adds irq_chip.irq_ack callback

Signed-off-by: Radoslaw Pietrzyk <radoslaw.pietrzyk@gmail.com>
Reviewed-by: Ludovic Barre <ludovic.barre@st.com>
Tested-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-03-02 08:40:31 +01:00
Niklas Cassel 928af22477 pinctrl: artpec6: dt: add smaller groups for uarts
Add group configuration for uarts that are cut down
variants, the standard being full, i.e. all signals,
flow control, i.e. rx/tx and cts/rts, and rx/tx only.

This allows us to be more precise in which pins we're
actually using.

Unfortunately the existing naming scheme leaves things
to be desired, e.g. uart3grp0 means RX/TX and CTS/RTS,
yet uart0grp0 means all pins.
Since the exising suffixes have different meaning for
different uarts, and the fact that we cannot change
the name of existing groups, makes it hard to use a
descriptive name for the newly added groups.

Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-03-02 08:40:31 +01:00
Niklas Cassel 7e065fb9cc pinctrl: artpec6: dt: add missing pin group uart5nocts
Add missing pin group uart5nocts (all pins except cts), which has been
supported by the artpec6 pinctrl driver since its initial submission.

Fixes: 00df0582ea ("pinctrl: Add pincontrol driver for ARTPEC-6 SoC")
Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-03-02 08:40:21 +01:00
Jesper Nilsson 41e009b2b5 pinctrl: artpec-6: Add smaller groups for uarts
Add group configuration for uarts that are cut down
variants, the standard being full, i.e. all signals,
flow control, i.e. rx/tx and cts/rts, and rx/tx only.

This allows us to be more precise in which pins we're
actually using.

Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-03-01 17:04:09 +01:00
James Hogan 4a7cba71ca pinctrl: Drop TZ1090 drivers
Now that arch/metag/ has been removed, along with TZ1090 SoC support,
remove the TZ1090 pinctrl drivers. They are of no value without the
architecture and SoC platform code.

Signed-off-by: James Hogan <jhogan@kernel.org>
Cc: linux-gpio@vger.kernel.org
Cc: linux-metag@vger.kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-03-01 15:34:15 +01:00
Takeshi Kihara a8ab4f2bd8 pinctrl: sh-pfc: r8a77965: Add support for INTC-EX IRQ pins
Most pins on the R8A77965 SoC can be configured in GPIO mode for
interrupt and GPIO functionality, while a couple of them can also
be routed to the INTC-EX hardware block (formerly known as IRQC).

On R8A77965 the INTC-EX hardware handles pins IRQ0 -> IRQ5 and
this patch adds support for them to the PFC driver as "intc_ex_irqN".

Based on a similar patch for the R8A7795 PFC driver by Magnus Damm
<damm+renesas@opensource.se>.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-28 09:17:54 +01:00
Ulrich Hecht fbd452aeb4 pinctrl: sh-pfc: r8a77995: Add VIN4 pins, groups and function
This patch adds VIN4 pins, groups and function for the
R8A77995 (D3) SoC.

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-26 10:19:03 +01:00
Ulrich Hecht 6b4de40810 pinctrl: sh-pfc: r8a7795: Add VIN4, VIN5 pins, groups and functions
This patch adds VIN4 and VIN5 pins, groups and functions for the
R8A7795 SoC.

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-26 10:19:03 +01:00
Ulrich Hecht 8db6cbabac pinctrl: sh-pfc: r8a7796: Add VIN4, VIN5 pins, groups and functions
This patch adds VIN4 and VIN5 pins, groups and functions for the
R8A7796 SoC.

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-26 10:19:03 +01:00
Phil Reid fa2b7fae84 pinctrl: mcp23s08: add open drain configuration for irq output
The mcp23s08 series device can be configured for wired and interrupts
using an external pull-up and open drain output via the IOCON_ODR bit.
And "drive-open-drain" property to enable this.

Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: Phil Reid <preid@electromag.com.au>
Reviewed-by: Jan Kundrát <jan.kundrat@cesnet.cz>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-02-22 16:08:59 +01:00
Phil Reid 39aba4714d dt-bindings: pinctrl: mcp23s08: add documentation for drive-open-drain
This flag set the mcp23s08 device irq type to open drain active low.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Phil Reid <preid@electromag.com.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-02-22 16:06:05 +01:00
Phil Reid d9f50048dc pinctrl: mcp23s08: fix probing of mcp23s18
one_regmap_config is always null if mcp type is MCP_TYPE_S18.
Remove the null check so that the mcp23s18 will probe.

Fixes: 1781af563a ("pinctrl: mcp23s08: spi: Fix duplicate pinctrl debugfs entries")
Signed-off-by: Phil Reid <preid@electromag.com.au>
Reviewed-by: Jan Kundrát <jan.kundrat@cesnet.cz>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-02-22 16:04:26 +01:00
Daniel Kurtz 12b10f47e5 pinctrl/amd: add get_direction handler
On boot, gpiochip_add_data() initializes the FLAG_IS_OUT bit in
desc->flags iff its gpio_chip does not have ->direction_input() handler,
else it is initialized to 0, which implies the GPIO is an "input".

Later, the sysfs "direction" handler will use gpiod_get_direction() to
get the current direction, but if no ->get_direction() handler is
installed, the result will just be the current (initial) value of flags,
which will always be OUT irregardless of the initial register value.

Add a get_direction() handler to pinctrl-amd to fix this and always
provide the correct value for direction.

Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-02-22 15:52:19 +01:00
Andy Shevchenko b5520891a3 pinctrl: Re-use DEFINE_SHOW_ATTRIBUTE() macro
...instead of open coding file operations followed by custom ->open()
callbacks per each attribute.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-02-22 15:36:03 +01:00
Colin Ian King ce3e7f0ee9 pinctrl: ocelot: make function ocelot_pinctrl_probe static
The function ocelot_pinctrl_probe is local to the source and does not
need to be in global scope, so make it static.

Cleans up sparse warning:
drivers/pinctrl/pinctrl-ocelot.c:465:5: warning: symbol
'ocelot_pinctrl_probe' was not declared. Should it be static?

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-02-22 14:02:18 +01:00
Jacopo Mondi fa3e8b71b9 pinctrl: sh-pfc: r8a77965: Add EtherAVB groups/functions
Add EtherAVB groups and functions definitions for R-Car M3-N.

Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-20 19:33:02 +01:00
Jacopo Mondi 58cfd7f37e pinctrl: sh-pfc: r8a77965: Add SCIFs groups/functions
Add SCIF[0-5] groups and pin function definitions for R-Car M3-N.

Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-20 19:32:59 +01:00
Jacopo Mondi 490e687eb8 pinctrl: sh-pfc: Initial R-Car M3-N support
Add initial PFC support for R-Car M3-N (r8a77965) SoC.
No groups or functions defined, just pin and registers enumeration.

Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-20 19:32:58 +01:00
Takeshi Kihara 74965de1ca pinctrl: sh-pfc: r8a7796: Add TMU pins, groups and functions
This patch adds TMU TCLK{1,2} pins, groups and functions to
the R8A7796 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-20 19:03:29 +01:00
Takeshi Kihara f0442cf27c pinctrl: sh-pfc: r8a7795-es1: Add TMU pins, groups and functions
This patch adds TMU TCLK{1,2} pins, groups and functions to
the R8A7795 ES1.x SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-20 19:03:26 +01:00
Takeshi Kihara edcc14c82d pinctrl: sh-pfc: r8a7795: Add TMU pins, groups and functions
This patch adds TMU TCLK{1,2} pins, groups and functions to
the R8A7795 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-20 19:03:23 +01:00
Takeshi Kihara 71c236adf0 pinctrl: sh-pfc: r8a7796: Add HDMI pins, groups and functions
This patch adds HDMI0 CEC pin, group and function to the R8A7796 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-20 19:03:18 +01:00
Takeshi Kihara 1240414859 pinctrl: sh-pfc: r8a7795-es1: Add HDMI pins, groups and functions
This patch adds HDMI0 CEC pin, group and function to
the R8A7795 ES1.x SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[uli: fixed typo in comment]
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-20 19:03:15 +01:00
Takeshi Kihara 5722110e2f pinctrl: sh-pfc: r8a7795: Add HDMI pins, groups and functions
This patch adds HDMI0 CEC pin, group and function to the R8A7795 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[uli: fixed typo in comment]
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-20 19:02:56 +01:00