Commit Graph

3860 Commits

Author SHA1 Message Date
Nathan Chancellor b40ac08ff8 pinctrl: bcm2835: Use define directive for BCM2835_PINCONF_PARAM_PULL
Clang warns when one enumerated type is implicitly converted to another:

drivers/pinctrl/bcm/pinctrl-bcm2835.c:707:40: warning: implicit
conversion from enumeration type 'enum bcm2835_pinconf_param' to
different enumeration type 'enum pin_config_param' [-Wenum-conversion]
        configs[0] = pinconf_to_config_packed(BCM2835_PINCONF_PARAM_PULL, pull);
                     ~~~~~~~~~~~~~~~~~~~~~~~~ ^~~~~~~~~~~~~~~~~~~~~~~~~~
1 warning generated.

It is expected that pinctrl drivers can extend pin_config_param because
of the gap between PIN_CONFIG_END and PIN_CONFIG_MAX so this conversion
isn't an issue. Most drivers that take advantage of this define the
PIN_CONFIG variables as constants, rather than enumerated values. Do the
same thing here so that Clang no longer warns.

Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-11-09 10:22:28 +01:00
Nathan Chancellor 957063c924 pinctrl: sprd: Use define directive for sprd_pinconf_params values
Clang warns when one enumerated type is implicitly converted to another:

drivers/pinctrl/sprd/pinctrl-sprd.c:845:19: warning: implicit conversion
from enumeration type 'enum sprd_pinconf_params' to different
enumeration type 'enum pin_config_param' [-Wenum-conversion]
        {"sprd,control", SPRD_PIN_CONFIG_CONTROL, 0},
        ~                ^~~~~~~~~~~~~~~~~~~~~~~
drivers/pinctrl/sprd/pinctrl-sprd.c:846:22: warning: implicit conversion
from enumeration type 'enum sprd_pinconf_params' to different
enumeration type 'enum pin_config_param' [-Wenum-conversion]
        {"sprd,sleep-mode", SPRD_PIN_CONFIG_SLEEP_MODE, 0},
        ~                   ^~~~~~~~~~~~~~~~~~~~~~~~~~

It is expected that pinctrl drivers can extend pin_config_param because
of the gap between PIN_CONFIG_END and PIN_CONFIG_MAX so this conversion
isn't an issue. Most drivers that take advantage of this define the
PIN_CONFIG variables as constants, rather than enumerated values. Do the
same thing here so that Clang no longer warns.

Link: https://github.com/ClangBuiltLinux/linux/issues/138
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Reviewed-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-11-09 10:20:47 +01:00
Nathan Chancellor 1f60652dd5 pinctrl: max77620: Use define directive for max77620_pinconf_param values
Clang warns when one enumerated type is implicitly converted to another:

drivers/pinctrl/pinctrl-max77620.c:56:12: warning: implicit conversion
from enumeration type 'enum max77620_pinconf_param' to different
enumeration type 'enum pin_config_param' [-Wenum-conversion]
                .param = MAX77620_ACTIVE_FPS_SOURCE,
                         ^~~~~~~~~~~~~~~~~~~~~~~~~~

It is expected that pinctrl drivers can extend pin_config_param because
of the gap between PIN_CONFIG_END and PIN_CONFIG_MAX so this conversion
isn't an issue. Most drivers that take advantage of this define the
PIN_CONFIG variables as constants, rather than enumerated values. Do the
same thing here so that Clang no longer warns.

Link: https://github.com/ClangBuiltLinux/linux/issues/139
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-11-09 10:02:22 +01:00
Brian Masney 149a960472 pinctrl: qcom: spmi-gpio: fix gpio-hog related boot issues
When attempting to setup up a gpio hog, device probing would repeatedly
fail with -EPROBE_DEFERED errors. It was caused by a circular dependency
between the gpio and pinctrl frameworks. If the gpio-ranges property is
present in device tree, then the gpio framework will handle the gpio pin
registration and eliminate the circular dependency.

See Christian Lamparter's commit a86caa9ba5 ("pinctrl: msm: fix
gpio-hog related boot issues") for a detailed commit message that
explains the issue in much more detail. The code comment in this commit
came from Christian's commit.

Signed-off-by: Brian Masney <masneyb@onstation.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-11-09 09:56:48 +01:00
Colin Ian King 78bf386daf pinctrl: mediatek: clean up indentation issues, add missing tab
Trivial fix to clean up indentation issues, add one level of
indentation on two if statements.

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-11-09 09:54:54 +01:00
Andy Shevchenko 166d6e2adc pinctrl: baytrail: Code formatting fixes
Remove comma from terminator line to allow compiler fail
in case an entry has been put in a wrong place by any weird reason.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2018-11-08 17:16:41 +02:00
Andy Shevchenko 5c20a0227e pinctrl: icelake: Code formatting fixes
Remove comma from terminator line to allow compiler fail
in case an entry has been put in a wrong place by any weird reason.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2018-11-08 17:16:41 +02:00
Andy Shevchenko 3d5d096ec9 pinctrl: cannonlake: Code formatting fixes
Remove comma from terminator line to allow compiler fail
in case an entry has been put in a wrong place by any weird reason.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2018-11-08 17:16:41 +02:00
Andy Shevchenko 6463955837 pinctrl: geminilake: Code formatting fixes
Remove comma from terminator line to allow compiler fail
in case an entry has been put in a wrong place by any weird reason.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2018-11-08 17:16:41 +02:00
Andy Shevchenko cd06a5e7f7 pinctrl: broxton: Code formatting fixes
Remove comma from terminator line to allow compiler fail
in case an entry has been put in a wrong place by any weird reason.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2018-11-08 17:16:40 +02:00
Andy Shevchenko 1068934c8f pinctrl: lewisburg: Replace acpi.h with mod_devicetable.h
There is no need to include acpi.h since driver doesn't use anything from it
except the propagation of mod_devicetable.h.

Include latter directly instead.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2018-11-08 17:16:40 +02:00
Andy Shevchenko c73e7ad6f6 pinctrl: denverton: Replace acpi.h with mod_devicetable.h
There is no need to include acpi.h since driver doesn't use anything from it
except the propagation of mod_devicetable.h.

Include latter directly instead.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2018-11-08 17:16:40 +02:00
Andy Shevchenko 35bf500769 pinctrl: cedarfork: Replace acpi.h with mod_devicetable.h
There is no need to include acpi.h since driver doesn't use anything from it
except the propagation of mod_devicetable.h.

Include latter directly instead.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2018-11-08 17:16:40 +02:00
Andy Shevchenko f27a0d9ad3 pinctrl: merrifield: include bits.h instead of bitops.h
The reason of including <linux/bitops.h> here is just for BIT() and Co macros.

Since commit 8bd9cb51da

  ("... Move some macros from <linux/bitops.h> to a new <linux/bits.h> file"),

<linux/bits.h> is enough for such compile-time macros.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2018-11-08 17:16:40 +02:00
Andy Shevchenko 0dd519e378 pinctrl: intel: Unexport intel_pinctrl_probe()
Since there are no more users, unexport it and make static.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2018-11-08 17:16:40 +02:00
Andy Shevchenko c34c177508 pinctrl: sunrisepoint: Get rid of unneeded ->probe() stub
The local ->probe() stub does nothing except calling
a generic Intel pin control probe function. Thus,
it's not needed and generic function may be called directly.

Convert the driver accordingly.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2018-11-08 17:16:39 +02:00
Andy Shevchenko ec7cf5c5c8 pinctrl: icelake: Get rid of unneeded ->probe() stub
The local ->probe() stub does nothing except calling
a generic Intel pin control probe function. Thus,
it's not needed and generic function may be called directly.

Convert the driver accordingly.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2018-11-08 17:16:39 +02:00
Andy Shevchenko 9080e77bc3 pinctrl: cannonlake: Get rid of unneeded ->probe() stub
The local ->probe() stub does nothing except calling
a generic Intel pin control probe function. Thus,
it's not needed and generic function may be called directly.

Convert the driver accordingly.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2018-11-08 17:16:39 +02:00
Andy Shevchenko bdc2bc72b6 pinctrl: broxton: Get rid of unneeded ->probe() stub
The local ->probe() stub does nothing except calling
a generic Intel pin control probe function. Thus,
it's not needed and generic function may be called directly.

Convert the driver accordingly.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2018-11-08 17:16:39 +02:00
Andy Shevchenko 883a60dfda pinctrl: lewisburg: Get rid of unneeded ->probe() stub
The local ->probe() stub does nothing except calling
a generic Intel pin control probe function. Thus,
it's not needed and generic function may be called directly.

Convert the driver accordingly.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2018-11-08 17:16:39 +02:00
Andy Shevchenko 185d33c2a2 pinctrl: denverton: Get rid of unneeded ->probe() stub
The local ->probe() stub does nothing except calling
a generic Intel pin control probe function. Thus,
it's not needed and generic function may be called directly.

Convert the driver accordingly.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2018-11-08 17:16:39 +02:00
Andy Shevchenko 6ad3d49576 pinctrl: cedarfork: Get rid of unneeded ->probe() stub
The local ->probe() stub does nothing except calling
a generic Intel pin control probe function. Thus,
it's not needed and generic function may be called directly.

Convert the driver accordingly.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2018-11-08 17:16:38 +02:00
Wolfram Sang cb035d7469 pinctrl: intel: simplify getting .driver_data
We should get 'driver_data' from 'struct device' directly. Going via
platform_device is an unneeded step back and forth.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2018-11-08 17:16:33 +02:00
Wolfram Sang a4833c6059 pinctrl: cherryview: simplify getting .driver_data
We should get 'driver_data' from 'struct device' directly. Going via
platform_device is an unneeded step back and forth.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2018-11-08 17:16:27 +02:00
Wolfram Sang d481de4730 pinctrl: baytrail: simplify getting .driver_data
We should get 'driver_data' from 'struct device' directly. Going via
platform_device is an unneeded step back and forth.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2018-11-08 17:15:33 +02:00
Fabrizio Castro b06a8b4387 pinctrl: sh-pfc: r8a77470: Add SDHI support
Add SH_PFC_PIN_CFG_IO_VOLTAGE definition for the SDHI pins
capable of switching voltage, also add pin groups and functions
for SDHI0 and SDHI1. Please note that with the RZ/G1C only 1
bit of the POC Control Register is used to control each interface.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-06 09:20:26 +01:00
Geert Uytterhoeven 50f3f2d73e pinctrl: sh-pfc: Reduce kernel size for narrow VIN channels
Some VIN channels support less than 24 lanes.  As union vin_data always
consumes space for 24 lanes, this wastes memory.

Hence introduce new smaller unions vin_data12 and vin_data16, to
accommodate VIN channels with only 12 or 16 lanes.

This reduces the static pin controller driver size by 320 bytes for
R-Car V2H, and by 96 bytes for R-Car E2.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2018-11-06 09:20:26 +01:00
Takeshi Kihara ccb44a8a5b pinctrl: sh-pfc: r8a77990: Add Audio SSI pins, groups and functions
This patch adds Audio SSI{0,1,2,3,4,5,6,7,8,9} pins, groups
and functions to the R8A77990 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[simon: rebase]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-06 09:20:26 +01:00
Takeshi Kihara 4c833b2fa5 pinctrl: sh-pfc: r8a77990: Add Audio clock pins, groups and functions
This patch adds AUDIO_CLK{A,B,C}, AUDIO_CLKOUT, AUDIO_CLKOUT{1,2,3}
pins, groups and functions to the R8A77990 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[simon: rebase]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-06 09:20:26 +01:00
Fabrizio Castro f743f017b7 pinctrl: sh-pfc: r8a77470: Add QSPI1 pin groups
Add QSPI1 pin groups and function to the RZ/G1C (a.k.a. R8A77470)
pinctrl driver.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-05 13:43:40 +01:00
Fabrizio Castro 610d662ac3 pinctrl: sh-pfc: r8a77470: Add VIN pin groups
Add VIN[01] pin groups and functions to the RZ/G1C (a.k.a.
R8A77470) pinctrl driver.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-05 13:43:38 +01:00
Fabrizio Castro 5c9258bca9 pinctrl: sh-pfc: r8a77470: Add DU1 pin groups
Add DU1 pin groups and function to the RZ/G1C (a.k.a. R8A77470)
pinctrl driver.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-05 13:43:36 +01:00
Fabrizio Castro 80ef7d0910 pinctrl: sh-pfc: r8a77470: Add remaining I2C pin groups
This patch adds I2C[0123] groups and functions to the RZ/G1C
(a.k.a. R8A77470) pinctrl driver.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-05 13:43:17 +01:00
Lukas Wunner 3c7b30f704 pinctrl: bcm2835: Use raw spinlock for RT compatibility
The BCM2835 pinctrl driver acquires a spinlock in its ->irq_enable,
->irq_disable and ->irq_set_type callbacks.  Spinlocks become sleeping
locks with CONFIG_PREEMPT_RT_FULL=y, therefore invocation of one of the
callbacks in atomic context may cause a hard lockup if at least two GPIO
pins in the same bank are used as interrupts.  The issue doesn't occur
with just a single interrupt pin per bank because the lock is never
contended.  I'm experiencing such lockups with GPIO 8 and 28 used as
level-triggered interrupts, i.e. with ->irq_disable being invoked on
reception of every IRQ.

The critical section protected by the spinlock is very small (one bitop
and one RMW of an MMIO register), hence converting to a raw spinlock
seems a better trade-off than converting the driver to threaded IRQ
handling (which would increase latency to handle an interrupt).

Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Acked-by: Julia Cartwright <julia@ni.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-11-05 09:33:33 +01:00
A.s. Dong 623f788d0e pinctrl: imx: add imx8qxp driver
MX8QXP contains a system controller that is responsible for controlling
the pad setting of the IPs that are present. Communication between the
host processor running an OS and the system controller happens through
a SCU protocol. This patch adds the SCU based MX8QXP pinctrl driver.

Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-11-05 09:33:32 +01:00
A.s. Dong b96eea718b pinctrl: fsl: add scu based pinctrl support
Some i.MX SoCs (e.g. MX8QXP and MX8QM) contain a system controller
that is responsible for controlling the pad setting of the IPs that
are present. Communication between the host processor running an OS
and the system controller happens through a SCU protocol.

This patch classifies the pad settings into two categories: MMIO and SCU.
For the original MMIO method, no functional changes except organize them
into a few imx_*_mmio() functions. Besides that, we add the SCU based
Pad Mux and Pinconf setting support which are implemented in pinctrl-scu.c.

Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-11-05 09:33:32 +01:00
Wolfram Sang 1ccb0426d7 pinctrl: pinctrl-at91-pio4: simplify getting .driver_data
We should get 'driver_data' from 'struct device' directly. Going via
platform_device is an unneeded step back and forth.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-11-05 09:33:32 +01:00
Wolfram Sang 9f540c3e1d pinctrl: pinctrl-amd: simplify getting .driver_data
We should get 'driver_data' from 'struct device' directly. Going via
platform_device is an unneeded step back and forth.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-11-05 09:33:32 +01:00
Jerome Brunet a1705f0270 pinctrl: meson: fix meson8b ao pull register bits
AO pull register definition is inverted between pull (up/down) and
pull enable. Fixing this allows to properly apply bias setting
through pinconf

Fixes: 0fefcb6876 ("pinctrl: Add support for Meson8b")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-11-05 09:33:22 +01:00
Jerome Brunet e91b162d28 pinctrl: meson: fix meson8 ao pull register bits
AO pull register definition is inverted between pull (up/down) and
pull enable. Fixing this allows to properly apply bias setting
through pinconf

Fixes: 6ac7309511 ("pinctrl: add driver for Amlogic Meson SoCs")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-11-05 09:33:22 +01:00
Jerome Brunet ed3a2b74f3 pinctrl: meson: fix gxl ao pull register bits
AO pull register definition is inverted between pull (up/down) and
pull enable. Fixing this allows to properly apply bias setting
through pinconf

Fixes: 0f15f500ff ("pinctrl: meson: Add GXL pinctrl definitions")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-11-05 09:33:22 +01:00
Jerome Brunet 4bc51e1e35 pinctrl: meson: fix gxbb ao pull register bits
AO pull register definition is inverted between pull (up/down) and
pull enable. Fixing this allows to properly apply bias setting
through pinconf

Fixes: 468c234f9e ("pinctrl: amlogic: Add support for Amlogic Meson GXBB SoC")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-11-05 09:33:22 +01:00
Jerome Brunet e39f9dd820 pinctrl: meson: fix pinconf bias disable
If a bias is enabled on a pin of an Amlogic SoC, calling .pin_config_set()
with PIN_CONFIG_BIAS_DISABLE will not disable the bias. Instead it will
force a pull-down bias on the pin.

Instead of the pull type register bank, the driver should access the pull
enable register bank.

Fixes: 6ac7309511 ("pinctrl: add driver for Amlogic Meson SoCs")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-11-05 09:33:22 +01:00
Linus Torvalds 114b5f8f7e This is the bulk of GPIO changes for the v4.20 series:
Core changes:
 
 - A patch series from Hans Verkuil to make it possible to
   enable/disable IRQs on a GPIO line at runtime and drive GPIO
   lines as output without having to put/get them from scratch.
   The irqchip callbacks have been improved so that they can
   use only the fastpatch callbacks to enable/disable irqs
   like any normal irqchip, especially the gpiod_lock_as_irq()
   has been improved to be callable in fastpath context.
   A bunch of rework had to be done to achieve this but it is
   a big win since I never liked to restrict this to slowpath.
   The only call requireing slowpath was try_module_get() and
   this is kept at the .request_resources() slowpath callback.
   In the GPIO CEC driver this is a big win sine a single
   line is used for both outgoing and incoming traffic, and
   this needs to use IRQs for incoming traffic while actively
   driving the line for outgoing traffic.
 
 - Janusz Krzysztofik improved the GPIO array API to pass a
   "cookie" (struct gpio_array) and a bitmap for setting or
   getting multiple GPIO lines at once. This improvement
   orginated in a specific need to speed up an OMAP1 driver and
   has led to a much better API and real performance gains
   when the state of the array can be used to bypass a lot
   of checks and code when we want things to go really fast.
   The previous code would minimize the number of calls
   down to the driver callbacks assuming the CPU speed was
   orders of magnitude faster than the I/O latency, but this
   assumption was wrong on several platforms: what we needed
   to do was to profile and improve the speed on the hot
   path of the array functions and this change is now
   completed.
 
 - Clean out the painful and hard to grasp BNF experiments
   from the device tree bindings. Future approaches are looking
   into using JSON schema for this purpose. (Rob Herring
   is floating a patch series.)
 
 New drivers:
 
 - The RCAR driver now supports r8a774a1 (RZ/G2M).
 
 - Synopsys GPIO via CREGs driver.
 
 Major improvements:
 
 - Modernization of the EP93xx driver to use irqdomain and
   other contemporary concepts.
 
 - The ingenic driver has been merged into the Ingenic pin
   control driver and removed from the GPIO subsystem.
 
 - Debounce support in the ftgpio010 driver.
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Merge tag 'gpio-v4.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio

Pull GPIO updates from Linus Walleij:
 "This is the bulk of GPIO changes for the v4.20 series:

  Core changes:

   - A patch series from Hans Verkuil to make it possible to
     enable/disable IRQs on a GPIO line at runtime and drive GPIO lines
     as output without having to put/get them from scratch.

     The irqchip callbacks have been improved so that they can use only
     the fastpatch callbacks to enable/disable irqs like any normal
     irqchip, especially the gpiod_lock_as_irq() has been improved to be
     callable in fastpath context.

     A bunch of rework had to be done to achieve this but it is a big
     win since I never liked to restrict this to slowpath. The only call
     requireing slowpath was try_module_get() and this is kept at the
     .request_resources() slowpath callback. In the GPIO CEC driver this
     is a big win sine a single line is used for both outgoing and
     incoming traffic, and this needs to use IRQs for incoming traffic
     while actively driving the line for outgoing traffic.

   - Janusz Krzysztofik improved the GPIO array API to pass a "cookie"
     (struct gpio_array) and a bitmap for setting or getting multiple
     GPIO lines at once.

     This improvement orginated in a specific need to speed up an OMAP1
     driver and has led to a much better API and real performance gains
     when the state of the array can be used to bypass a lot of checks
     and code when we want things to go really fast.

     The previous code would minimize the number of calls down to the
     driver callbacks assuming the CPU speed was orders of magnitude
     faster than the I/O latency, but this assumption was wrong on
     several platforms: what we needed to do was to profile and improve
     the speed on the hot path of the array functions and this change is
     now completed.

   - Clean out the painful and hard to grasp BNF experiments from the
     device tree bindings. Future approaches are looking into using JSON
     schema for this purpose. (Rob Herring is floating a patch series.)

  New drivers:

   - The RCAR driver now supports r8a774a1 (RZ/G2M).

   - Synopsys GPIO via CREGs driver.

  Major improvements:

   - Modernization of the EP93xx driver to use irqdomain and other
     contemporary concepts.

   - The ingenic driver has been merged into the Ingenic pin control
     driver and removed from the GPIO subsystem.

   - Debounce support in the ftgpio010 driver"

* tag 'gpio-v4.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (116 commits)
  gpio: Clarify kerneldoc on gpiochip_set_chained_irqchip()
  gpio: Remove unused 'irqchip' argument to gpiochip_set_cascaded_irqchip()
  gpio: Drop parent irq assignment during cascade setup
  mmc: pwrseq_simple: Fix incorrect handling of GPIO bitmap
  gpio: fix SNPS_CREG kconfig dependency warning
  gpiolib: Initialize gdev field before is used
  gpio: fix kernel-doc after devres.c file rename
  gpio: fix doc string for devm_gpiochip_add_data() to not talk about irq_chip
  gpio: syscon: Fix possible NULL ptr usage
  gpiolib: Show correct direction from the beginning
  pinctrl: msm: Use init_valid_mask exported function
  gpiolib: Add init_valid_mask exported function
  GPIO: add single-register GPIO via CREG driver
  dt-bindings: Document the Synopsys GPIO via CREG bindings
  gpio: mockup: use device properties instead of platform_data
  gpio: Slightly more helpful debugfs
  gpio: omap: Remove set but not used variable 'dev'
  gpio: omap: drop omap_gpio_list
  Accept partial 'gpio-line-names' property.
  gpio: omap: get rid of the conditional PM runtime calls
  ...
2018-10-23 08:45:05 +01:00
Linus Torvalds b0b6a28bc4 This is the bulk of pin control changes for the v4.20 series:
There were no significant changes to the core this time!
 
 New drivers:
 
 - Broadcom Northstar pin control driver.
 
 - Mediatek MT8183 subdriver.
 
 - Mediatek MT7623 subdriver.
 
 - Mediatek MT6765 subdriver.
 
 - Meson g12a subdriver.
 
 - Nuvoton NPCM7xx pin control and GPIO driver.
 
 - Qualcomm QCS404 pin control and GPIO subdriver.
 
 - Qualcomm SDM660 pin control and GPIO subdriver.
 
 - Renesas R8A7744 PFC subdriver.
 
 - Renesas R8A774C0 PFC subdriver.
 
 - Renesas RZ/N1 pinctrl driver
 
 Major improvements:
 
 - Pulled the GPIO support for Ingenic over from the GPIO
   subsystem and consolidated it all in the Ingenic pin control
   driver.
 
 - Major cleanups and consolidation work in all Intel drivers.
 
 - Major cleanups and consolidation work in all Mediatek drivers.
 
 - Lots of incremental improvements to the Renesas PFC pin
   controller family.
 
 - All drivers doing GPIO now include <linux/gpio/driver.h> and
   nothing else.
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Merge tag 'pinctrl-v4.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v4.20 series:

  There were no significant changes to the core this time! Bur the new
  Qualcomm, Mediatek and Broadcom drivers are quite interesting as they
  will be used in a few million embedded devices the coming years as it
  seems.

  New drivers:

   - Broadcom Northstar pin control driver.

   - Mediatek MT8183 subdriver.

   - Mediatek MT7623 subdriver.

   - Mediatek MT6765 subdriver.

   - Meson g12a subdriver.

   - Nuvoton NPCM7xx pin control and GPIO driver.

   - Qualcomm QCS404 pin control and GPIO subdriver.

   - Qualcomm SDM660 pin control and GPIO subdriver.

   - Renesas R8A7744 PFC subdriver.

   - Renesas R8A774C0 PFC subdriver.

   - Renesas RZ/N1 pinctrl driver

  Major improvements:

   - Pulled the GPIO support for Ingenic over from the GPIO subsystem
     and consolidated it all in the Ingenic pin control driver.

   - Major cleanups and consolidation work in all Intel drivers.

   - Major cleanups and consolidation work in all Mediatek drivers.

   - Lots of incremental improvements to the Renesas PFC pin controller
     family.

   - All drivers doing GPIO now include <linux/gpio/driver.h> and
     nothing else"

* tag 'pinctrl-v4.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (153 commits)
  pinctrl: sunxi: Fix a memory leak in 'sunxi_pinctrl_build_state()'
  gpio: uniphier: include <linux/bits.h> instead of <linux/bitops.h>
  pinctrl: uniphier: include <linux/bits.h> instead of <linux/bitops.h>
  dt-bindings: pinctrl: bcm4708-pinmux: improve example binding
  pinctrl: geminilake: Sort register offsets by value
  pinctrl: geminilake: Get rid of unneeded ->probe() stub
  pinctrl: geminilake: Update pin list for B0 stepping
  pinctrl: renesas: Fix platform_no_drv_owner.cocci warnings
  pinctrl: mediatek: Make eint_m u16
  pinctrl: bcm: ns: Use uintptr_t for casting data
  pinctrl: madera: Fix uninitialized variable bug in madera_mux_set_mux
  pinctrl: gemini: Fix up TVC clock group
  pinctrl: gemini: Drop noisy debug prints
  pinctrl: gemini: Mask and set properly
  pinctrl: mediatek: select GPIOLIB
  pinctrl: rza1: don't manually release devm managed resources
  MAINTAINERS: update entry for Mediatek pin controller
  pinctrl: bcm: add Northstar driver
  dt-bindings: pinctrl: document Broadcom Northstar pin mux controller
  pinctrl: qcom: fix 'const' pointer handling
  ...
2018-10-23 08:40:16 +01:00
Christophe JAILLET a93a676b07 pinctrl: sunxi: Fix a memory leak in 'sunxi_pinctrl_build_state()'
If 'krealloc()' fails, 'pctl->functions' is set to NULL.
We should instead use a temp variable in order to be able to free the
previously allocated memeory, in case of OOM.

Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-16 10:03:48 +02:00
Masahiro Yamada e24cf513cb pinctrl: uniphier: include <linux/bits.h> instead of <linux/bitops.h>
The reason of including <linux/bitops.h> here is just for BIT() macro.

Since commit 8bd9cb51da ("locking/atomics, asm-generic: Move some
macros from <linux/bitops.h> to a new <linux/bits.h> file"),
<linux/bits.h> is enough for such compile-time macros.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-16 10:01:59 +02:00
Andy Shevchenko ce96a3a041 pinctrl: geminilake: Sort register offsets by value
No functional change.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-16 09:18:15 +02:00
Andy Shevchenko 2b3445c7eb pinctrl: geminilake: Get rid of unneeded ->probe() stub
The local ->probe() stub does nothing except calling
a generic Intel pin control probe function. Thus,
it's not needed and generic function may be called directly.

This patch converts the driver accordingly.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-16 09:18:15 +02:00
Andy Shevchenko 08a3e5dca0 pinctrl: geminilake: Update pin list for B0 stepping
According to an updated pin list few names of the pins can be spelled better,
taking into account their primary functions.

Thus, update a pin list to cover B0 stepping.

Note, SPI numbering had been fixed even in A0 public documentation.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-16 09:17:18 +02:00
YueHaibing 2b9ea543fa pinctrl: renesas: Fix platform_no_drv_owner.cocci warnings
Remove .owner field if calls are used which set it automatically
Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-15 16:19:44 +02:00
Manivannan Sadhasivam 28e0603c4d pinctrl: mediatek: Make eint_m u16
For SoC's which lacks EINT support, U16_MAX is assigned to both eint_m
and eint_n through macro NO_EINT_SUPPORT. This will generate integer
overflow warning because eint_m is declared as u8 type. Hence modify
the eint_m type to u16.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-15 16:17:01 +02:00
Rafał Miłecki ce7bdb957b pinctrl: bcm: ns: Use uintptr_t for casting data
Fix up a compiler error on 64bit architectures where pointers
and integers differ in size.

Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-12 11:14:59 +02:00
Gustavo A. R. Silva 4fe81669df pinctrl: madera: Fix uninitialized variable bug in madera_mux_set_mux
There is a potential execution path in which variable *ret* is checked
in an IF statement, and then its value is used to report an error at
line 659 without being properly initialized previously:

659 if (ret)
660	dev_err(priv->dev, "Failed to write to 0x%x (%d)\n", reg, ret);

Fix this by initializing variable *ret* to 0 in order to
avoid unpredictable or unintended results.

Addresses-Coverity-ID: 1471969 ("Uninitialized scalar variable")
Fixes: 218d72a77b ("pinctrl: madera: Add driver for Cirrus Logic Madera codecs")
Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-12 11:14:38 +02:00
Linus Walleij a85c928f6a pinctrl: gemini: Fix up TVC clock group
The previous fix made the TVC clock get muxed in on the
D-Link DIR-685 instead of giving nagging warnings of this
not working. Not good. We didn't want that, as it breaks
video.

Create a specific group for the TVC CLK, and break out
a specific GPIO group for it on the SL3516 so we can use
that line as GPIO if we don't need the TVC CLK.

Fixes: d17f477c5b ("pinctrl: gemini: Mask and set properly")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-10 21:05:35 +02:00
Marco Felsch f259f896f2 pinctrl: mcp23s08: fix irq and irqchip setup order
Since 'commit 02e389e63e ("pinctrl: mcp23s08: fix irq setup order")' the
irq request isn't the last devm_* allocation. Without a deeper look at
the irq and testing this isn't a good solution. Since this driver relies
on the devm mechanism, requesting a interrupt should be the last thing
to avoid memory corruptions during unbinding.

'Commit 02e389e63e ("pinctrl: mcp23s08: fix irq setup order")' fixed the
order for the interrupt-controller use case only. The
mcp23s08_irq_setup() must be split into two to fix it for the
interrupt-controller use case and to register the irq at last. So the
irq will be freed first during unbind.

Cc: stable@vger.kernel.org
Cc: Jan Kundrát <jan.kundrat@cesnet.cz>
Cc: Dmitry Mastykin <mastichi@gmail.com>
Cc: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Fixes: 82039d244f ("pinctrl: mcp23s08: add pinconf support")
Fixes: 02e389e63e ("pinctrl: mcp23s08: fix irq setup order")
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Tested-by: Phil Reid <preid@electromag.com.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-10 14:36:35 +02:00
Linus Walleij dab6558f57 pinctrl: gemini: Drop noisy debug prints
The dev_info() in the pin control driver is really just good
for debug, so drop it.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-10 13:55:31 +02:00
Linus Walleij d17f477c5b pinctrl: gemini: Mask and set properly
The code was written under the assumption that the
regmap_update_bits() would mask the bits in the mask and
set the bits in the value.

It missed the points that it will not set bits in the value
unless these are also masked in the mask. Set value bits
that are not in the mask will simply be ignored.

Fixes: 06351d133d ("pinctrl: add a Gemini SoC pin controller")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-10 13:55:04 +02:00
Arnd Bergmann 71a9d395aa pinctrl: mediatek: select GPIOLIB
Removing the linux/gpio.h include means we no longer have a declaration
of gpiochip_lock_as_irq() when CONFIG_GPIOLIB is disabled:

drivers/pinctrl/mediatek/mtk-eint.c: In function 'mtk_eint_irq_request_resources':
drivers/pinctrl/mediatek/mtk-eint.c:247:8: error: implicit declaration of function 'gpiochip_lock_as_irq'; did you mean 'spin_lock_irq'? [-Werror=implicit-function-declaration]
drivers/pinctrl/mediatek/mtk-eint.c: In function 'mtk_eint_irq_release_resources':
drivers/pinctrl/mediatek/mtk-eint.c:272:2: error: implicit declaration of function 'gpiochip_unlock_as_irq'; did you mean 'spin_unlock_irq'? [-Werror=implicit-function-declaration]

Select it explictly instead.

Fixes: 1c5fb66afa ("pinctrl: Include <linux/gpio/driver.h> nothing else")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-10 13:53:21 +02:00
Uwe Kleine-König 5fd8d05191 pinctrl: rza1: don't manually release devm managed resources
If the probe function fails the driver core cares to return the allocated
resources automatically. So the driver can be simplified accordingly.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-10 11:56:21 +02:00
Linus Walleij b0b378acde pinctrl: sh-pfc: Updates for v4.20 (take three)
- Add support for the new RZ/N1D (R9A06G032) and RZ/N1S (R9A06G033)
     SoCs,
   - Add INTC-EX pin groups on R-Car E3.
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Merge tag 'sh-pfc-for-v4.20-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v4.20 (take three)

  - Add support for the new RZ/N1D (R9A06G032) and RZ/N1S (R9A06G033)
    SoCs,
  - Add INTC-EX pin groups on R-Car E3.
2018-10-10 11:15:33 +02:00
Ricardo Ribalda Delgado 6f0ec09afe pinctrl: msm: Use init_valid_mask exported function
The current code produces XPU violation if get_direction is called just
after the initialization.

Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Acked-by: Timur Tabi <timur@kernel.org>
Tested-by: Jeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-10 10:31:57 +02:00
Rafał Miłecki c12fb1774d pinctrl: bcm: add Northstar driver
This driver provides support for Northstar mux controller. It differs
from Northstar Plus one so a new binding and driver were needed.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-10 09:16:54 +02:00
Arnd Bergmann c5ad04dd44 pinctrl: qcom: fix 'const' pointer handling
The 'tiles' array is initialized to a constant pointers to constant
strings, but the declaration is only half as constant:

drivers/pinctrl/qcom/pinctrl-qcs404.c:1660:11: error: initialization discards 'const' qualifier from pointer target type [-Werror=discarded-qualifiers]
drivers/pinctrl/qcom/pinctrl-sdm660.c:1417:11: error: initialization discards 'const' qualifier from pointer target type [-Werror=discarded-qualifiers]

Let's make it more constant.

Fixes: 22eb8301db ("pinctrl: qcom: Add qcs404 pinctrl driver")
Fixes: a46d5e9819 ("pinctrl: qcom: Support dispersed tiles")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-03 09:11:58 +02:00
Linus Walleij 936a3a23be pinctrl: nomadik: Fix debugfs
The .to_irq() function obviously takes the per-chip offset
as parameter, not the global GPIO number.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-03 09:10:52 +02:00
Andy Shevchenko 946ffefcdc pinctrl: intel: Fix a spelling typo in kernel documentation
The parameter 'community' had been spelled incorrectly.
Fix it here.

As a side effect it satisfies static checkers that issue
the following warnings:

drivers/pinctrl/intel/pinctrl-intel.c:845: warning: Function parameter or member 'community' not described in 'intel_gpio_to_pin'
drivers/pinctrl/intel/pinctrl-intel.c:845: warning: Excess function parameter 'commmunity' description in 'intel_gpio_to_pin'

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-03 09:05:35 +02:00
Andy Shevchenko cd057a765f pinctrl: broxton: Convert unsigned to unsigned int
Simple type conversion with no functional change implied.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-03 09:05:32 +02:00
Andy Shevchenko 4e737af8c4 pinctrl: cherryview: Convert unsigned to unsigned int
Simple type conversion with no functional change implied.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-03 09:05:28 +02:00
Andy Shevchenko 939330d71e pinctrl: baytrail: Convert unsigned to unsigned int
Simple type conversion with no functional change implied.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-03 09:05:25 +02:00
Andy Shevchenko 04035f7f59 pinctrl: intel: Convert unsigned to unsigned int
Simple type conversion with no functional change implied.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-03 09:05:21 +02:00
Geert Uytterhoeven ef26d96023 pinctrl: sh-pfc: r8a77990: Add INTC-EX pins, groups and function
Add pins, groups, and function for the Interrupt Controller for
External Devices (INTC-EX) on the R-Car E3 SoC.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-10-02 12:16:47 +02:00
Phil Edworthy 4e53b50047 pinctrl: renesas: Renesas RZ/N1 pinctrl driver
This provides a pinctrl driver for the Renesas RZ/N1 device family.

Based on a patch originally written by Michel Pollet at Renesas.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-10-02 12:16:47 +02:00
Stephen Boyd de0c18a87c pinctrl: msm: Actually use function 0 for gpio selection
This code needs to select function #0, which is the first int in the
array of functions, not the number 0 which may or may not be the
function for "GPIO mode" per the enum mapping. We were getting lucky on
SDM845, where this was tested, because the function 0 matched the enum
value for "GPIO mode". On other platforms, e.g. MSM8996, the gpio enum
value is the last one in the list so this code doesn't work and we see a
warning at boot. Fix it by grabbing the first element out of the array
of functions.

Cc: Doug Anderson <dianders@chromium.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Niklas Cassel <niklas.cassel@linaro.org>
Reported-by: Niklas Cassel <niklas.cassel@linaro.org>
Fixes: 1de7ddb3a1 ("pinctrl: msm: Mux out gpio function with gpio_request()")
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-02 10:48:43 +02:00
Yanjiang Jin 54a58185bf pinctrl: core: make sure strcmp() doesn't get a null parameter
Some drivers, for example, QCOM's qdf2xxx, set groups[gpio].name only
when gpio is valid, and leave invalid gpio names as null.
If we want to access the sys node "pinconf-groups",
pinctrl_get_group_selector() -> get_group_name() may return a null
pointer if group_selector is invalid, then the below Kernel panic
would happen since strcmp() uses this null pointer to do comparison.

 Unable to handle kernel NULL pointer dereference at ss 00000000
el:Internal error: Oops: 9600000[ 143.080279]
SMP
 CPU: 19 PID: 2493 Comm: read_all Tainted: G O
.aarch64 #1
 Hardware name: HXT Semiconductor HXT REP-2 System
 PC is at strcmp+0x18/0x154
 LR is at pinctrl_get_group_selector+0x6c/0xe8
 Process read_all (pid: 2493, stack limit =
 Call trace:
 Exception stack
  strcmp+0x18/0x154
  pin_config_group_get+0x64/0xd8
  pinconf_generic_dump_one+0xd8/0x1c0
  pinconf_generic_dump_pins+0x94/0xc8
  pinconf_groups_show+0xb4/0x104
  seq_read+0x178/0x464
  full_proxy_read+0x6c/0xac
  __vfs_read+0x58/0x178
  vfs_read+0x94/0x164
  SyS_read+0x60/0xc0
  __sys_trace_return+0x0/0x4
 --[ end trace]--
 Kernel panic - not syncing: Fatal exception

Signed-off-by: Yanjiang Jin <yanjiang.jin@hxt-semitech.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-01 13:46:13 +02:00
Linus Walleij 18887f31df pinctrl: sh-pfc: Updates for v4.20 (take two)
- Add MSIOF pin groups on R-Car E3 and D3,
   - Add support for the new RZ/G1N (R8A7744) and RZ/G2E (R8A774C0) SoCs,
   - Add I2C4, DU0, QSPI0, SDHI2, and USB pin groups on RZ/G1C,
   - Convert to SPDX license identifiers,
   - Small cleanups.
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Merge tag 'sh-pfc-for-v4.20-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v4.20 (take two)

  - Add MSIOF pin groups on R-Car E3 and D3,
  - Add support for the new RZ/G1N (R8A7744) and RZ/G2E (R8A774C0) SoCs,
  - Add I2C4, DU0, QSPI0, SDHI2, and USB pin groups on RZ/G1C,
  - Convert to SPDX license identifiers,
  - Small cleanups.
2018-10-01 13:21:58 +02:00
Linus Walleij 30aa69e7bd This is the 4.19-rc6 release
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Merge tag 'v4.19-rc6' into devel

This is the 4.19-rc6 release

I needed to merge this in because of extensive conflicts in
the MSM and Intel pin control drivers. I know how to resolve
them, so let's do it like this.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-01 13:20:45 +02:00
Geert Uytterhoeven a97f340c0a pinctrl: sh-pfc: rcar: Rename automotive-only arrays to automotive
Renesas RZ/G SoCs are pin compatible with R-Car SoCs, but lack several
automotive-specific peripherals.

Currently pin groups and functions for automotive-specific peripherals
are grouped in arrays named after the automative SoC part numbers.
Rename them to "automotive" for clarity and consistency.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-28 09:49:15 +02:00
Baolin Wang 63e037bc51 pinctrl: sprd: Move DT parsing before registering pinctrl device
It will be failed to select default or sleep state for pins hogged
by the pin controller device, since we hadn't parsed pins configuration
in device tree before registering the pin controller device. Thus
we should move the device tree parsing function before registering
the pin controller device.

Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-28 09:34:19 +02:00
Arnd Bergmann ad335bee6c pinctrl: mediatek: mark dummy helpers as 'static inline'
mtk_eint_set_debounce and mtk_eint_find_irq are defined as stub functions
in a header file, but without marking them as 'static inline', we get
a copy for each file that includes the header:

drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.o: In function `mtk_eint_set_debounce':
pinctrl-mtk-common-v2.c:(.text+0x134): multiple definition of `mtk_eint_set_debounce'
drivers/pinctrl/mediatek/pinctrl-moore.o:pinctrl-moore.c:(.text+0x7d0): first defined here
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.o: In function `mtk_eint_find_irq':
pinctrl-mtk-common-v2.c:(.text+0x13c): multiple definition of `mtk_eint_find_irq'

Fixes: e46df235b4 ("pinctrl: mediatek: refactor EINT related code for all MediaTek pinctrl can fit")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-28 09:27:04 +02:00
Colin Ian King 7a52127e3c pinctrl: mediatek: fix check on EINT_NA comparison
Currently, the check on desc->eint.eint_n == EINT_NA is always false
because this is comparing a u16 to -1 which can never be true.  Fix
this by casting EINT_NA to u16.

Detected by CoverityScan, CID#1473610 ("Operands don't affect result")

Fixes: fb5fa8dc15 ("pinctrl: mediatek: extend struct mtk_pin_desc to pinctrl-mtk-common-v2.c")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-26 09:43:01 +02:00
Avaneesh Kumar Dwivedi 22eb8301db pinctrl: qcom: Add qcs404 pinctrl driver
Add initial pinctrl driver to support pin configuration with
pinctrl framework for qcs404.

Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org>
Signed-off-by: Chintan Pandya <cpandya@codeaurora.org>
Signed-off-by: Anu Ramanathan <anur@codeaurora.org>
[bjorn: Reworked tile handling and did some minor rework]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-26 09:43:01 +02:00
Bjorn Andersson a46d5e9819 pinctrl: qcom: Support dispersed tiles
On some new platforms the tiles have been placed too far apart to be
covered in a single ioremap. Turn "regs" into an array of base addresses
and make the pingroup carry the information about which tile the pin
resides in.

For existing platforms we map the first entry regs and the existing
pingroups will all use tile 0, meaning that there's no functional
change.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-26 09:30:43 +02:00
Bjorn Andersson 6c73698904 pinctrl: qcom: Introduce readl/writel accessors
In preparation for the support for dispersed tiles move all readl and
writel calls to helper functions. This will allow us to isolate the
added complexity of another indirection.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-26 09:29:59 +02:00
Neeraj Upadhyay 9cf0c526bc pinctrl: qcom: Add sdm660 pinctrl driver
Add initial pinctrl driver to support pin configuration with
pinctrl framework for sdm660.
Based off CAF implementation.

Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
Co-Developed-by: Venkatesh Yadav Abbarapu <vabbar@codeaurora.org>
Signed-off-by: Venkatesh Yadav Abbarapu <vabbar@codeaurora.org>
[craig: minor updates for upstreaming, updated tile handling]
Signed-off-by: Craig Tatlor <ctatlor97@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-26 08:55:53 +02:00
Mika Westerberg 72923e5488 Revert "pinctrl: intel: Do pin translation when lock IRQ"
This reverts commit 55aedef50d.

Commit 55aedef50d ("pinctrl: intel: Do pin translation when lock IRQ")
added special translation from GPIO number to hardware pin number to
irq_reqres/relres hooks to avoid failure when IRQs are requested. The
actual failure happened inside gpiochip_lock_as_irq() because it calls
gpiod_get_direction() and pinctrl-intel.c::intel_gpio_get_direction()
implementation originally missed the translation so the two hooks made
it work by skipping the ->get_direction() call entirely (it overwrote
the default GPIOLIB provided functions).

The proper fix that adds translation to GPIO callbacks was merged with
commit 96147db1e1 ("pinctrl: intel: Do pin translation in other GPIO
operations as well"). This allows us to use the default GPIOLIB provided
functions again.

In addition as find out by Benjamin Tissoires the two functions
(intel_gpio_irq_reqres()/intel_gpio_irq_relres()) now cause problems of
their own because they operate on pin numbers and pass that pin number
to gpiochip_lock_as_irq() which actually expects a GPIO number.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=199911
Fixes: 55aedef50d ("pinctrl: intel: Do pin translation when lock IRQ")
Reported-and-tested-by: Benjamin Tissoires <benjamin.tissoires@gmail.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-25 12:50:00 +02:00
Mika Westerberg e50d95e2ad pinctrl: cannonlake: Fix HOSTSW_OWN register offset of H variant
It turns out the HOSTSW_OWN register offset is different between LP and
H variants. The latter should use 0xc0 instead so fix that.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=199911
Fixes: a663ccf0fe ("pinctrl: intel: Add Intel Cannon Lake PCH-H pin controller support")
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-25 12:48:15 +02:00
Andy Shevchenko e99542fb8d pinctrl: intel: merrifield: Group IO accessors in code
Consolidate IO accessors in the code to make maintenance a little bit easier
in the future.

No functional change intended.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-25 12:45:47 +02:00
Andy Shevchenko 5e0b7e7cd2 pinctrl: intel: merrifield: Introduce mrfld_read_bufcfg()
mrfld_read_bufcfg() helper checks if pin is correct and reads back
the current value of corresponding BUFCFG register.

While it adds lines of code it will be easier to maintain in the future.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-25 12:44:41 +02:00
Daniel Kurtz b85bfa246e pinctrl/amd: poll InterruptEnable bits in amd_gpio_irq_set_type
From the AMD BKDG, if WAKE_INT_MASTER_REG.MaskStsEn is set, a software
write to the debounce registers of *any* gpio will block wake/interrupt
status generation for *all* gpios for a length of time that depends on
WAKE_INT_MASTER_REG.MaskStsLength[11:0].  During this period the Interrupt
Delivery bit (INTERRUPT_ENABLE) will read as 0.

In commit 4c1de0414a ("pinctrl/amd: poll InterruptEnable bits in
enable_irq") we tried to fix this same "gpio Interrupts are blocked
immediately after writing debounce registers" problem, but incorrectly
assumed it only affected the gpio whose debounce was being configured
and not ALL gpios.

To solve this for all gpios, we move the polling loop from
amd_gpio_irq_enable() to amd_gpio_irq_set_type(), while holding the gpio
spinlock.  This ensures that another gpio operation (e.g.
amd_gpio_irq_unmask()) can read a temporarily disabled IRQ and
incorrectly disable it while trying to modify some other register bits.

Fixes: 4c1de0414a pinctrl/amd: poll InterruptEnable bits in enable_irq
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-25 12:39:19 +02:00
YueHaibing a4925311a5 pinctrl: sunxi: fix 'pctrl->functions' allocation in sunxi_pinctrl_build_state
fixes following Smatch static check warning:

 ./drivers/pinctrl/sunxi/pinctrl-sunxi.c:1112 sunxi_pinctrl_build_state()
 warn: passing devm_ allocated variable to kfree. 'pctrl->functions'

As we will be calling krealloc() on pointer 'pctrl->functions', which means
kfree() will be called in there, devm_kzalloc() shouldn't be used with
the allocation in the first place.  Fix the warning by calling kcalloc()
and managing the free procedure in error path on our own.

Fixes: 0e37f88d9a ("ARM: sunxi: Add pinctrl driver for Allwinner SoCs")
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-21 09:17:27 -07:00
Mars Cheng bb8d8466ca pinctrl: mediatek: add eint support to MT6765 pinctrl driver
Just add eint support to MT6765 pinctrl driver as usual as
happens on the other SoCs.

Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-21 09:13:54 -07:00
ZH Chen 477fecee7c pinctrl: mediatek: add MT6765 pinctrl driver
Add MT6765 pinctrl driver based on MediaTek pinctrl-paris core.

Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: ZH Chen <zh.chen@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-21 09:12:55 -07:00
Mars Cheng ecfcfb4988 pinctrl: mediatek: add no eint function for pin define
Add NO_EINT_SUPPORT back to pinctrl-mtk-common-v2.h as the alias of
EINT_NA to indicate that some pin not capable of being controlled as eint
and that is required by pinctrl-paris based driver as old
pinctrl-mtk-common.h already had.

Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-21 09:12:06 -07:00
Sean Wang 7f2e29e133 pinctrl: mediatek: fix static checker warning caused by EINT_NA
EINT_NA is an u16 number, so it should be U16_MAX instead of -1
to fix up drivers/pinctrl/mediatek/pinctrl-paris.c:732 mtk_gpio_to_irq()
warn: impossible condition (desc->eint.eint_n == -1) => (0-u16max == (-1))

Also happens in
drivers/pinctrl/mediatek/pinctrl-paris.c:749 mtk_gpio_set_config()
warn: impossible condition (desc->eint.eint_n == -1) => (0-u16max == (-1))

drivers/pinctrl/mediatek/pinctrl-moore.c:479 mtk_gpio_to_irq()
warn: impossible condition (desc->eint.eint_n == -1) => (0-u16max == (-1))

drivers/pinctrl/mediatek/pinctrl-moore.c:496 mtk_gpio_set_config()
warn: impossible condition '(desc->eint.eint_n == -1) => (0-u16max == (-1))

Fixes: 6561859b06 ("pinctrl: mediatek: add eint support to MT8183 pinctrl driver")
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-21 09:11:12 -07:00
Wei Yongjun 068cfb9a0f pinctrl: mediatek: moore: fix return value check in mtk_moore_pinctrl_probe()
In case of error, the function devm_kmalloc_array() returns NULL pointer
not ERR_PTR(). The IS_ERR() test in the return value check should be
replaced with NULL test.

Fixes: b7d7f9eeca ("pinctrl: mediatek: extend struct mtk_pin_desc which per-pin driver depends on")
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Acked-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-21 09:08:18 -07:00
Wei Yongjun 07c6b037c2 pinctrl: mediatek: make symbol 'mtk_drive' static
Fixes the following sparse warning:

drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c:37:29: warning:
 symbol 'mtk_drive' was not declared. Should it be static?

Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Acked-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-21 09:02:37 -07:00
Wei Yongjun 184744e9a0 pinctrl: mediatek: paris: fix return value check in mtk_paris_pinctrl_probe()
In case of error, the function devm_kmalloc_array() returns NULL pointer
not ERR_PTR(). The IS_ERR() test in the return value check should be
replaced with NULL test.

Fixes: 805250982b ("pinctrl: mediatek: add pinctrl-paris that implements the vendor dt-bindings")
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Acked-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-21 09:00:51 -07:00
YueHaibing 69f8455f6c pinctrl: qcom: spmi-mpp: Fix err handling of pmic_mpp_set_mux
'ret' should be returned while pmic_mpp_write_mode_ctl fails.

Fixes: 0e948042c4 ("pinctrl: qcom: spmi-mpp: Implement support for sink mode")
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-21 08:17:43 -07:00
Fabio Estevam c98b0d2db7 pinctrl: mxs: do not export mxs_pinctrl_probe
No user of mxs_pinctrl_probe() can be built as a module, hence
exporting the symbol is not necessary. Drop EXPORT_SYMBOL_GPL.

Inspired by a patch from Stefan Agner for the tegra pinctrl driver.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-20 15:45:14 -07:00
Mika Westerberg 96147db1e1 pinctrl: intel: Do pin translation in other GPIO operations as well
For some reason I thought GPIOLIB handles translation from GPIO ranges
to pinctrl pins but it turns out not to be the case. This means that
when GPIOs operations are performed for a pin controller having a custom
GPIO base such as Cannon Lake and Ice Lake incorrect pin number gets
used internally.

Fix this in the same way we did for lock/unlock IRQ operations and
translate the GPIO number to pin before using it.

Fixes: a60eac3239 ("pinctrl: intel: Allow custom GPIO base for pad groups")
Reported-by: Rajat Jain <rajatja@google.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Tested-by: Rajat Jain <rajatja@google.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-20 08:21:52 -07:00
Stefan Agner a65fbff275 pinctrl: tegra: do not export tegra_pinctrl_probe
No user of tegra_pinctrl_probe can be built as a module, hence
exporting the symbol is not necessary. Drop EXPORT_SYMBOL_GPL.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-20 08:15:16 -07:00
Fabrizio Castro 8faa0754ec pinctrl: sh-pfc: r8a77470: Add USB pin groups
Add USB[01] pin groups and functions to the R8A77470 SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-20 17:11:25 +02:00
Fabrizio Castro df9c71694f pinctrl: sh-pfc: r8a77470: Add SDHI2 pin groups
Add SDHI2 pin groups and functions to the R8A77470 SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-20 17:11:25 +02:00
Fabrizio Castro e5984d0576 pinctrl: sh-pfc: r8a77470: Add QSPI0 pin groups
Add QSPI0 pin groups and function to the R8A77470 SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-20 17:11:25 +02:00
Fabrizio Castro 469c1e97dc pinctrl: sh-pfc: r8a77470: Add DU0 pin groups
Add DU0 pin groups and function to the R8A77470 SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-20 17:11:25 +02:00
Fabrizio Castro e34ebe5a6b pinctrl: sh-pfc: r8a77470: Add I2C4 pin groups
Add I2C4 pin groups and function to the R8A77470 SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-20 17:11:25 +02:00
Fabrizio Castro 9f2b76a2db pinctrl: sh-pfc: r8a77990: Add R8A774C0 PFC support
Renesas RZ/G2E (a.k.a. r8a774c0) is pin compatible with R-Car
E3 (a.k.a. r8a77990), however it doesn't have several automotive
specific peripherals. Add a r8a77990 specific pin groups/functions
along with common pin groups/functions for supporting both r8a77990
and r8a774c0 SoCs.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-19 17:29:00 +02:00
Biju Das d7097b97e9 pinctrl: sh-pfc: r8a7791: Add r8a7744 support
Renesas RZ/G1N (R8A7744) is pin compatible with R-Car M2-W/N (R8A7791/3)
and RZ/G1M.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-19 17:27:18 +02:00
Linus Walleij 22d7fe4984 pinctrl: mtk: Fix up GPIO includes
Include only <linux/gpio/driver.h> since this is a driver,
not a consumer.

Cc: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-18 16:38:27 -07:00
Andy Shevchenko 994f886568 pinctrl: cherryview: Remove linux/init.h and sort headers
There is no need to include linux/init.h when at the same time
we include linux/module.h.

Remove redundant inclusion.

While here, sort header block alphabetically for easy maintenance.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-18 16:37:19 -07:00
Andy Shevchenko a919684f9e pinctrl: cherryview: Describe members of couple of structs
Compiler unsatisfied to see half described data structures
and issues warnings:

drivers/pinctrl/intel/pinctrl-cherryview.c:136: warning: Function parameter or member 'acpi_space_id' not described in 'chv_community'
drivers/pinctrl/intel/pinctrl-cherryview.c:169: warning: Function parameter or member 'saved_intmask' not described in 'chv_pinctrl'
drivers/pinctrl/intel/pinctrl-cherryview.c:169: warning: Function parameter or member 'saved_pin_context' not described in 'chv_pinctrl'

To satisfy it, describe mentioned members.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-18 16:37:19 -07:00
Andy Shevchenko e93ca9bbf3 pinctrl: cherryview: Remove unused groups of pins
For the long time no one complained about unused groups of pins
for fSPI and SMBUS.

Remove them for good and at the same time satisfy compiler,
otherwise get warning:

CC      drivers/pinctrl/intel/pinctrl-cherryview.o
drivers/pinctrl/intel/pinctrl-cherryview.c:285:23: warning: ‘southwest_smbus_pins’ defined but not used [-Wunused-const-variable=]
  static const unsigned southwest_smbus_pins[] = { 79, 81, 82 };
                        ^~~~~~~~~~~~~~~~~~~~
drivers/pinctrl/intel/pinctrl-cherryview.c:269:23: warning: ‘southwest_fspi_pins’ defined but not used [-Wunused-const-variable=]
  static const unsigned southwest_fspi_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7 };
                        ^~~~~~~~~~~~~~~~~~~

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-18 16:37:19 -07:00
Andy Shevchenko 5458b7cec4 pinctrl: cherryview: Re-use data structures from pinctrl-intel.h
We have some data structures duplicated across the drivers.
Let's deduplicate them by using ones that being provided by
pinctrl-intel.h.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-18 16:37:19 -07:00
Andy Shevchenko e0da38425b pinctrl: baytrail: Sort headers alphabetically
Sort header block alphabetically for easy maintenance.

No functional change intended.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-18 16:37:19 -07:00
Andy Shevchenko b76f191420 pinctrl: baytrail: Remove unneeded MODULE_DEVICE_TABLE()
Since the driver can't be compiled as a module, there is no need
to use no-op macros in the code.

Thus, remove unneeded MODULE_DEVICE_TABLE() macro from the driver.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-18 16:37:19 -07:00
Andy Shevchenko 677506ee09 pinctrl: intel: Move linux/pm.h to the local header
We now using a common macro for PM operations in pin control drivers for Intel
SoCs, and since that macro relies on the definition and macro from linux/pm.h
header file, it's logical to include it directly in pinctrl-intel.h. Otherwise
it's a bit fragile and requires a proper ordering of header inclusion in C
files.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-18 16:37:19 -07:00
Simon Detheridge 8e2aac3337 pinctrl: cannonlake: Fix gpio base for GPP-E
The gpio base for GPP-E was set incorrectly to 258 instead of 256,
preventing the touchpad working on my Tong Fang GK5CN5Z laptop.

Buglink: https://bugzilla.kernel.org/show_bug.cgi?id=200787
Signed-off-by: Simon Detheridge <s@sd.ai>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-18 16:35:22 -07:00
Linus Walleij 55818b9023 Merge branch 'ib-mtk' into devel 2018-09-18 14:55:54 -07:00
Sean Wang 6561859b06 pinctrl: mediatek: add eint support to MT8183 pinctrl driver
Just add eint support to MT8183 pinctrl driver as usual as
happens on the other SoCs.

Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-18 14:53:42 -07:00
Sean Wang 89132dd8ff pinctrl: mediatek: extend eint build to pinctrl-mtk-common-v2.c
Almost all MediaTek SoCs apply the exact same logic to build eint, so move
the common functions into pinctrl-mtk-common-v2.c to allow each new pinctrl
driver to reuse them. Also, add a protection checker on hw->soc->eint_hw to
avoid invalid memory access when there's certain SoC not to define its
eint_hw properly in the code flow.

Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-18 14:53:37 -07:00
Zhiyong Tao 29686f0151 pintcrl: mediatek: add pull tweaks for I2C related pins on MT8183
This patch provides the advanced pull for I2C used pins on MT8183.

Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-18 14:53:34 -07:00
Sean Wang 79348f6fb7 pinctrl: mediatek: extend advanced pull support in pinctrl-mtk-common-v2.c
Extend the advanced pull based on the legacy bias plus additional r0 and r1
to tweak the resistor level.

Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-18 14:53:32 -07:00
Zhiyong Tao 750cd15d90 pinctrl: mediatek: add MT8183 pinctrl driver
Add MT8183 pinctrl driver based on  MediaTek pinctrl-paris core.

Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-18 14:53:29 -07:00
Zhiyong Tao 805250982b pinctrl: mediatek: add pinctrl-paris that implements the vendor dt-bindings
Add pinctrl-paris core that implements vendor dt-binding which MediaTek
tablet, box and smartphone-based SoCs such as MT81xx, MT27xx, and MT67xx
SoCs really want to depend on. The driver is just completely rewritten
according to pinctrl-mtk-common.c but uses the new logic from
pinctrl-mtk-common-v2.c to have an elegant way to support new SoCs in the
future.

Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-18 14:53:25 -07:00
Sean Wang b7d7f9eeca pinctrl: mediatek: extend struct mtk_pin_desc which per-pin driver depends on
Because the pincrl-mtk-common.c is an implementation for per-pin binding,
its pin descriptor includes more information than pinctrl-mtk-common-v2
so far can support. So, we complement these data before writing a driver
using pincrl-mtk-common-v2.c for per-pin binding. By the way, the size of
struct mtk_pin_desc would be larger than struct pinctrl_pin_desc can hold,
so it's necessary to have a copy before the pins information is being
registered into the core.

Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-18 14:53:22 -07:00
Sean Wang 9d9b171c68 pinctrl: mediatek: adjust error code and message when some register not supported is found
It's usual and not an error for there's some register not supported by a
certain SoC or a pin so that in the case we have to adjust the message to
print and the error code to get rid of unnecessary false alarm.

Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-18 14:53:19 -07:00
Sean Wang 2bc47dfe4f pinctrl: mediatek: add multiple register bases support to pinctrl-mtk-common-v2.c
Certain SoC own multiple register base for accessing each pin groups,
it's easy to be done with extend struct mtk_pin_field_calc to support
the kind of SoC such as MT8183.

Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-18 14:53:12 -07:00
Sean Wang ea051eb384 pinctrl: mediatek: use pin descriptor all in pinctrl-mtk-common-v2.c
all use pin descriptor instead in pinctrl-mtk-common-v2.c for the
consistency and extensibility.

Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-18 14:53:07 -07:00
Sean Wang e7507f57a9 pinctrl: mediatek: add MT7623 pinctrl driver based on generic pinctrl binding
Adding MT7623 pinctrl driver based on generic pinctrl binding, that is
good example and demonstrates how to port any other MediaTek SoCs
pinctrl-moore core when people really would like to use the generic
pinctrl binding to support these MediaTek SoCs.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-18 14:53:05 -07:00
Sean Wang 9afc305bfa pinctrl: mediatek: add pullen, pullsel register support to pinctrl-mtk-common-v2.c
Certain SoCs have to program an extra PULLEN, PULLSEL register to configure
bias related function so that we add it in the existing path.

Signed-off-by: Ryder.Lee <ryder.lee@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-18 14:53:02 -07:00
Sean Wang 182c842fd5 pinctrl: mediatek: add ies register support to pinctrl-mtk-common-v2.c
Certain SoCs have to program an extra IES register to configure input
enabled mode so that we add it in the existing path as an option.

Signed-off-by: Ryder.Lee <ryder.lee@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-18 14:53:00 -07:00
Sean Wang 0d7ca77214 pinctrl: mediatek: add advanced pull related support to pinctrl-mtk-common-v2.c
There are some specific pins (i.e. MMC/SD) need specific registers to
turn on/off the 10K & 50k(75K) resistors when pull up/down.

Therefore, this patch adds the custom prarmeters so that the user could
control it through device tree.

Signed-off-by: Ryder.Lee <ryder.lee@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-18 14:52:57 -07:00
Sean Wang 85430152ba pinctrl: mediatek: add pull related support to pinctrl-mtk-common-v2.c
Put pull control support related functions to pinctrl-mtk-common-v2.c
as these operations might be different by chips and allow different
type of driver to reuse them.

Signed-off-by: Ryder.Lee <ryder.lee@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-18 14:52:55 -07:00
Sean Wang 3ad38a14e1 pinctrl: mediatek: add drv register support to pinctrl-mtk-common-v2.c
Certain SoCs have to program DRV register to configure driving
strength so that we add it in the existing path as an option.

Signed-off-by: Ryder.Lee <ryder.lee@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-18 14:52:52 -07:00
Sean Wang c28321979b pinctrl: mediatek: add driving strength related support to pinctrl-mtk-common-v2.c
Put driving strength support related functions to pinctrl-mtk-common-v2.c
as these operations might be different by chips and allow different type
of driver to reuse them.

Signed-off-by: Ryder.Lee <ryder.lee@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-18 14:52:49 -07:00
Sean Wang 1dc5e53691 pinctrl: mediatek: extend struct mtk_pin_soc to pinctrl-mtk-common-v2.c
Add two parameters gpio_m and eint_m for configuring GPIO mode and EINT
mode, they might be varying depend on SoC.

Signed-off-by: Ryder.Lee <ryder.lee@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-18 14:52:45 -07:00
Sean Wang fb5fa8dc15 pinctrl: mediatek: extend struct mtk_pin_desc to pinctrl-mtk-common-v2.c
This patch introduces a data structure mtk_pin_desc, which is used to
provide information per pin characteristic such as driving current,
eint number and a driving index, that is used to lookup table describing
the details about the groups of driving current by which the pin is able
to adjust the driving strength so that the driver could get the
appropriate driving group when calls .pin_config_get()/set().

Signed-off-by: Ryder.Lee <ryder.lee@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-18 14:52:42 -07:00
Sean Wang b906faf7b6 pinctrl: mediatek: extend struct mtk_pin_field_calc to pinctrl-mtk-common-v2.c
This patch adds members sz_reg fixed in struct mtk_pin_field_calc

- The 'fixed' is used to represent the consecutive pins share the same
bits within the same register with the 1st pin so that it can largely
reduce the entry size a bit.

- The 'sz_reg' is used to indicate the range of bits we use in a register
  that may vary by SoC

The above changes make the code more generic and this is useful as there
might be other existing or future chips all use the same logic to access
their register set and then being a little more abstract could help in the
long run.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-18 14:52:40 -07:00
Sean Wang e78d57b2f8 pinctrl: mediatek: add pinctrl-moore that implements the generic pinctrl dt-bindings
Add a generic driver pinctrl-moore.c for MT762x SoC and any other SoC
that would like to use generic dt-binding. The patch is furtherly
refactored from pinctrl-mt7622.c that totally uses the functions back by
the generic pinctrl core such as GENERIC_PINCONF, GENERIC_PINCTRL_GROUPS,
and GENERIC_PINMUX_FUNCTIONS and its binding also completely follows up
pinctrl-bindings.txt in Documentation/devicetree/bindings/pinctrl/ to
implement.

Signed-off-by: Ryder.Lee <ryder.lee@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-18 14:52:37 -07:00
Sean Wang a1a503a8c3 pinctrl: mediatek: add pinctrl-mtk-common-v2 for all MediaTek pinctrls
Irregular register arrangement and distinct logic access from various
MediaTek SoCs would cause pinctrl-mtk-common to bloat and really hard to
maintain in the future so that the patch creates pinctrl-mtk-common-v2
based on the core of mt7622-pinctrl.

The goals pinctrl-mtk-common-v2 want to achieve are to hopefully support
all of MediaTek SoCs, and two kinds of dt-bindings being supported,
Linux generic pinctrl dt-binding mt7622 supports and MediaTek per-pin
dt-binding the other SoCs support the MT8183 and MT6765 incline to make
use of.

The patch starts to refactor MT7622 pinctrl driver first with splitting
out these portable ways from there such as table-based register operation
and drive strength control that is common in both kinds of driver.

Signed-off-by: Ryder.Lee <ryder.lee@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-18 14:52:34 -07:00
Linus Walleij 1c5fb66afa pinctrl: Include <linux/gpio/driver.h> nothing else
These drivers are GPIO drivers, and the do not need to use the
legacy header in <linux/gpio.h>, go directly for
<linux/gpio/driver.h> instead.

Replace any use of GPIOF_* with 0/1, these flags are for
consumers, not drivers.

Get rid of a few gpio_to_irq() users that was littering
around the place, use local callbacks or avoid using it at
all.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-14 15:10:57 +02:00
Linus Walleij e897b38665 pinctrl: at91-pio4: Get rid of legacy call
By just moving the atmel_gpio_to_irq() and calling the internal
function we can get rid of the driver calling back out into the
deprecated external consumer API.

Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-14 12:49:19 +02:00
Ludovic Desroches 0c3dfa1769 pinctrl: at91: don't use the same irqchip with multiple gpiochips
Sharing the same irqchip with multiple gpiochips is not a good
practice. For instance, when installing hooks, we change the state
of the irqchip. The initial state of the irqchip for the second
gpiochip to register is then disrupted.

Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-14 10:58:54 +02:00
Dan Carpenter b97760ae8e pinctrl: at91-pio4: fix has_config check in atmel_pctl_dt_subnode_to_map()
Smatch complains about this condition:

	if (has_config && num_pins >= 1)

The "has_config" variable is either uninitialized or true.  The
"num_pins" variable is unsigned and we verified that it is non-zero on
the lines before so we know "num_pines >= 1" is true.  Really, we could
just check "num_configs" directly and remove the "has_config" variable.

Fixes: 776180848b ("pinctrl: introduce driver for Atmel PIO4 controller")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-13 14:17:09 +02:00
Kuninori Morimoto a8b4d4cb9a pinctrl: rza1: Convert to SPDX identifiers
This patch updates license to use SPDX-License-Identifier
instead of verbose license text.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-11 12:25:44 +02:00
Kuninori Morimoto 63b6d7e762 pinctrl: sh-pfc: Convert to SPDX identifiers
This patch updates license to use SPDX-License-Identifier
instead of verbose license text.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-11 12:25:32 +02:00
Takeshi Kihara 2ef7a12f55 pinctrl: sh-pfc: r8a77995: Add MSIOF pins, groups and functions
This patch adds MSIOF{0,1,2,3} pins, groups and functions to R8A77995 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[ykaneko0929@gmail.com: fix the order of definitions]
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-11 12:14:06 +02:00
Takeshi Kihara 0a7cad486f pinctrl: sh-pfc: r8a77990: Add MSIOF pins, groups and functions
This patch adds MSIOF{0,1,2,3} pins, groups and functions to
the R8A77990 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-11 12:12:59 +02:00
Stephen Boyd 89c68b102f pinctrl: qcom: spmi-mpp: Fix drive strength setting
It looks like we parse the drive strength setting here, but never
actually write it into the hardware to update it. Parse the setting and
then write it at the end of the pinconf setting function so that it
actually sticks in the hardware.

Fixes: 0e948042c4 ("pinctrl: qcom: spmi-mpp: Implement support for sink mode")
Cc: Doug Anderson <dianders@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-10 09:31:02 +02:00
YueHaibing 9ae4987ebb pinctrl: sirf: atlas7: remove set but not used variables 'conf, bank'
Fixes gcc '-Wunused-but-set-variable' warning:

drivers/pinctrl/sirf/pinctrl-atlas7.c: In function 'atlas7_pinmux_resume_noirq':
drivers/pinctrl/sirf/pinctrl-atlas7.c:5545:6: warning:
 variable 'bank' set but not used [-Wunused-but-set-variable]
  u32 bank;

drivers/pinctrl/sirf/pinctrl-atlas7.c:5543:28: warning:
 variable 'conf' set but not used [-Wunused-but-set-variable]
  struct atlas7_pad_config *conf;

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-05 12:13:13 +02:00