Commit Graph

95 Commits

Author SHA1 Message Date
Emil Lundmark 5c2f117a22 clk: imx: fix integer overflow in AV PLL round rate
Since 'parent_rate * mfn' may overflow 32 bits, the result should be
stored using 64 bits.

The problem was discovered when trying to set the rate of the audio PLL
(pll4_post_div) on an i.MX6Q. The desired rate was 196.608 MHz, but
the actual rate returned was 192.000570 MHz. The round rate function should
have been able to return 196.608 MHz, i.e., the desired rate.

Fixes: ba7f4f557e ("clk: imx: correct AV PLL rate formula")
Cc: Anson Huang <b20788@freescale.com>
Signed-off-by: Emil Lundmark <emil@limesaudio.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-01 17:07:54 -07:00
Linus Torvalds a771151a83 ARM: SoC cleanups for v4.9
The cleanups for v4.9 are a little larger that usual, but thankfully
 that is almost exclusively due to removing a significant number of
 files that have become obsolete after the still ongoing conversion
 of old board files to devicetree.
 
 - for mach-omap2, which is still the largest platform in arch/arm/,
   the conversion to DT is finally complete after the Nokia N900 is
   now fully supported there, along with the omap3 LDP, and we can
   remove those two board files.
   If no regressions are found, another large cleanup for the platform
   will happen as a follow-up, removing dead code and restructuring
   the platform based on being DT-only.
 
 - In mach-imx, similar work is ongoing, but has not come that far.
   This time, we remove the obsolete board file for the i.MX1
   generation, which like i.MX25, i.MX5, i.MX6, and i.MX7 is now DT-only.
   The remaining board files are for i.MX2 and i.MX3 machines
   based on old ARM926 or ARM1136 cores that should work with DT
   in principle.
 
 - realview has just been converted from board files to DT, and a lot
   of code gets removed in the process. This is the last
   ARM/Keil/Versatile derived platform that was still using board
   files, the other ones being integrator, versatile and vexpress.
   We can probably merge the remaining code into a single directory
   in the near future.
 
 - clps711x had completed the conversion in v4.8, but we accidentally
   left the files in place that should have been deleted then.
 
 Conflicts: two files deleted here have been modified upstream,
 the changes can be discarded.
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Merge tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC cleanups from Arnd Bergmann:
 "The cleanups for v4.9 are a little larger that usual, but thankfully
  that is almost exclusively due to removing a significant number of
  files that have become obsolete after the still ongoing conversion of
  old board files to devicetree.

   - for mach-omap2, which is still the largest platform in arch/arm/,
     the conversion to DT is finally complete after the Nokia N900 is
     now fully supported there, along with the omap3 LDP, and we can
     remove those two board files. If no regressions are found, another
     large cleanup for the platform will happen as a follow-up, removing
     dead code and restructuring the platform based on being DT-only.

   - In mach-imx, similar work is ongoing, but has not come that far.
     This time, we remove the obsolete board file for the i.MX1
     generation, which like i.MX25, i.MX5, i.MX6, and i.MX7 is now
     DT-only. The remaining board files are for i.MX2 and i.MX3 machines
     based on old ARM926 or ARM1136 cores that should work with DT in
     principle.

   - realview has just been converted from board files to DT, and a lot
     of code gets removed in the process. This is the last
     ARM/Keil/Versatile derived platform that was still using board
     files, the other ones being integrator, versatile and vexpress. We
     can probably merge the remaining code into a single directory in
     the near future.

   - clps711x had completed the conversion in v4.8, but we accidentally
     left the files in place that should have been deleted then"

* tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (21 commits)
  ARM: select PCI_DOMAINS config from ARCH_MULTIPLATFORM
  ARM: stop *MIGHT_HAVE_PCI* config from being selected redundantly
  ARM: imx: (trivial) fix typo and grammar
  ARM: clps711x: remove extraneous files
  ARM: imx: use IS_ENABLED() instead of checking for built-in or module
  ARM: OMAP2+: use IS_ENABLED() instead of checking for built-in or module
  ARM: OMAP1: use IS_ENABLED() instead of checking for built-in or module
  ARM: imx: remove platform-mxc_rnga
  ARM: realview: imply device tree boot
  ARM: realview: no need to select SMP_ON_UP explicitly
  ARM: realview: delete the RealView board files
  ARM: imx: no need to select SMP_ON_UP explicitly
  ARM: i.MX: Move SOC_IMX1 into 'Device tree only'
  ARM: i.MX: Remove i.MX1 non-DT support
  ARM: i.MX: Remove i.MX1 Synertronixx SCB9328 board support
  ARM: i.MX: Remove i.MX1 Armadeus APF9328 board support
  ARM: mxs: remove obsolete startup code for TX28
  ARM: i.MX31 iomux: remove duplicates with alternate name
  ARM: i.MX31 iomux: remove plain duplicates
  ARM: OMAP2+: Drop legacy board file for LDP
  ...
2016-10-07 21:16:16 -07:00
Lucas Stach d8846023ae clk: imx6: initialize GPU clocks
Initialize the GPU clock muxes to sane inputs. Until now they have
not been changed from their default values, which means that both
GPU3D shader and GPU2D core were fed by clock inputs whose rates
exceed the maximium allowed frequency of the cores by as much as
200MHz.

This fixes a severe GPU stability issue on i.MX6DL.

Cc: stable@vger.kernel.org
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-20 16:57:15 -07:00
Lucas Stach b1d51b448e clk: imx6: fix i.MX6DL clock tree to reflect reality
The current clock tree only implements the minimal set of differences
between the i.MX6Q and the i.MX6DL, but that doesn't really reflect
reality.

Apply the following fixes to match the RM:
- DL has no GPU3D_SHADER_SEL/PODF, the shader domain is clocked by
  GPU3D_CORE
- GPU3D_SHADER_SEL/PODF has been repurposed as GPU2D_CORE_SEL/PODF
- GPU2D_CORE_SEL/PODF has been repurposed as MLB_SEL/PODF

Cc: stable@vger.kernel.org
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-20 16:52:37 -07:00
Kalle Kankare 377d6479d2 clk: imx53: Add clocks configuration
Add clocks configuration for CSI, FIRI and IEEE1588.

Signed-off-by: Fabien Lahoudere <fabien.lahoudere@collabora.co.uk>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-20 16:52:06 -07:00
Uwe Kleine-König ece59749c3 ARM: clk-imx35: annotate clk enum with number values
This helps to decode error messages like:

	[    0.000000] i.MX clk 82: register failed with -17

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-14 11:28:04 -07:00
Uwe Kleine-König fcff03813a ARM: clk-imx35: fix name for ckil clk
This fixes
	[    0.000000] i.MX clk 82: register failed with -17
because the name is duplicated.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Fixes: 3713e3f5e9 ("clk: imx35: define two clocks for rtc")
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-14 11:27:49 -07:00
Fabio Estevam 54fe0791fa clk: imx7d: Add PLL_AUDIO_TEST_DIV/POST_DIV clocks
Currently we see the following error when using the SAI audio
driver on mx7:

Division by zero in kernel.
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.8.0-rc3-next-20160823
Hardware name: Freescale i.MX7 Dual (Device Tree)
Backtrace:
[<c010b70c>] (dump_backtrace) from [<c010b8a8>] (show_stack+0x18)
r6:60000013 r5:ffffffff r4:00000000 r3:00000000
[<c010b890>] (show_stack) from [<c03e9324>] (dump_stack+0xb0/0xe)
[<c03e9274>] (dump_stack) from [<c010b578>] (__div0+0x18/0x20)
r8:00000000 r7:ffffffff r6:ffffffff r5:00000000 r4:00000000 r3:0
[<c010b560>] (__div0) from [<c03e795c>] (Ldiv0_64+0x8/0x18)
[<c06cd860>] (divider_get_val) from [<c06cda28>] (clk_divider_se)

This error happens due to the lack of definition of the
IMX7D_PLL_AUDIO_TEST_DIV/IMX7D_PLL_AUDIO_POST_DIV clocks.

Add support for them.

Tested on a imx7s-warp board.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-30 14:58:15 -07:00
Fabio Estevam 0698102576 clk: imx7d: Add SAI IPG clocks
The SAI_IPG clocks are enabled by the same bits that control SAI_ROOT_CLK
clocks, so represent them as shared clocks.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-19 12:53:43 -07:00
Fabio Estevam d5ebf5fabb clk: imx: Introduce clk_register_gate2()
Introduce imx_clk_gate2_shared2() which is similar to the existing
imx_clk_gate2_shared() and passes CLK_OPS_PARENT_ENABLE flag, which
is useful for i.MX7 shared clocks.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-19 12:53:41 -07:00
Fabio Estevam 96e9dff6dd clk: imx7d: Add the clock for SDMA
Add IMX7D_SDMA_CORE_CLK clock so that SDMA can be functional.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-19 12:53:36 -07:00
Fabio Estevam 1fd92dbaab clk: imx7d: do not set the parent of IMX7D_ENET_AXI_ROOT_SRC
Booting the kernel on a imx7s-warp leads to several warnings like these:

[    0.000000] ------------[ cut here ]------------
[    0.000000] WARNING: CPU: 0 PID: 0 at kernel/locking/lockdep.c:3536 lock_release+0x2f8/0x330
[    0.000000] releasing a pinned lock

[    0.000000] ------------[ cut here ]------------
[    0.000000] WARNING: CPU: 0 PID: 0 at kernel/locking/lockdep.c:2722 trace_hardirqs_on_caller+0x1ac/0x1f4
[    0.000000] DEBUG_LOCKS_WARN_ON(unlikely(early_boot_irqs_disabled))

[    0.000000] ---[ end trace cb88537fdc8fa201 ]---
[    0.000000] bad: scheduling from the idle thread!
[    0.000000] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G        W       4.7.0-rc7-next-20160715 #404

[    0.000000] ------------[ cut here ]------------
[    0.000000] WARNING: CPU: 0 PID: 0 at kernel/time/sched_clock.c:179 sched_clock_register+0x44/0x1f8
[    0.000000] Modules linked in:

[    0.000591] ------------[ cut here ]------------
[    0.000610] WARNING: CPU: 0 PID: 0 at kernel/time/sched_clock.c:179 sched_clock_register+0x44/0x1f8

[    0.002084] ------------[ cut here ]------------
[    0.002104] WARNING: CPU: 0 PID: 0 at init/main.c:576 start_kernel+0x258/0x3b0
[    0.002114] Interrupts were enabled early

This fix is along the same lines as 5e33ebff7e ("clk: imx7d: do not
set parent of ethernet time/ref clocks") and the explanation from that
commit is:

"The reason for the warning is that setting the parent enables the ENET
 PLL since we are using CLK_OPS_PARENT_ENABLE. Enabling the ENET PLL can
 cause clk_pllv3_wait_lock to sleep. See also:
 commit fc8726a2c0 ("clk: core: support clocks which requires parents
 enable (part 2)")."

imx7s-warp does not even use the FEC interface, so we should not really
configure the parent of IMX7D_ENET_AXI_ROOT_SRC in the common MX7 clock
driver code.

The dts file should use the assigned-clocks/assigned-clock-parents method,
so simply remove the configuration of IMX7D_ENET_AXI_ROOT_SRC parent.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-11 18:49:20 -07:00
Alexander Shiyan e1291cffcc ARM: i.MX: Remove i.MX1 non-DT support
This patch removes registration helpers and support files,
used for non-DT i.MX1 targets.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-08-09 22:47:26 +08:00
Stefan Agner 5e33ebff7e clk: imx7d: do not set parent of ethernet time/ref clocks
All device trees currently in mainline specify the time clock parent
using the assigned-clocks/assigned-clock-parents method, there is no
need to statically assign the parent in the core clock driver.
Also all current boards provide an Ethernet reference clock for the
PHY externally, hence configuring the internal PHY reference clock.

Furthermore, and the actual driver of this patch, specify ethernet
related parents at that early point in boot leads to a warning:
bad: scheduling from the idle thread!

The reason for the warning is that setting the parent enables the ENET
PLL since we are using CLK_OPS_PARENT_ENABLE. Enabling the ENET PLL can
cause clk_pllv3_wait_lock to sleep. See also:
commit fc8726a2c0 ("clk: core: support clocks which requires parents
enable (part 2)").

Note that setting the ENET AXI root clock parent also requires ENET
PLL to be enabled. However, U-Boot typically leaves the ENET PLL on,
hence when the framework sets the parent of the first clock, it does
not need to wait for the PLL to come up. But because there is currently
no user of that clock, the PLL gets disabled after setting the parent.
Therefore, subsequent reparenting calls of any clock which somehow rely
on the ENET PLL, need to reenable the ENET PLL which leads to a sleep.
Removing those subsequent reparenting calls works around this issue.

Also remove comments. The code is really verbose enough.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Tested-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160703174813.13970-1-stefan@agner.ch
2016-07-12 15:31:14 -07:00
Stefan Agner a06498297d clk: imx: vf610: Disable automatic clock gating for lpuart in LPSTOP mode
In order to allow wake support in STOP sleep mode, clocks are needed. Use
imx_clk_gate2_cgr to disable automatic clock gating in low power mode STOP.
This allows to enable wake by UART using:
echo enabled > /sys/class/tty/ttyLP0/power/wakeup

However, if wake is not enabled, the driver should disable the clocks explicitly
to save power.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160628053235.5114-3-bhuvanchandra.dv@toradex.com
2016-07-08 11:38:17 -07:00
Dong Aisheng e8e628fb3f clk: imx7d: only enable minimum required clocks
Formerly clk core does not support imx7d clock type well that all
its clock operations requires the parent clock on.
Therefore we enabled all clocks by default in clock driver
initialization for other module clocks operate well.

After patch 'clk: imx7d: using api with flag CLK_OPS_PARENT_ENABLE',
clk core can handle such clock type well, so we don't have to enable
them all by default anymore. Instead, we only enable a minimum required
set of clocks.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-07-01 17:43:21 -07:00
Dong Aisheng cbeac74a58 clk: imx7d: using api with flag CLK_OPS_PARENT_ENABLE
i.MX7D requires all clocks operations including enable/disable,
rate change and re-parent with its parent clock on.
Changing to the correct APIs to tell clk core such requirement.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-07-01 17:43:20 -07:00
Dong Aisheng 39c29498ce clk: imx: add clk api for supporting CLK_OPS_PARENT_ENABLE clocks
IMX SoCs like i.MX7D requires using CLK_OPS_PARENT_ENABLE flags,
adding the corresponding clock APIs variants for easily to use.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-07-01 17:43:19 -07:00
Dong Aisheng 5afc99417f clk: imx: re-order and concentrate the same type of clk api
Re-order and concentrate the same type of clk api for better
code maintenance.

Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-07-01 17:43:18 -07:00
Dong Aisheng bfa10f7d9a clk: imx6ul: fix gpt2 clock names
fix gpt2 clock names

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-16 09:05:55 +08:00
Dong Aisheng c684766308 clk: imx: refine the powerdown bit of clk-pllv3
The powerdown bit is a bit confused, let's change it to power_bit
to relfect both powerdown and powerup case according to different
plls.

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-16 09:05:05 +08:00
Dong Aisheng b3e76bdc0b clk: imx: clk-pllv3: fix incorrect handle of enet powerdown bit
After commit f53947456f ("ARM: clk: imx: update pllv3 to support imx7"),
the former used BM_PLL_POWER bit is not correct anymore for IMX7 ENET.
Instead, pll->powerdown holds the correct bit, so using powerdown bit
in clk_pllv3_{prepare | unprepare} functions.

Fixes: f53947456f ("ARM: clk: imx: update pllv3 to support imx7")
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-13 10:53:32 +08:00
Dong Aisheng f83d31635c clk: imx: fix pll clock parents
pllx_bypass_src mux shouldn't be the parent of pllx clock
since it's only valid when when pllx BYPASS bit is set.
Thus it is actually one parent of pllx_bypass only.

Instead, pllx parent should be fixed to osc according to
reference manual.
Other plls have the same issue.

e.g. before fix, the pll tree is:
osc                                      6            6    24000000          0 0
   pll1_bypass_src                       0            0    24000000          0 0
      pll1                               0            0   792000000          0 0
         pll1_bypass                     0            0   792000000          0 0
            pll1_sys                     0            0   792000000          0 0

After the fix, it's:
osc                                      6            6    24000000          0 0
   pll1                                  0            0   792000000          0 0
      pll1_bypass                        0            0   792000000          0 0
         pll1_sys                        0            0   792000000          0 0

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-12 21:21:41 +08:00
Anson Huang 1479475495 clk: imx7d: correct dram pll type
DRAM PLL is a audio/video type PLL, need to correct
it to get correct ops of PLL.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-12 19:26:05 +08:00
Anson Huang 7e797d9fc8 clk: imx7d: correct dram root clk parent select
DRAM root clk should be either from pll dram main clk
or dram alt root clk.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-12 19:26:01 +08:00
Anson Huang ba7f4f557e clk: imx: correct AV PLL rate formula
The audio/video PLL's rate calculation is as below in RM:

Fref * (DIV_SELECT + NUM / DENOM), in origin clk-pllv3's
code, below code is used:

(parent_rate * div) + ((parent_rate / mfd) * mfn

as it does NOT consider the float data using div, so below
formula should be used as a decent method:

(parent_rate * div) + ((parent_rate * mfn) / mfd)

and we also need to consider parent_rate * mfd may overflow
a 32 bit value, 64 bit value should be used.

After updating this formula, the dram PLL's rate is
1066MHz, which is correct, while the old formula gets
1056MHz.

[Aisheng: fix clk_pllv3_av_round_rate too]

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-12 19:25:38 +08:00
Stephen Boyd d8609a3a2e Merge tag 'imx-clk-fixes-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next
Pull some non-critical i.MX clk fixes from Shawn Guo:

 * Fix the commit 3713e3f5e9 ("clk: imx35: define two clocks for rtc")
   which messed up the clock enumeration when adding new clock.

* tag 'imx-clk-fixes-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  ARM: dts: imx35: restore existing used clock enumeration
  clk: imx6q: fix typo in CAN clock definition
2016-05-12 14:48:26 -07:00
Stefan Agner 92a847e360 clk: imx7d: fix ahb clock mux 1
The clock parent of the AHB root clock when using mux option 1
is the SYS PLL 270MHz clock. This is specified in  Table 5-11
Clock Root Table of the i.MX 7Dual Applications Processor
Reference Manual.

While it could be a documentation error, the 270MHz parent is
also mentioned in the boot ROM configuration in Table 6-28: The
clock is by default at 135MHz due to a POST_PODF value of 1
(=> divider of 2).

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-05-03 20:35:38 +08:00
Stefan Agner 585a60f24b clk: imx: return correct frequency for Ethernet PLL
The i.MX 7 designs Ethernet PLL provides a 1000MHz reference clock.
Store the reference clock in the clk_pllv3 structure according to
the PLL type.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-04-27 10:02:04 +08:00
Alexander Kurz 3397c2c45b ARM: dts: imx35: restore existing used clock enumeration
A new element got inserted into enum mx35_clks with commit 3713e3f5e9
("clk: imx35: define two clocks for rtc"). This insertion shifted most
nummerical clock assignments to a new nummerical value which in turn
rendered most hardcoded nummeric values in imx35.dtsi incorrect.

Restore the existing order by moving the newly introduced clock to the
end of the enum. Update the dts documentation accordingly.

Signed-off-by: Alexander Kurz <akurz@blala.de>
Fixes: 3713e3f5e9 ("clk: imx35: define two clocks for rtc")
Cc: <stable@vger.kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-04-18 12:37:21 +08:00
Lothar Waßmann 7196c52c93 clk: imx6q: fix typo in CAN clock definition
commit ee36027427 ("clk: imx: Add clock support for imx6qp")
introduced a regression due to a subtle typo in the 'can_root' clock
definition. The effect is that trying to configure the bitrate of the
can interfaces fails with -EDOM or produces a division by zero error
due to the clock_freq of the can serial clock being reported as '0'.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Fixes: ee36027427 ("clk: imx: Add clock support for imx6qp")
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-04-13 15:27:15 +08:00
Stefan Agner afd7350a9a clk: imx: vf610: add TCON ipg clock
Add the ipg (bus) clock for the TCON modules (Timing Controller). This
module is required by the new DCU DRM driver, since the display signals
pass through TCON.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-04-12 09:22:17 +08:00
Stefan Agner 3218b21ab0 clk: imx: vf610: fix DCU clock tree
Similar to an earlier fix for the SAI clocks, the DCU clock hierarchy
mixes the bus clock with the display controllers pixel clock. Tests
have shown that the gates in CCM_CCGR3/9 registers do not control
the DCU pixel clock, but only the register access clock (bus clock).

Fix this by defining the parent clock of VF610_CLK_DCUx to be the bus
clock (ipg_bus).

Since the clock has not been used far, there are no further changes
needed.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-04-12 09:21:53 +08:00
Gary Bisson 4aba2755b8 clk: imx: add ckil clock for i.MX7
Add the necessary clock to use the ckil on i.MX7.

Inspired from the following patch:
https://github.com/boundarydevices/linux-imx6/commit/b80e8271

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-04-06 17:04:26 +08:00
Stefan Agner 4cfe6aebb2 clk: imx: vf610: add suspend/resume support
The clock register are lost when enterying LPSTOPx, hence provide
suspend/resume functions restoring them. The clock gates get
restored by the individual driver, hence we do not need to restore
them here.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-03-31 17:02:06 +08:00
Stefan Agner 349efbeedb clk: imx: vf610: add WKPU unit
Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-03-31 17:02:02 +08:00
Stefan Agner 0da15d36a9 clk: imx: vf610: leave DDR clock on
To use STOP mode without putting DDR3 into self-refresh mode, we
need to keep the DDR clock enabled. Use the new gate configuration
with a value of 2 to make sure that the clock is enabled in RUN,
WAIT and STOP mode.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-03-31 17:01:58 +08:00
Stefan Agner 456829228f clk: imx: clk-gate2: allow custom gate configuration
The 2-bit gates found i.MX and Vybrid SoC support different clock
configuration:

0b00: clk disabled
0b01: clk enabled in RUN mode but disabled in WAIT and STOP mode
0b10: clk enabled in RUN, WAIT and STOP mode (only Vybrid)
0b11: clk enabled in RUN and WAIT mode

For some clocks, we might want to configure different behaviour,
e.g. a memory clock should be on even in STOP mode. Add a new
function imx_clk_gate2_cgr which allow to configure specific
gate values through the cgr_val parameter.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-03-31 17:01:55 +08:00
Fabio Estevam 0b55257ebc clk: imx6sx: Register SAI clocks as shared clocks
SAIx and SAIx_IPG share the same bit fields in the CCM registers, so
we should better register them via imx_clk_gate2_shared().

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-03-31 14:36:42 +08:00
Stephen Boyd 38c7035f9c clk: imx: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:44:26 -08:00
Stephen Boyd 5788923b27 Merge tag 'imx-clk-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next
Pull i.MX clk updates from Shawn Guo:

The i.MX clock update for 4.6:
- Add the clock driver support for the latest i.MX6 family SoCs
  addition - i.MX6QP.
- Clean up the whitespace in i.MX6UL clock driver and add the missing
  KPP clock.
- Correct pwm7 clock name in i.MX6UL clock driver.

* tag 'imx-clk-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  clk: imx: add kpp clock for i.MX6UL
  clk: imx: whitespace cleanup; no functional change
  clk: imx: correct pwm7 clock name in driver for i.MX6UL
  clk: imx: Add clock support for imx6qp
2016-03-02 14:31:47 -08:00
Lothar Waßmann f6c3aec2f7 clk: imx: add kpp clock for i.MX6UL
Add the necessary clock to use the KPP interface on i.MX6UL.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-02-28 10:45:29 +08:00
Lothar Waßmann 9797d81936 clk: imx: whitespace cleanup; no functional change
remove whitespace before TAB.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-02-28 10:45:13 +08:00
Anatolij Gustschin 81a467efe3 clk: imx: correct pwm7 clock name in driver for i.MX6UL
Don't capitalize p in the pwm7 clock name.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-02-18 22:25:19 +08:00
Bai Ping ee36027427 clk: imx: Add clock support for imx6qp
most of the clock tree structures on i.MX6 Quad Plus are
same as on i.MX6Q. there still some differences between
these two SOCs. compared to the i.XM6Q, the differents of
clocks on i.MX6QP is mainly on:

1. New clock gate added to support the PRE and PRG modules
2. 24MHz OSC clock option added to the UART, IPG, ECSPI, and
   CAN clock roots.
3. MMDC channel 1 clock gate is now controllable.
4. clock gating added to the LDB_DIx_IPU clocks on i.MX6QP
5. EMI clock root divider fix
6. other updates fo CSCMRx, CSCDRx and CS2CDR registers.

detailed infomation, please refer to the i.MX6QP RM.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-02-14 11:06:29 +08:00
Geliang Tang 5fd9c05c84 clk: move the common clock's to_clk_*(_hw) macros to clk-provider.h
to_clk_*(_hw) macros have been repeatedly defined in many places.
This patch moves all the to_clk_*(_hw) definitions in the common
clock framework to public header clk-provider.h, and drop the local
definitions.

Signed-off-by: Geliang Tang <geliangtang@163.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 12:59:50 -08:00
Michael Turquette b8f15e7119 Merge commit 'fe5fa8fbd4d47f40a45fa29ee1abdb10cb061ec2' into clk-next 2015-12-22 11:57:35 -08:00
Michael Turquette fcd5ac1a41 Merge tag 'imx-clk-v4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next
The i.MX clock updates for 4.5:
- Add is_prepared function callback for pllv3 clock driver
- Use imx_check_clocks() on imx6ul and imx7d clock drivers to save
  some code
- Add a core clock for imx7d to support generic cpufreq driver
- Support imx6q clock routing with OSC to anaclk2/2b
- To support more precise pixel clocks on imx5, allow ipu_di_sel clock
  selectors to influence the PLLs that they are derived from
- A cleanup on imx25 OSC clock
2015-12-22 11:57:34 -08:00
Linus Torvalds 097b285d32 ARM: SoC fixes for 4.4-rc
Here are a bunch of small bug fixes for various ARM platforms, nothing
 really sticks out this week, most of either fixes bugs in code that was
 just added in 4.4, or that has been broken for many years without anyone
 noticing.
 
 at91/sama5d2
 - fix sama5de hardware setup of sd/mmc interface
 - proper selection of pinctrl drivers. PIO4 is necessary for sama5d2
 
 berlin
 - fix incorrect clock input for SDIO
 
 exynos
 - Fix potential NULL pointer dereference in Exynos PMU driver.
 
 imx
 - Fix vf610 SAI clock configuration bug which is discovered by
   the newly added master mode support in SAI audio driver.
 - Fix buggy L2 cache latency values in vf610 device trees, which may
   cause system hang when cpu runs at a higher frequency.
 
 ixp4xx
 - fix prototypes for readl/writel functions
 
 ls2080a
 - use little-endian register access for GPIO and SDHCI
 
 omap
 - Fix clock source for ARM TWD and global timers on am437x
 - Always select REGULATOR_FIXED_VOLTAGE for omap2+ instead of
   when MACH_OMAP3_PANDORA is selected
 - Fix SPI DMA handles for dm816x as only some were mapped
 - Fix up mbox cells for dm816x to make mailbox usable
 
 pxa
 - use PWM lookup table for all ezx machines
 
 s3c24xx
 - Remove incorrect __init annotation from s3c24xx cpufreq driver structures.
 
 versatile
 - fix PCI IRQ mapping on Versatile PB
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Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Arnd Bergmann:
 "Here are a bunch of small bug fixes for various ARM platforms, nothing
  really sticks out this week, most of either fixes bugs in code that
  was just added in 4.4, or that has been broken for many years without
  anyone noticing.

  at91/sama5d2:
   - fix sama5de hardware setup of sd/mmc interface
   - proper selection of pinctrl drivers.  PIO4 is necessary for sama5d2

  berlin:
   - fix incorrect clock input for SDIO

  exynos:
   - Fix potential NULL pointer dereference in Exynos PMU driver.

  imx:
   - Fix vf610 SAI clock configuration bug which is discovered by the
     newly added master mode support in SAI audio driver.
   - Fix buggy L2 cache latency values in vf610 device trees, which may
     cause system hang when cpu runs at a higher frequency.

  ixp4xx:
   - fix prototypes for readl/writel functions

  ls2080a:
   - use little-endian register access for GPIO and SDHCI

  omap:
   - Fix clock source for ARM TWD and global timers on am437x
   - Always select REGULATOR_FIXED_VOLTAGE for omap2+ instead of when
     MACH_OMAP3_PANDORA is selected
   - Fix SPI DMA handles for dm816x as only some were mapped
   - Fix up mbox cells for dm816x to make mailbox usable

  pxa:
   - use PWM lookup table for all ezx machines

  s3c24xx:
   - Remove incorrect __init annotation from s3c24xx cpufreq driver
     structures.

  versatile:
   - fix PCI IRQ mapping on Versatile PB"

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ls2080a/dts: Add little endian property for GPIO IP block
  dt-bindings: define little-endian property for QorIQ GPIO
  ARM64: dts: ls2080a: fix eSDHC endianness
  ARM: dts: vf610: use reset values for L2 cache latencies
  ARM: pxa: use PWM lookup table for all machines
  ARM: dts: berlin: add 2nd clock for BG2Q sdhci0 and sdhci1
  ARM: dts: berlin: correct BG2Q's sdhci2 2nd clock
  ARM: dts: am4372: fix clock source for arm twd and global timers
  ARM: at91: fix pinctrl driver selection
  ARM: at91/dt: add always-on to 1.8V regulator
  ARM: dts: vf610: fix clock definition for SAI2
  ARM: imx: clk-vf610: fix SAI clock tree
  ARM: ixp4xx: fix read{b,w,l} return types
  irqchip/versatile-fpga: Fix PCI IRQ mapping on Versatile PB
  ARM: OMAP2+: enable REGULATOR_FIXED_VOLTAGE
  ARM: dts: add dm816x missing spi DT dma handles
  ARM: dts: add dm816x missing #mbox-cells
  cpufreq: s3c24xx: Do not mark s3c2410_plls_add as __init
  ARM: EXYNOS: Fix potential NULL pointer access in exynos_sys_powerdown_conf
2015-12-12 16:43:44 -08:00
Patrick Brünn c20737a2a7 clk: imx5: ipu_di_sel clocks can set parent rates
To obtain exact pixel clocks, allow the DI clock selectors to influence
the PLLs that they are derived from.

Commit 4591b13289 ("ARM: i.MX6: ipu_di_sel clocks can set parent
rates") did this for i.MX6.
Port it to enable high display resolutions on i.MX53 based platforms
such as CX9020 Embedded PC, too.

Signed-off-by: Patrick Brünn <p.bruenn@beckhoff.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-12-02 21:02:33 +08:00