This patch adds a few additional cpu feature overrides so that they do not
need to be probed at runtime.
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/19914/
Cc: James Hogan <jhogan@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
This patch disables irq on reboot to fix hang issues that were observed
due to pending interrupts.
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/19913/
Cc: James Hogan <jhogan@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
This patch adds support for 2 new types of QCA silicon. TP9343 is
essentially the same as the QCA956X but is licensed by TPLink.
Signed-off-by: Weijie Gao <hackpascal@gmail.com>
Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/19911/
Cc: James Hogan <jhogan@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
This patch adds many new registers for various QCA MIPS SoCs. The patch is
an aggragate of many contributions made to OpenWrt.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Henryk Heisig <hyniu@o2.pl>
Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
Signed-off-by: Weijie Gao <hackpascal@gmail.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: Julien Dusser <julien.dusser@free.fr>
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/19910/
Cc: James Hogan <jhogan@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
According to the QCA u-boot source the "PCIE Phase Lock Loop
Configuration (PCIE_PLL_CONFIG)" register is for all SoCs except the
QCA955X and QCA956X at offset 0x10.
Since the PCIE PLL config register is only defined for the AR724x fix
only this value. The value is wrong since the day it was added and isn't
used by any driver yet.
Signed-off-by: Mathias Kresin <dev@kresin.me>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16048/
Signed-off-by: James Hogan <jhogan@kernel.org>
The driver stays the same but the initialization changes a bit.
For OF boards we now get the memory map from the OF node and use
a linear mapping instead of the legacy mapping. For legacy boards
we still use a legacy mapping and just pass down all the parameters
from the board init code.
Signed-off-by: Alban Bedel <albeu@free.fr>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Link: https://lkml.kernel.org/r/1453553867-27003-1-git-send-email-albeu@free.fr
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Move the declaration of ath79_ddr_wb_flush() to asm/mach-ath79/ath79.h
to allow using it from drivers. This is needed to move the CPU IRQ
driver to drivers/irqchip.
Signed-off-by: Alban Bedel <albeu@free.fr>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Alexander Couzens <lynxis@fe80.eu>
Cc: Joel Porquet <joel@porquet.org>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11502/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Currently CONFIG_ARCH_HAVE_CUSTOM_GPIO_H is defined for all MIPS
machines, and each machine type provides its own gpio.h. However
only a handful really implement the GPIO API, most just forward
everythings to gpiolib.
The Alchemy machine is notable as it provides a system to allow
implementing the GPIO API at the board level. But it is not used by
any board currently supported, so it can also be removed.
For most machine types we can just remove the custom gpio.h, as well
as the custom wrappers if some exists. Some of the code found in
the wrappers must be moved to the respective GPIO driver.
A few more fixes are need in some drivers as they rely on linux/gpio.h
to provides some machine specific definitions, or used asm/gpio.h
instead of linux/gpio.h for the gpio API.
Signed-off-by: Alban Bedel <albeu@free.fr>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-mips@linux-mips.org
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Cc: Rafał Miłecki <zajec5@gmail.com>
Cc: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Cc: Tejun Heo <tj@kernel.org>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Cc: Florian Fainelli <florian@openwrt.org>
Cc: Manuel Lauss <manuel.lauss@gmail.com>
Cc: Joe Perches <joe@perches.com>
Cc: Daniel Walter <dwalter@google.com>
Cc: Sergey Ryazanov <ryazanov.s.a@gmail.com>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: James Hartley <james.hartley@imgtec.com>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Jiri Kosina <jkosina@suse.cz>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Wolfram Sang <wsa@the-dreams.de>
Cc: Randy Dunlap <rdunlap@infradead.org>
Cc: Varka Bhadram <varkabhadram@gmail.com>
Cc: Masanari Iida <standby24x7@gmail.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Michael Buesch <m@bues.ch>
Cc: abdoulaye berthe <berthe.ab@gmail.com>
Cc: linux-kernel@vger.kernel.org
Cc: linux-ide@vger.kernel.org
Cc: linux-gpio@vger.kernel.org
Cc: linux-input@vger.kernel.org
Cc: netdev@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10828/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Pull MIPS updates from Ralf Baechle:
- Improvements to the tlb_dump code
- KVM fixes
- Add support for appended DTB
- Minor improvements to the R12000 support
- Minor improvements to the R12000 support
- Various platform improvments for BCM47xx
- The usual pile of minor cleanups
- A number of BPF fixes and improvments
- Some improvments to the support for R3000 and DECstations
- Some improvments to the ATH79 platform support
- A major patchset for the JZ4740 SOC adding support for the CI20 platform
- Add support for the Pistachio SOC
- Minor BMIPS/BCM63xx platform support improvments.
- Avoid "SYNC 0" as memory barrier when unlocking spinlocks
- Add support for the XWR-1750 board.
- Paul's __cpuinit/__cpuinitdata cleanups.
- New Malta CPU board support large memory so enable ZONE_DMA32.
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (131 commits)
MIPS: spinlock: Adjust arch_spin_lock back-off time
MIPS: asmmacro: Ensure 64-bit FP registers are used with MSA
MIPS: BCM47xx: Simplify handling SPROM revisions
MIPS: Cobalt Don't use module_init in non-modular MTD registration.
MIPS: BCM47xx: Move NVRAM driver to the drivers/firmware/
MIPS: use for_each_sg()
MIPS: BCM47xx: Don't select BCMA_HOST_PCI
MIPS: BCM47xx: Add helper variable for storing NVRAM length
MIPS: IRQ/IP27: Move IRQ allocation API to platform code.
MIPS: Replace smp_mb with release barrier function in unlocks.
MIPS: i8259: DT support
MIPS: Malta: Basic DT plumbing
MIPS: include errno.h for ENODEV in mips-cm.h
MIPS: Define GCR_GIC_STATUS register fields
MIPS: BPF: Introduce BPF ASM helpers
MIPS: BPF: Use BPF register names to describe the ABI
MIPS: BPF: Move register definition to the BPF header
MIPS: net: BPF: Replace RSIZE with SZREG
MIPS: BPF: Free up some callee-saved registers
MIPS: Xtalk: Update xwidget.h with known Xtalk device numbers
...
The DDR controller need to be used by the IRQ controller to flush
the write buffer of some devices before running the IRQ handler.
It is also used by the PCI controller to setup the PCI memory windows.
The current interface used to access the DDR controller doesn't
provides any useful abstraction and simply rely on a shared global
pointer.
Replace this by a simple API to setup the PCI memory windows and use
the write buffer flush independently of the SoC type. That remove the
need for the shared global pointer, simplify the IRQ handler code.
[ralf@linux-mips.org: Folded in Alban Bedel's follup fix.]
Signed-off-by: Alban Bedel <albeu@free.fr>
Cc: linux-mips@linux-mips.org
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: Wolfram Sang <wsa@the-dreams.de>
Cc: Sergey Ryazanov <ryazanov.s.a@gmail.com>
Cc: Gabor Juhos <juhosg@openwrt.org>
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9773/
Patchwork: http://patchwork.linux-mips.org/patch/10543/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This register is named PLL_FB and is not a divider but a multiplier.
To make things less confusing rename the ARxxxx_PLL_DIV_SHIFT and
ARxxxx_PLL_DIV_MASK macros to ARxxxx_PLL_FB_SHIFT and
ARxxxx_PLL_FB_MASK.
Signed-off-by: Alban Bedel <albeu@free.fr>
Cc: linux-mips@linux-mips.org
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: Wolfram Sang <wsa@the-dreams.de>
Cc: Sergey Ryazanov <ryazanov.s.a@gmail.com>
Cc: Gabor Juhos <juhosg@openwrt.org>
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9772/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Set the OF node of the spi controller and use the generic GPIO based
chip select instead of the custom controller data. As the controller
data isn't used by any board just drop it.
Signed-off-by: Alban Bedel <albeu@free.fr>
Signed-off-by: Mark Brown <broonie@kernel.org>
11 platforms require at least one of these workarounds to be enabled; 22
platforms do not. In the latter case we can fall back to a generic version.
Note that this also deletes an orphaned reference to RM9000_CDEX_SMP_WAR.
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Cc: James Hartley <james.hartley@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/9567/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
None of these files are actually using any __init type directives
and hence don't need to include <linux/init.h>. Most are just a
left over from __devinit and __cpuinit removal, or simply due to
code getting copied from one driver to the next.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6320/
In commit 15ef17f622
(tty: ar933x_uart: use the clk API to get the uart
clock), the AR933x UART driver for has been converted
to get the uart clock rate via the clock API and it
does not use the platform data anymore.
Remove the ar933x_uart_platform.h header file and get
rid of the superfluous variable and initialization code
in platform setup.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5832/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The ath79 code supports various SoCs which are using either a 24Kc
or a 74Kc core. The 74Kc core has DSP support, so don't hardwire
the values to zero.
Commit 00dc5ce2a6 (MIPS: ath79: don't
hardcode the unavailability of the DSP ASE) has fixed this already,
but that change got reverted by 475032564e
(MIPS: Hardwire detection of DSP ASE Rev 2 for systems, as required.)
Reported-by: Helmut Schaa <helmut.schaa@googlemail.com>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5750/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Register platfom devices for the built-in USB
controllers of the SoCs.
Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4952/
Signed-off-by: John Crispin <blogic@openwrt.org>
Add SoC specific PCI IRQ map, and register platform
devices for the two built-in PCIe RCs.
Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4951/
Signed-off-by: John Crispin <blogic@openwrt.org>
The SoC has a built-in wireless MAC. Register a platform
device for that to make it usable with the ath9k driver.
Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4956/
Signed-off-by: John Crispin <blogic@openwrt.org>
The ath79_device_reset_* are causing BUG when
those are used on the QCA955x SoCs. The patch
adds the required code to avoid that.
Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4948/
Signed-off-by: John Crispin <blogic@openwrt.org>
The existing code can handle the GPIO controller of
the QCA955x SoCs. Add a minimal glue code to make it
working.
Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4947/
Signed-off-by: John Crispin <blogic@openwrt.org>
The IRQ routing in the QCA955x SoCs is slightly
different from the routing implemented in the
already supported SoCs.
Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4955/
Signed-off-by: John Crispin <blogic@openwrt.org>
The patch adds code to get various clock frequencies
from the PLLs used in the QCA955x SoCs.
Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4945/
Signed-off-by: John Crispin <blogic@openwrt.org>
Also add 'soc_is_qca955[68x]' helper functions
and a Kconfig symbol for the SoC family.
Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4943/
Signed-off-by: John Crispin <blogic@openwrt.org>
The patch allows to see kernel messages on the
QCA955X SoCs in early boot stage.
Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4944/
Signed-off-by: John Crispin <blogic@openwrt.org>
Use the ATH79_MISC_IRQ() macro instead.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4930/
Signed-off-by: John Crispin <blogic@openwrt.org>
Remove the individual ATH79_CPU_IRQ_* constants and
use the new macro instead of those.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4929/
Signed-off-by: John Crispin <blogic@openwrt.org>
The command register of the PCI controller is
not initialized correctly by the bootloader on
some boards and this leads to non working PCI
bus.
Add code to initialize the command register
from the Linux code to avoid this.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4916/
Signed-off-by: John Crispin <blogic@openwrt.org>
The functions are unused now, so remove them.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4909/
Signed-off-by: John Crispin <blogic@openwrt.org>
The constants will be used by a subsequent patch.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4907/
Signed-off-by: John Crispin <blogic@openwrt.org>
The current code uses multiple if statements for
demultiplexing the different interrupt sources.
Additionally, the MISC interrupt controller has
32 interrupt sources and the current code does not
handles all of them.
Get rid of the if statements and process all interrupt
sources in a loop to fix these issues.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4874/
Signed-off-by: John Crispin <blogic@openwrt.org>
GPIO function selection is not working on the AR934x
SoCs because the offset of the function selection
register is different on those.
Add a helper routine which returns the correct
register address based on the SoC type, and use
that in the 'ath79_gpio_function_*' routines.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4870/
Signed-off-by: John Crispin <blogic@openwrt.org>
Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Most supported systems currently hardwire cpu_has_dsp to 0, so we also
can disable support for cpu_has_dsp2 resulting in a slightly smaller
kernel.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Besides the CPU and DDR PLLs, the CPU and DDR frequencies
can be derived from other PLLs in the SRIF block on the
AR934x SoCs. The current code does not checks if the SRIF
PLLs are used and this can lead to incorrectly calculated
CPU/DDR frequencies.
Fix it by calculating the frequencies from SRIF PLLs if
those are used on a given board.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: <stable@vger.kernel.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4324/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The ath79 platform code allows to run a single kernel image on various
SoCs which are based on the 24Kc and 74Kc cores. The current code
explicitely disables the DSP ASE, but that is available in the 74Kc core.
Remove the override in order to let the kernel to detect the availability
of the DSP ASE at runtime.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4222/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The AR724X specific PCI code can be used for the
AR934X SoCs, however it can be selected only if
SOC_AR724X is set.
Introduce a new Kconfig symbol in order to be able
to use the code for AR934X as well.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
Cc: linux-mips@linux-mips.org
Cc: mcgrof@infradead.org
Patchwork: https://patchwork.linux-mips.org/patch/3514/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Add copyright records according to the recent changes in
the PCI code. Also fix up the descriptions.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3503/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Felix Fietkau