Fix a compilation error caused by pinconf_generic_parse_dt_config() not
being defined on !CONFIG_OF platforms by guarding the whole DT node
parsing code with #ifdef CONFIG_OF.
Defining a pinconf_generic_parse_dt_config() on !CONFIG_OF would have
been possible as well, but would have resulted in a larger code size on
!CONFIG_OF platforms (such as arch/sh).
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
tidyup MMC_D1 pin for r8a7778 SoC
fix two pin numbers and add HSCIF pin groups to r8a7790 SoC
add pinmux data for MMCIF and SDHI interfaces for r8a73a4 SoC
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRwa8VAAoJENfPZGlqN0++L+4P/3/nWnOTcEBi1nlDYyZW1DC7
C7xv7cjK9hcOwydS1jqm5VrPVkNghEv7cQog1vD0aIJgEi8qnCrVBG2Y/QdIMX0p
JIFVFVoi5nMgpH5OQUAN1uuRK/6w1phAe34BUsTPfQBcd0sqKki0lc1FhUpUaXHy
hvEMi1yymLM9d6aJhXOZjcPXTXRbJbWyTnzZQ2SGVxHCqvgQ3UVg2gXjH7uo6nrv
0EIGEq0FPvBMwgbPF28Fo/Wp5OEs1n1J+NUiWx9LjrsCdKBnppcweFA1XD0drkis
a/NiGvmbTMc3FioiZg+6rZb+QOa2Rj3AXhPVsSRjsPY90psTLzg6R9jXQrDTdfV9
HYv5mYhbXFsWLjk0CWqciVQrH+xv6V+hPZ9IzOsjecq6yJt/ub1TEa+u+iK1pyaf
f4u0yy83rqW2NFaB91dkwPQgUZD45RDAW7kN5gzIetCuL7qpOMbC2tvzxN4n+vhG
F0V7BYcByXrCiiaSrXHw6xWdIHCq1OsY5cgonMe3bfrvgQuxiUAf4EftoxkK8sX3
PGgGHlwtik/rvVDIWZdHjxmEv5HpPS52l+edA/z1WnXns4qg4xsMMdh6ByNl1N1y
rXSM01iGNaV3YsZWgMY2v2GFqHFMsI9HnUG7eczJqqLGpiLn7bf/u0rYzHl3vNtK
dOSBWvqokKgGf6oT6cLF
=X22H
-----END PGP SIGNATURE-----
Merge tag 'renesas-pinmux2-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers
From Simon Horman:
Second Round of Renesas ARM based SoC pinmux and GPIO update for v3.11
tidyup MMC_D1 pin for r8a7778 SoC
fix two pin numbers and add HSCIF pin groups to r8a7790 SoC
add pinmux data for MMCIF and SDHI interfaces for r8a73a4 SoC
* tag 'renesas-pinmux2-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
sh-pfc: r8a7778: tidyup MMC_D1 pin
pinctrl: r8a7790: fix two pin numbers
sh-pfc: r8a7790: add HSCIF pin groups
pinctrl: r8a73a4: add pinmux data for MMCIF and SDHI interfaces
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
__initdata annotations for the r8a7790 SoC by Morimoto-san.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRvrESAAoJENfPZGlqN0++Kl4P/j1twlyTQ7WA99/qba3Ql36u
hGUbqmpoq5MtqdIrkJh4L48Y5M2+MJmmQaH9CkxyxlsmIFDvAb5Ta55iQ6BJgap3
I6yLxRbhQ2ZhydaY/VrtSQLtPg1wAmAYdfTP/1FT+XuR5JddBk95j9I91LnzkTuP
pUr6k3Ahz9Uz6//cYIdyBvM5y1CWSMtwhSTjL7Fb8UXWls/PzRrvmP1lWH5h0v8L
PZAmVWIE5AaeChd8Z88rtlcf61TouxDnghe72yFlE4A9RD3JFjoduBo7/izn3EAA
BYEAyqJYvrW9mxrMuyJlpE8+Gy2CGB0asKYu63n9FYC6T+RKVhNtGNHJ35ys3xMa
hmAOkpa2oFTJI57APtmR+/SzCGTXElqRNw5LJP95GZkpa5PsugtRXVpczgdTOvnv
4VswyH6EzdzcW5KQYE3v/Zp3/58ZzbLzj+nRkjLG1shi739+CQuJngQin+GGdBWL
hUEIgoNuZl1GN/OjMQzpt5b+rWfIyy8jnRTcluvaNIulaFhqc/sYvolurqQGWa0n
U/mSIZT/PxQftguAgUfzhV1vgvJ80Kkb37c9UKwglJjX7E0oNCkZZ8JD9sce7EXn
IvOZL8k8IPDrl8URtNV3IialW3FpGCwM7S/DZ8qM4JHgBYEbJGZ2QGboUMgvnOBo
cEveedi1Qur0x4ZKYrS7
=i7Kv
-----END PGP SIGNATURE-----
Merge tag 'renesas-cleanup-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/late
From Simon Horman:
Renesas ARM based SoC cleanups for v3.11
__initdata annotations for the r8a7790 SoC by Morimoto-san.
* tag 'renesas-cleanup-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (158 commits)
ARM: shmobile: r8a7790: add __initdata on resource and device data
Based on 'renesas-pinmux-for-v3.11' and 'renesas-soc-for-v3.11
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- use correct header for chained_irq functions for s3c24xx-pinctrl
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJRwK9wAAoJEA0Cl+kVi2xq158P/19lNxhcLQqJ36RPyfyOimVR
ejLvUZjPhYqWHO7pHkSSrvMdmoJ/NEDBmbwrrFTi4SjBEPlL0W8aU/lQspgx+zio
FgA5z6jhRG4Jsle4Fisv5aRUU5qCl7nNlXt/021/SsuIWCvo6tgYvXEjvE1343PA
Im9v/biHN2PpeJpqM4SJiHe6wjn60lRXiBMPtgkSUtN/IixMao80uE8jH5YW7t4q
P1Jb7YHDZfSEwlkg5Gvq92+rhIR/fFpsF88Qxf2ufwY7yl2Qx9Kuy0Vpij/4Fblw
Ai1oRQQHvkBu1UBr6AHvUUuRLmGWWTspPjQA8DOwG0PbOvl8Ax2692w942+tA+zP
8a5rhUjqJ54aUxNM3SsqXVRZ2qg4qSHGY1KDkCfoiSI1GiS8nRO5ZGg1fWq8Lh0y
eA3Fg+CX2gNWuo4pRcBncdGKwg/28XX3ZkAapG2zkAHWoTt6SZmHZjYwyPHHphAS
kKSuSGOTxtL1n57QNSSpuUu5NCFDP7KItGv/NkLm4FD1vRN2TDafgwaPgEpIQP2p
3eh4JbuMqJ6Wdv7duTbt/yIlOSALPx5uyvF+KiT/o4Ju/IcUoVPmynLof2dVAvlr
O7vEU6kf9BEh7gu+ON3Dq0MhAEErrJ0EoqSPwB7GzzBDnszuObzpNLHnE5hZWDmU
eK8gVXpUeRcUVsA5qg1L
=LnWR
-----END PGP SIGNATURE-----
Merge tag 's3c24xx-pinctrl-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers
From Kukjin Kim:
based on s3c24xx-pinctrl
- use correct header for chained_irq functions for s3c24xx-pinctrl
* tag 's3c24xx-pinctrl-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
pinctrl: s3c24xx: use correct header for chained_irq functions
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- enable XHCI on exynos5
- enable Pinctrl on exynos4 and exynos5
- calling scu_enable() is only available on Cortex-A9
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJRwKr0AAoJEA0Cl+kVi2xqd58P/A4WmBGgE+OuWni1VJh87Dj9
FOHEt0ZadtnE7YQ/eaTFalWEUecxyKGAy4TlgViDFy1Wkm6YlVVv8tpauSQBBt2g
dcIW8oO3Bo/yh7t6x1sWkdrzD/CXGTuHJedztg18ViuycmLFqkySj/q7jfLONdw+
SPYggkXofbeBmzFLde2eMPK1o0xd8EpkMaoJcqTe5hLhCw3kIYlkqrQlm5gILgHH
vnJwV0vuAUrUwWttMZ0K3Q2YQ00axXrbaMSEosO+c8BbpDgFhRvRK7LVlBQLJUnI
VjYCXwFQsu1hUU+iWFYlL1Y1ZHcLNWqXCiV1rySFpAHyNCkm4/Hkeny2NB3/Lzs9
YL74jGn2ZBX2Pd5ybE02gn0dsRZg7Pwvjh3ECF7y45K7eYx1QAUpzqrEkY6LMM2u
XWV+ZwX7RI6bhjwUGxXY9bijFmDv3JnoQV1ZzZ0QaAGeE+vmcs8YpeMY31sA7VJR
o/KHEPmBUfMJpUssqD54bEYRjcVWFoRb8dsZRPI2yNgVC95ewprba3S2DEMYFIdT
nahndfdvL+GXENa9+BS/q08Oh4PlP21OGBM5Nv1lgbc0SLsyAfQG5rMogsrj5KNU
izc4PLIf0mUvCudkaDxRdGywpjK3FGFZB4C114Zn3eJOPBF+m6n5T/BRjXn6dfPa
mITERPhogy60HFTzlkVl
=oexl
-----END PGP SIGNATURE-----
Merge tag 'exynos-arch-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc
From Kukjin Kim:
arch/arm/mach-exynos update
- enable XHCI on exynos5
- enable Pinctrl on exynos4 and exynos5
- calling scu_enable() is only available on Cortex-A9
* tag 'exynos-arch-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: call scu_enable() only in case of cortex-A9 processor
ARM: EXYNOS: Select PINCTRL_EXYNOS for exynos4/5 at chip level
ARM: EXYNOS: Enable XHCI support on exynos5
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Lee Jones' pinctrl compat ontology patches
- A real clock driver for the Nomadik, 100% DT-based
- Device tree changes for the Nomadik clocks
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.13 (GNU/Linux)
iQIcBAABAgAGBQJRwrp4AAoJEEEQszewGV1zLVkP/1c/zyS4gOjMZLf2aqhT/KAR
K5NRuNQgWnzLtZiEV/sEfiG1aXdJIRUiRwYYOBm//DiTduEURh60H4xIU+BgwaA8
FjwZw52y9iFp92uASz0IGyBoWc3x8poEPVgM9qStSMKLPdpU0IvsYxRi9reFUtM3
XQrs8geZ2Twjzwu81655D/aIbps1dhN6JvUtclhHKdcqcISndOk8LGqTPLhqo7R1
nBmKMmM04uQz/sov/iKiOG9LeUPgJwBzgdDtP/qgmGMDbZqMF9Hy6ErNYL4X2iNa
wzJNl17n0Ml2Z1qoB+WCrpF7sNRKj66ee0T6K0L4MpIHM4NsXuRg0hV7Hzkzd5aY
FBSNu02m9k7Cz8RHlqd1ova1deqCsER04gIF/06kyqWq2g+l8ACeAVxUOHHD/cnr
JX4nNfmDowzKCneJVa+CWmh9DWIzAocCFTEBRb4DkHHZypWzR7OKXAI/L1mzDtV+
n2uKu9lQt/0dzVv87fxh4cBWswsl28ADJdc9l7S4PILkYTYBL7oz/UXL6A/xBZY1
NBsIHp23/QJiGVXkbKeMAjt7kTVQIPtti/NxWAjGrJcEc5BTT8031SLnOrdTLmtD
IixP6r0ZaTHKpYkgEygZHOYrcOh4TbbQ57Cb0cuzl/Ph/u7RgtaYfpbRumhHTbUM
rHEvMBVGgN7dzOoJ+/oS
=0yyI
-----END PGP SIGNATURE-----
Merge tag 'nomadik-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into next/dt
From Linus Walleij:
Nomadik DT and clock work:
- Lee Jones' pinctrl compat ontology patches
- A real clock driver for the Nomadik, 100% DT-based
- Device tree changes for the Nomadik clocks
* tag 'nomadik-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik:
ARM: nomadik: add the new clocks to the device tree
clk: nomadik: implement the Nomadik clocks properly
pinctrl/nomadik: Standardise Pinctrl compat string for Nomadik based platforms
ARM: nomadik: Standardise Nomadik STN8815 based Pinctrl compat string in the DTS
Conflicts:
arch/arm/boot/dts/ste-nomadik-s8815.dts
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Add devicetree support to timer, pinctrl (probe), I2C block,
watchdog, DMA controller and clocks.
- Piecewise add a device tree containing all peripherals.
- Delete the ATAG boot path.
- Delete redundant platform data and board files.
- Convert to multiplatform.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.10 (GNU/Linux)
iQIcBAABAgAGBQJRvvkdAAoJEEEQszewGV1zqjQQAMFYxb4B0c2YweNzDzWjuWM/
STZNyAV62LcE7GvssFYpeJ/+lrB7tNwgplJQ13uluEdFws2Xd63G+qIVznkBE7rW
+ZLHG+MPi/uia2yYcg9Vz1M42Aj5COuu1q6ex9OfR2v/tX3G2G/rjIzAaiiEvWWd
ljcBGlDh41iphY6dsBtFFXR0b9rzzyhhmY5wS1P+bMyl9YlqYp0x0oznLo5eFTlA
9ad9H0oeYYXCcB0V5UI1wsRGCaJqa04xotb6uqn1TUPpVc9ZpYQUkVI/1Fb3gVez
3MrLW2/9tDfXWUOTZTo9VtC4rpbmGSsvBc3C0IUGEj9ovmWTCA/OU/WXsEOAymb9
+F36wMX07z8OmmebBn06s6/Zhy0ht9BoV+NeW4lz3s3uiuE3vxnaxW/kb845xfUI
7o87kV8DpXuEokNP+jYyCDJTw/feq5Dy0HXr4KFOAwXMd3imRREnHgvihCsFtNj4
vRkz+6A17YrtpuvCqnuXiM5Ts+Dz4MAEJ/Iokrm1e28fUw/wuklAXeII8+kxc36R
w6AHTbXpWPjglVAn3DTuh4BjIoN53/cLhttezg7NcgtgRW3AxyHGx3T+345mHsgT
dbust8Qow/bapby8NPHKJDHM5A9RGNWX4rJ+abTxI0iJ0fpcEWT1c5TKlpUR+0KZ
qMTNGvDfonu1xaoPLo81
=fstd
-----END PGP SIGNATURE-----
Merge tag 'u300-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/soc
From Linus Walleij:
Device Tree and Multiplatform support for U300:
- Add devicetree support to timer, pinctrl (probe), I2C block,
watchdog, DMA controller and clocks.
- Piecewise add a device tree containing all peripherals.
- Delete the ATAG boot path.
- Delete redundant platform data and board files.
- Convert to multiplatform.
* tag 'u300-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson: (40 commits)
ARM: u300: switch to using syscon regmap for board
ARM: u300: Update MMC configs for u300 defconfig
spi: pl022: use DMA by default when probing from DT
pinctrl: get rid of all platform data for coh901
ARM: u300: convert MMC/SD clock to device tree
ARM: u300: move the gated system controller clocks to DT
i2c: stu300: do not request a specific clock name
clk: move the U300 fixed and fixed-factor to DT
ARM: u300: remove register definition file
ARM: u300: add syscon node
ARM: u300 use module_spi_driver to register driver
ARM: u300: delete remnant machine headers
ARM: u300: convert to multiplatform
ARM: u300: localize <mach/u300-regs.h>
ARM: u300: delete <mach/irqs.h>
ARM: u300: delete <mach/hardware.h>
ARM: u300: push down syscon registers
ARM: u300: remove deps from debug macro
ARM: u300: move debugmacro to debug includes
ARM: u300: delete all static board data
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add Samsung EXYNOS5420 SoC specific data to enable pinctrl
support for all platforms based on EXYNOS5420.
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Tested-by : Sunil Joshi <joshi@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Previously if you had MACH_EXYNOS5_DT but not MACH_EXYNOS4_DT you'd be
missing the pincontrol definitions. Move PINCTRL selects to the arch
level since we should be enabling the code for all exynos variants.
Update the PINCTRL descriptions to indicate that PINCTRL_EXYNOS is not
for exynos5440. Also add basic dependencies for the PINCTRL_EXYNOS
kernel config.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
chained_irq_enter and chained_irq_exit moved to a real header
under linux/pinctrl instead of asm/.
Update the pinctrl driver to use the correct header and fix the
build error.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Linus Walleij <linus.walleij@linaro.org>`
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add support for gpio on Intel BayTrail platforms. BayTrail supports 3 banks
of gpios called SCORE, NCORE ans SUS with 102, 28 and 44 gpio pins.
Supports gpio interrupts and ACPI gpio events
Pins may be muxed to alternate function instead of gpio by firmware.
This driver does not touch the pin muxing and expect firmare
to set pin muxing and pullup/down properties properly.
Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Symbols referenced only in this file are made static.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Cc: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
'spear310_o2p' is referenced only in this file.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Some symbols referenced only in this file are made static.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
'bcm2835_gpio_pins' is used only in this file.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Support device instantiation through the device tree. The compatible
property is used to select the SoC pinmux information.
Set the gpio_chip device field to the PFC device to enable automatic
GPIO OF support.
Cc: devicetree-discuss@lists.ozlabs.org
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add the missing unlock before return from function pinctrl_find_gpio_range_from_pin()
in the error handling case.
Introduced by commit 2ff3477efd7086544b9e298fc63afab0645921b4.
(pinctrl: add pin list based GPIO ranges)
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
A level-triggered interrupt should be acked after the interrupt line
becomes inactive and before it is unmasked, or else another interrupt
will be immediately triggered. Acking before or after calling the
handler is not enough.
Signed-off-by: Luigi Semenzato <semenzato@chromium.org>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The three functions pinctrl_pm_select_default_state,
pinctrl_pm_select_sleep_state, and pinctrl_pm_select_idle_state
are used in drivers that can be loadable modules, and should
be exported.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Change the rockchip pinctrl driver to handle the arguments to the pull
pinconfig options correctly. So only accept non-0 values for the
pull options as the rockchip pin-controller can only turn pulls on and
off (this via BIAS_DISABLE).
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Make pinctrl-single able to handle suspend/resume events and change
hogged pins states accordingly.
Signed-off-by: Hebbar Gururaja <gururaja.hebbar@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
It will allow us to have a cleaner separation between the data needed by
the driver to work, and the core logic of the driver in itself, and will
allow having too much noise in the core driver in the future.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Allocating the temorary array in pinconf_generic_parse_dt_config on stack
might cause problems later on, when the number of options grows over time.
Therefore also allocate this array dynamically to be on the safe side.
Suggested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds a shortcut when no valid pinconf properties are found
in the parsed dt node, to set the values immediately and return.
Suggested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The bias-pull-* options use values > 0 to indicate that the pull should
be activated and optionally also indicate the strength of the pull.
Therefore use an default value of 1 for these options.
Split the low-power-mode option into low-power-enable and -disable.
Update the documentation to describe the param arguments better.
Reported-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Traditionally, GPIO ranges are based on consecutive ranges of both GPIO
and pin numbers. This patch allows for GPIO ranges with arbitrary lists
of pin numbers.
Signed-off-by: Christian Ruppert <christian.ruppert@abilis.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This deletes the dependency on any platform data for
the COH901 pin controller. There is only one user in the
kernel, and if we at some point want to support more
variants, they shall provide their variant info through
the device tree.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch does nothing but reorder the functions to improve the
readability of a future patch.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The patch:
1984695 pinctrl: samsung: Protect bank registers with a spinlock
...added spinlocks to protect many accesses. However, the irq_mask
and irq_unmask functions still do an unprotected read/modify/write.
Add the spinlock there.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl-abx500.c: In function 'abx500_gpio_dbg_show_one':
pinctrl-abx500.c:534:14: warning: 'pud' may be used
uninitialized in this function [-Wuninitialized]
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This driver adds support the Cortex-A9 based SoCs from Rockchip,
so at least the RK2928, RK3066 (a and b) and RK3188.
Earlier Rockchip SoCs seem to use similar mechanics for gpio
handling so should be supportable with relative small changes.
Pull handling on the rk3188 is currently a stub, due to it being
a bit different to the earlier SoCs.
Pinmuxing as well as gpio (and interrupt-) handling tested on
a rk3066a based machine.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinconf_generic_parse_dt_config() takes a node as input and generates an
array of generic pinconfig values from the properties of this node.
As I couldn't find a mechanism to count the number of properties of a node
the function uses internally an array to accept one of parameter and copies
the real present options to a smaller variable at its end.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The A10 and A13 has a few pins that can be muxed into a particular
function that can be used as an interrupt source. Add the available
pins for such functions to the A10 and A13 description array.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The port controller IP found in the Allwinner A10 and A13 can use few of
the pins it manage as an interrupt source, called external interrupts in
the datasheet.
The number of these external interrupts are SoCs specific, but the
current upper limit is 32. In order to work, the external interrupts'
pins have to be muxed to a specific function to generate an interrupt.
This patch adds the irqchip and the needed logic to use the PIO
controller as an interrupt controller.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Avoid to use expensive string manipulation functions and search by pin
id when possible.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch fixes issues reported by prevent tool.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
[Drop hunk already in-tree from a patch by Wei Yongjun]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Take care to name pin names as
register-offset.bit-pos-of-pin-in-register in case configuring multiple
pins in register.
Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add support to configure multiple pins in each register, existing
implementation added by [1] does not support full fledge multiple pin
configuration in single register, reports a pin clash when different
modules configure different bits of same register. The issue reported
and discussed here
http://www.spinics.net/lists/arm-kernel/msg235213.html
With pinctrl-single,bits-per-mux property specified, use function-mask
property to find out number pins to configure. Allocate and register
pin control functions based sub mask.
Tested on da850/omap-l138 EVM.
does not support variable submask for pins.
does not support pinconf.
[1] "pinctrl: pinctrl-single: Add pinctrl-single,bits type of mux"
(9e605cb68a),
Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com>
Reported-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Tested-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
If a device have sleep and idle states in addition to the
default state, look up these in the core and stash them in
the pinctrl state container.
Add accessor functions for pinctrl consumers to put the pins
into "default", "sleep" and "idle" states passing nothing but
the struct device * affected.
Solution suggested by Kevin Hilman, Mark Brown and Dmitry
Torokhov in response to a patch series from Hebbar
Gururaja.
Cc: Hebbar Gururaja <gururaja.hebbar@ti.com>
Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Wolfram Sang <wsa@the-dreams.de>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Reviewed-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
There exist controllers that don't support to set the pull to up or down
separately but instead automatically set the pull direction based on
embedded knowledge inside the controller, for example depending on the
selected mux function of the pin.
Therefore this patch adds another config option to use this default
pull-state for a pin where it is not possible to know or decide if the
pin will be pulled up or down.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
On some platforms such as VF610, offset of mux and pad ctrl register
may be zero, and the mux_mode and config_val are in one 32-bit register.
This patch adds support to imx core pinctrl framework to handle these
cases.
Signed-off-by: Jingchang Lu <b35083@freescale.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- rework abx500_gpio_dbg_show_one() to take in account pull up/down
feature available on AB8540 only.
- add abx500_get_pull_updown() needed by abx500_gpio_dbg_show_one()
- rename abx500_config_pull_updown() to abx500_set_pull_updown()
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
On ABx500 chip family, all pins support only pull down except for
AB8540 which supports pull up/down on some pins.
Rework abx500_pin_config_set to be able to set pull up on
pins which support this feature.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fix abx500_config_pull_updown() to set correct bit in
AB8540_GPIO_PULL_UPDOWN_REG.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add a new PIN_CONFIG_BIAS_BUS_HOLD pin configuration for a bus holder
pin mode (also known as bus keeper, or repeater). This is a weak latch
which drives the last value on a tristate bus. Another device on the bus
can drive the bus high or low before going tristate to change the value
driven by the pin.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add the drive strength pinconf to debugfs output (with the unit "mA").
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Suppress a mutex which was initialized on probe
and destroyed on remove but never used.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
this patch saves the status of pinctrl registers and restore them while
resuming. this makes all drivers have coherent status for pinmux after
suspending and resuming.
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The pinctrldev_list_mutex is sinked into the functions that
actually traverse the list and lock it there. The code makes
much more sense in this way. All the callers are in
non-performance critical paths and the code is way more
readable this way.
Also refactor the function get_pinctrl_dev_from_devname() to
follow the design pattern of get_pinctrl_dev_from_of_node()
which is slightly simpler.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
atlas6 is a SoC very similar with primaII, the register layput of
pinctrl is same, but the pads, groups and functions of atlas6 have
different layout with prima2, this patch
1. pull the definition of pads, groups and functions out of the
pinctrl-sirf driver,and put them into soc-specific files
2. add pads, groups and functions tables for atlas6
3. let pads, groups and functions tables become the config data of
the related dt compatible node, so the pinctrl-sirf can support
all SiRF SoCs with the config data as private data.
In this patch,we create a sirf dir, and let
the old drivers/pinctrl/pinctrl-sirf.c =
drivers/pinctrl/sirf/pinctrl-prima2.c +
drivers/pinctrl/sirf/pinctrl-sirf.c
drivers/pinctrl/sirf/pinctrl-atlas6.c is a newly created file for the
pin layout of atlas6.
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Replace a call to deprecated devm_request_and_ioremap by devm_ioremap_resource.
Found with coccicheck and this semantic patch:
scripts/coccinelle/api/devm_ioremap_resource.cocci
Signed-off-by: Laurent Navet <laurent.navet@gmail.com>
Acked-by: Tony Prisk <linux@prisktech.co.nz>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Dove power management unit can mux some special functions to mpp0-15.
This patch adds support to set/get the current PMU function mapped
to the corresponding mpp pins. The device tree documentation is also
updated accordingly.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
devm_ioremap_resource does sanity checks on the given resource. No need to
duplicate this in the driver.
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The pinctrl-imx6sl is in place. Enable the build of it.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
devm_ioremap_resource does sanity checks on the given resource. No need to
duplicate this in the driver.
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The driver core clears the driver data to NULL after device_release
or on probe failure, since commit 0998d06310
(device-core: Ensure drvdata = NULL when no driver is bound).
Thus, it is not needed to manually clear the device driver data to NULL.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The driver core clears the driver data to NULL after device_release
or on probe failure, since commit 0998d06310
(device-core: Ensure drvdata = NULL when no driver is bound).
Thus, it is not needed to manually clear the device driver data to NULL.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The driver core clears the driver data to NULL after device_release
or on probe failure, since commit 0998d06310
(device-core: Ensure drvdata = NULL when no driver is bound).
Thus, it is not needed to manually clear the device driver data to NULL.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The driver core clears the driver data to NULL after device_release
or on probe failure, since commit 0998d06310
(device-core: Ensure drvdata = NULL when no driver is bound).
Thus, it is not needed to manually clear the device driver data to NULL.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
DT support to GPIO R-Car driver by Laurent Pinchart.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRuWcSAAoJENfPZGlqN0++zVAP/i+sSeyv8MYVov8AVhZcPmIf
B+u+EPMn//e7ILsRquMw8TIf4NnJDDbafs6oCSSL6/0+dAHQX/6BbnlyX2O/7YFa
vd24gn/NzPNVz6+N8q5EqUT1OKIQMdusU0oK/w2Bg2D/U1OsfjCalcbISjoIJqfw
jqCRliC7n8Qt1OhMCVvUY8wmxcZYbwTsh3zRpVac7RjaWEt3+Qf8Ms1fUbV8A2ZG
ZI+JahxbjuAsQe7Ygp/yZYhdVN7PRatszESEXbx0236hLYUSMqT9TPYUIBOlCmaN
nP3qwpnEJJPsnFd3knnyle5rBrDUMwqBxUNEkBCRcDfvmM3FMgTnnqWGq5yBFj6W
Y4ZxADLcuntpFbiHDIy0a0yFAzNnvFJoYniDx5mvTOcmC1kK/dDHA3fNcni60fiK
KCuvCdwsB+1ZNqsQYMVWingj2DGm0KBZHpy9doPXRCS6H9aclk6DfCFAFpIs+9It
NMt8Bqz5nqAWYFFm/TF0UomFAvLCRaRnzeSGWEcdffkHC9/3qatdrbnLhvafI1fo
SMpAqDGwr1oC15lvbts1jzSs92uSYdh8NXvdsbsjCk3dOdLiOvdlcfo14bsgXCBa
Ia3Uq5sCDXMT9kVV/ILTjellJecMAhwCDv1bZF93aOCfNZo6Rb1frYHXf8+7+s7A
+lGNHdFtclCtAB6Nf+Xq
=NgKm
-----END PGP SIGNATURE-----
Merge tag 'renesas-gpio-rcar-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers
From Simon Horman:
Renesas ARM based SoC GPIO R-Car updates for v3.11
DT support to GPIO R-Car driver by Laurent Pinchart.
* tag 'renesas-gpio-rcar-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (131 commits)
gpio-rcar: Add DT support
- Fix for the thermal node to be contained in the PRCMU node
- Add the DTS and auxdata needed to boot the U8540 platform
- Various regulators added and renamed
- Rename base SoC node
- A bunch of DMA patches adding channels for DT boots
- A bunch of crypto+hash patches adding config for DT boots
- A bunch of patches fixing the ALSA SoC support to work
- Register the LP5521 LEDs
- Fix a number of typos and naming errors
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.10 (GNU/Linux)
iQIcBAABAgAGBQJRrcq+AAoJEEEQszewGV1zRiYP/RaP2Cn78mgvJcjh4Rqw1KmP
LVAyMrmNLtaOKUdSsYfvd+UhIQDF0iDcpS5xRc24w8ZFxVl1Ts8lZ67Jg1r1k1ct
0f0X5o7sZ5YtYMFaJtKIGTqjPaKbSzf2lSEvx0YrzRdNyRNux+sU2tdx1TFPyTvd
OnWH0wPVaPwCVcqc404FaLpH3wFRlGvfGuRV7qT5ACBrMfCRKkQfqdpcLsaJ8cVW
op6kljkaRc56zwnm19LrUTo6h+WYS5DL7VpUSsZ4KsMfgy8RqgkGE9JWjBFp62To
p0HrCwO1lA+JULsI7SW6dRLt+/W+hjsr38B/+/LXZKm4oQo8gE328+l+0+x7NT+3
0tpD4Mw0MCh12ARAb/EEKdomzTZThJk0nJZGUW/EhcmMXw9nLZR9TFy11H0FkVdw
lUukvMAhM/gkGRyYqgMOQdoeC3a3au1O50XEZvYVHQVkXcmQhoY3ckrIWW+BgKQQ
u4wmMcB6Q/bDONqAb5RcFICapSlIrm8KbY9fO0801r5aSDVDxHLblcKF+/J1qcd9
gM68DoJ0A07dJaeHjM9LGdekUiEB6xsI3nU5r0QlNSbkQZqBLiu6PJZXJe8vIPIi
Fo8n3gRfpG97pn3EAaO1aw3w2WX10JEWIYetkwrirJaJiYwB2a2PYVwXLX0zgcZp
B//Uy9xFT3R9Mgv7Cu20
=cph0
-----END PGP SIGNATURE-----
Merge tag 'ux500-dt-for-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/dt
From Linus Walleij:
Device tree patches for ux500, basically trees and auxdata:
- Fix for the thermal node to be contained in the PRCMU node
- Add the DTS and auxdata needed to boot the U8540 platform
- Various regulators added and renamed
- Rename base SoC node
- A bunch of DMA patches adding channels for DT boots
- A bunch of crypto+hash patches adding config for DT boots
- A bunch of patches fixing the ALSA SoC support to work
- Register the LP5521 LEDs
- Fix a number of typos and naming errors
* tag 'ux500-dt-for-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson: (39 commits)
ARM: ux500: drop any 0x prefix from I2C DT devices
ARM: ux500: Allocate correct amount of memory for the u8540 in DT
ARM: ux500: Provide auxdata to ux500 ASoC driver
ARM: ux500: Add DT regulators for ab8500-codec
ARM: ux500: Correct anamic2 typo in DT files
ARM: ux500: Fix trivial typo in v-anamic1 comment
ARM: ux500: Reduce PRCMU reg-names to shorter form for u8540 DT
ARM: ux500: Add an auxdata entry for MUSB for clock-name look-up
ARM: ux500: cut chip-select GPIOs from SSP device
ARM: ux500: use symbolic names for interrupt flags
ARM: ux500: use #include syntax to include *.dtsi.
ARM: ux500: bump MMC/SD max frequency for DT boots
ARM: ux500: Apply other compatible name to the u8540 DTS file
pinctrl/nomadik: Standardise Pinctrl compat string for DBx5x based platforms
ARM: ux500: Standardise Pinctrl compatible string for DBx5x based platforms
ARM: ux500: Standardise DBx5x0 based Pinctrl compat string in the DTS
crypto: ux500/hash - Enable DT probing of the driver
crypto: ux500/cryp - Enable DT probing of the driver
ARM: ux500: enable the crypto and hash on all dbx500
ARM: ux500: Provide an AUXDATA entry for ux500-hash
...
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch adds pinmux groups and functions for the two MMCIF and three
SDHI interfaces on r8a73a4 (APE6).
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
From Alexander Shiyan, this is a series of cleanups of clps711x, movig it
closer to multiplatform and cleans up a bunch of old code.
* clps711x/soc:
ARM: clps711x: Update defconfig
ARM: clps711x: Add support for SYSCON driver
ARM: clps711x: edb7211: Control LCD backlight via PWM
ARM: clps711x: edb7211: Add support for I2C
ARM: clps711x: Optimize interrupt handling
ARM: clps711x: Add clocksource framework
ARM: clps711x: Replace "arch_initcall" in common code with ".init_early"
ARM: clps711x: Move specific definitions from hardware.h to boards files
ARM: clps711x: p720t: Define PLD registers as GPIOs
ARM: clps711x: autcpu12: Move remaining specific definitions to board file
ARM: clps711x: autcpu12: Special driver for handling memory is removed
ARM: clps711x: autcpu12: Add support for NOR flash
ARM: clps711x: autcpu12: Move LCD DPOT definitions to board file
ARM: clps711x: Set PLL clock to zero if we work from 13 mHz source
ARM: clps711x: Remove NEED_MACH_MEMORY_H dependency
ARM: clps711x: Re-add GPIO support
GPIO: clps711x: Add DT support
GPIO: clps711x: Rewrite driver for using generic GPIO code
+ Linux 3.10-rc4
Signed-off-by: Olof Johansson <olof@lixom.net>
* Correction to USB OVC and PENC pin groupings on r8a7779 SoC.
This avoids conflicts when the USB_OVCn pins are used by another function.
This has been observed to be a problem in v3.10-rc1.
* Update CMT clock rating for sh73a0 SoC to resolve boot failure
on kzm9g-reference. This resolves a regression between v3.9 and v3.10-rc1.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRrZpLAAoJENfPZGlqN0++t0UQAIBErmUK+bGdZ21NmWmjIMb3
mOegzj53Fvl3nWixPqYEGOSBEMtAltL4BnuEIJ5cC4jIijHYn9YtAfGQYSmgyV4+
KxloM8ZpJ6deGsKC5NyPnq9Hf+8Qec44LxQRuZxh58gchZFoUn2DAZBCBeLYlSs1
t2BHBD4aMaI6VYfMpBOaSPNn7oCds2kzqQ7pkiLkLdUWw1pnfxkWzBB+4+JYCOx1
BqfwgoxuhHSf7J9W2sb4EakDh19ZjBPfcjdS/DJOSk3Q6WyhkyaC6VkdYiVXekWg
tcedXxB4QavDkDiAje1/z9gBJHnE58ZKB+Q3MakHgwunhr5wMBzS1Hk62ybcPW+W
fUzhzmJd/BLxfzAJbguNoGistWmY6qcf8F2Zvx6VyI+X+BK4OulZvJzle4t5mDu6
GdYXRYP/dX9IuMrA5i5uemYF3/7Qj+CXkyO+6r6baGSBub9rE+dDI15Zjzm7en8n
DpSji9h2gvmN3jJ5fq22MikRegk+UyMGahr3P7DqgJdv6SPNGVe5cEJRLrijYojM
qC9MCyh4Jnai0NRnFoIf4+DhF3/fqbmgcBCOINDpkisf1u7Qxrm10c7kFHngu20w
ub9xhHq3hYgzcwn4rk/c/H5deWdOj5LoKM+ddy4isihbCOKtcPrOVHTWSnGuL+th
hnXe/GxU9Tyq0yF+JgT7
=oukw
-----END PGP SIGNATURE-----
Merge tag 'renesas-fixes-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into fixes
From Simon Horman, Renesas ARM based SoC fixes for v3.10:
- Correction to USB OVC and PENC pin groupings on r8a7779 SoC.
This avoids conflicts when the USB_OVCn pins are used by another function.
This has been observed to be a problem in v3.10-rc1.
- Update CMT clock rating for sh73a0 SoC to resolve boot failure
on kzm9g-reference. This resolves a regression between v3.9 and v3.10-rc1.
* tag 'renesas-fixes-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: sh73a0: Update CMT clockevent rating to 80
sh-pfc: r8a7779: Don't group USB OVC and PENC pins
Signed-off-by: Olof Johansson <olof@lixom.net>
The list of functions selected by the MOD_SEL2 register was missing
an entry. This caused all entries after this to modify the MOD_SEL2
register incorrectly.
This bug showed up when selecting i2c2_c pins on the Renesas Hurricane board.
This bug has been present since pinmux support was added for the
r8a7779 SoC by 881023d28b ("sh-pfc: Add
r8a7779 pinmux support") in v3.8-rc4.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds pinmux groups and functions for the two MMCIF and four
SDHI interfaces on r8a73a4 (APE6).
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Fix several errors in Peripheral Function Select register tables for
r8a7790, which prevent various function pins from being correctly
configured.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
IP2[31] func2 is IRQ1A, not IRQ3A
Reported-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add VIN DATA[0:8]/CLK/HSYNC/VSYNC pin groups to R8A7778 PFC driver.
While at it, add SH_PFC_MUX8() macro for 8-bit data busses.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
[Sergei: updated the copyrights, added SH_PFC_MUX8() macro for 8-bit data bus,
made use of SH_PFC_*() macros to define the pin groups.]
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
No sh73a0 platform use the function GPIOs API. Remove it.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The sh73a0 has an internal power gate on the VCCQ power supply for the
SDHI0 device that is controlled (for some strange reason) by a bit in a
PFC register. This feature should be exposed as a regulator.
As the same register is also used for pin control purposes there is no
way to achieve atomic read/write sequences with a separate regulator
driver. We thus need to implement the regulator here.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add two optional init and exit SoC operations and call them from the
core at probe and remove time.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Function GPIOs have been removed, remove comments that refer to them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The PFC GPIO API implementation moved to using port numbers. Replace all
GPIO_PORTx enum usage with the corresponding port number. The GPIO_PORTx
enum values are identical to the port number on this platform.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
No r8a7740 platform use the function GPIOs API. Remove it.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
All r8a7740 platforms now use the pinctrl API to control the HDMI pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
All r8a7740 platforms now use the pinctrl API to control the FSI pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
All r8a7740 platforms now use the pinctrl API to control the CEU pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
All r8a7740 platforms now use the pinctrl API to control the GETHER
pins, the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
All r8a7740 platforms now use the pinctrl API to control the BSC pins,
the corresponding function GPIOS are unused. Remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Laurent Pinchart