quite a while ago but have somehow fallen though the cracks
as most of the focus has been making things to work with
device tree. As the first patch depends on sparse IRQ
related removal of irqs.h and related header moves, these
are based on omap-cleanup-local-headers-for-v3.7 tag.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJQYP5uAAoJEBvUPslcq6VziaUQAOH+n32u1XCcRtwri1s5Md9/
mUrAzE2Q4PD8B9wFJf8lGQMljxJH1dzhauZOPghnbfZgMWmcnk/b1AxRMB84vskx
aPMirS8Aamb7wvzKv0CySAa+nGOeBm3k/6SqUmWNlpDoe1U5Sus5RgIxscfmTfKG
hunrn4Bp6dw2gLkLOqE6OAqX4oJaufSfQcWZH5M3m95TXzSrMDYqlzzcErY94wj5
DMvlBPg3AAozE0VQTTdOz6MONO35BMzBs9S5v10K5qgc7e7m/AnZljxakR6D6Cqp
k4wvURdC3yMJK5MpLCnQ8TOVb9g4PVFdPb1+CZX9qMfdBNsPnYVOX7cw755XNxFV
xe3Ki2HNVn5UMaD5UGzfqZFSxCtvWU8G8xGLZ8zmxEwUPkUdbGh3MHyYMI+NUCwy
rgS85JfJfLsZnw00m7/BY+i63/uMQhEZ8PrxLyGVbbzZGML6zjqssAJo3j0RpPDX
lbp8bDIh6+UeUikSYd1/jMYh9ZtnJMagf+NyRzYHsGcuDoGOi9grO1IY3VMnV8gz
ZEhrq7xwNxEEBgejUgIECapAoTMD5AnfsO5VFz8TaVlHF+gsa9Unb1De7oj7IW6y
+ClpUHAiDR9eWLoPcts6ZYBU3f6EJRMZWzFoRb2vpoqbD3pw0oPDGvvHKOeZD4FE
C21FhFyNsMyRZhuF1lz9
=0J8j
-----END PGP SIGNATURE-----
Merge tag 'omap-devel-board-late-v3-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/cleanup
From Tony Lindgren:
These board and platform related patches have been posted
quite a while ago but have somehow fallen though the cracks
as most of the focus has been making things to work with
device tree. As the first patch depends on sparse IRQ
related removal of irqs.h and related header moves, these
are based on omap-cleanup-local-headers-for-v3.7 tag.
* tag 'omap-devel-board-late-v3-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: serial: Change MAX_HSUART_PORTS to 6
ARM: OMAP4: twl-common: Support for additional devices on i2c1 bus
using device tree.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJQYKzmAAoJEBvUPslcq6Vz3I4P/iF17vddn2Ytnu8mCihW7nP7
mCAXijfFqpAHTTRjXK6VqvRwU1tUClwLCy2Shi+p5ne7tGOzQKVxeoA3eppdelfQ
9rkA6Z8n/OfeAqqmgo0cAABkoa54vX/t9bRAbvW0HAOnCLSb2XEEnh2pArWqCYvw
UcuPekS2Ff3nl5aiEZfvndmUjS+NHlBH759SvBdXpWvvIMDdpYKNvOEML4MPklM3
Vc0nPBe7THmVFIUc4Nr3jIUdaDjAAQMRa8Hl+4sbpZzkdBx8dQQFbI9HTeXM9VqM
gdGYuuenRs/Vzkgl881wJ1MlTaTVsSXXRMBI05l0DOBCZht16YJZ3OZ9zM8u6Ns4
nrOrzpwG9dBNxZ0OlnmJbyWau3FgWU30FVRTEL3OQtscyOOlbFxNB6NP5uuayNNN
2Zey6R863xjO1d+p13rh1HVu2Lj49YjlvQoaz49YWbVHjR0wR1sNN3dXqZgb6r9u
bsqaQMXn6tCBIYSeeA7V4TB39lK0fzMT3w8bbo2Y3ozW0hY9TG8I2hX+/fnc1h5W
hQBAlqnLmBoCwlBqLI11XvDWchiVceUgLeJwk712aD7X8IKbBQ1cUhnTem9UKaKS
gKYkQTL3GUO7vF0Io9aVX3Q+IngX8xb5YOezK1V4pv5vqeDJ6QqCIjinBeOuKCk6
uDgvIAfF2DwZEfNUpV/R
=LDvq
-----END PGP SIGNATURE-----
Merge tag 'devel-dt-arch-timer-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
From Tony Lindgren:
Few late patches to enable arch timer for omap5
using device tree.
* tag 'devel-dt-arch-timer-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP5: Enable arch timer support
ARM: OMAP: Add initialisation for the real-time counter.
CONFIG_MTD_NAND_VERIFY_WRITE was killed recently, so remove it from
defconfigs as well.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Because we can have a single kernel to support multiple machines, we
need to make loading specific drivers for the target platform only.
For this, driver is converted to the platform driver.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Moving ARCH_MVEBU for multi-platform support caused several breakages in
recently added addr-map and pinctrl support for mvebu. This adds the
necessary selects and include paths to fix the build.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The nhk8815 board files uses NAND_NO_READRDY in its platform data, but
this macro is getting removed because it was not being used anywhere.
Without this patch, building nhk8815_defconfig results in:
arch/arm/mach-nomadik/board-nhk8815.c:118:6: error: 'NAND_NO_READRDY' undeclared here (not in a function)
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Alessandro Rubini <rubini@unipv.it>
Cc: Linus Walleij <linus.walleij@linaro.org>
arm: Add ARM ERRATA 775420 workaround
Workaround for the 775420 Cortex-A9 (r2p2, r2p6,r2p8,r2p10,r3p0) erratum.
In case a date cache maintenance operation aborts with MMU exception, it
might cause the processor to deadlock. This workaround puts DSB before
executing ISB if an abort may occur on cache maintenance.
Based on work by Kouei Abe and feedback from Catalin Marinas.
Signed-off-by: Kouei Abe <kouei.abe.cp@rms.renesas.com>
[ horms@verge.net.au: Changed to implementation
suggested by catalin.marinas@arm.com ]
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Simon Horman <horms@verge.net.au>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Some architectures like xscale and feroceon have cache API variants that
map cache flushing functions as aliases to the base architecture.
This patch adds the required aliases to complete the implementation of
cache flushing LoUIS API.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* cleanup/__iomem:
ARM: Orion5x: ts78xx: Add IOMEM for virtual addresses.
ARM: ux500: use __iomem pointers for MMIO
Two new cleanup patches that were not already part of the
first cleanup branch.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Also convert logical or to + for register offsets from base
addresses. This fixes a number of warnings currently seen in
linux-next:
warning: passing argument 2 of '__raw_writeb' makes pointer from
interger without cast.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
In the earlier sweeping changes, the ux500 uncompress.h file was missed
because other problems were hiding this one.
Without this patch, building u8500_defconfig results in:
In file included from arch/arm/boot/compressed/misc.c:33:0:
arch/arm/mach-ux500/include/mach/uncompress.h: In function 'putc':
arch/arm/mach-ux500/include/mach/uncompress.h:32:2: warning: passing argument 1 of '__raw_readb' makes pointer from integer without a cast [enabled by default]
arch/arm/include/asm/io.h:95:89: note: expected 'const volatile void *' but argument is of type 'u32'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
While we fixed up all instances that were already present in v3.6,
this one came in through new code.
Without this patch, building kzm9g_defconfig results in:
arch/arm/mach-shmobile/board-kzm9g.c: In function 'kzm9g_restart':
arch/arm/mach-shmobile/board-kzm9g.c:781:2: warning: passing argument 2 of '__raw_writel' makes pointer from integer without a cast [enabled by default]
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Cc: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Cc: Simon Horman <horms@verge.net.au>
The removal of bcmring has non-obvious commits with the way the
multiplatform configuration works, so merge it in here.
Conflicts:
arch/arm/Kconfig
arch/arm/Makefile
arch/arm/mach-bcmring/arch.c
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
From "Christian Daudt" <csd@broadcom.com>:
Remove mach-bcmring as this is no longer maintained or used.
Updated the removal with:
- drop the edit to mach-types requested by Russell King
- eliminate defconfig mod from patch 1 requested Olof Johansson
Also switched to using git send-email to avoid word-wrapping
problems
* bcmring/removal:
ARM: Remove mach-bcmring
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Doing a large-scale cleaning and removing the platform in another
branch don't mix well, so do the trivial merge here.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Remove mach-bcmring as this is no longer maintained or used.
Signed-off-by: Christian Daudt <csd@broadcom.com>
Reviewed-by: Jiandong Zheng <jdzheng@broadcom.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The current kernel does not fit in the CEIVA ROM. Also, some functional
has already been removed due migrate from 2.6 to 3.0, and it seems that
no one uses this platform. So, remove support for this board and modules
specific only to this board.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
This patch contain some fixes:
- Fixes the address of register PORTE.
- Corrects name for DAIDR0 register.
- Removes unused definition for SYNCIO_CFGLEN.
- Fixes definition SYNCIO_FRMLEN.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
CTS signal can not be used for the port and tied to any logic state.
In this case we have an infinite loop waiting for the signal. For fix
this problem, checking CTS removed, waiting for the signal "busy" was
postponed after the byte write to the port.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Modern CPUs from CLPS711X-line can operate at frequencies other than 73 MHz.
This patch adds simple clock framework for handling all possible CPU rates.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Convert eukrea-tlv320 to platform driver.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This allows /proc/vmallocinfo to show the physical address for
ioremap mappings.
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This defines the proper sleep states for all the I2C pins of
the MOP500 DB8500 ASIC setting.
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Patrice Chotard <patrice.chotard@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Use the mapping of Elf_[SPE]hdr, Elf_Addr, Elf_Sym, Elf_Dyn, Elf_Rel/Rela,
ELF_R_TYPE() and ELF_R_SYM() to either the 32-bit version or the 64-bit version
into asm-generic/module.h for all arches bar MIPS.
Also, use the generic definition mod_arch_specific where possible.
To this end, I've defined three new config bools:
(*) HAVE_MOD_ARCH_SPECIFIC
Arches define this if they don't want to use the empty generic
mod_arch_specific struct.
(*) MODULES_USE_ELF_RELA
Arches define this if their modules can contain RELA records. This causes
the Elf_Rela mapping to be emitted and allows apply_relocate_add() to be
defined by the arch rather than have the core emit an error message.
(*) MODULES_USE_ELF_REL
Arches define this if their modules can contain REL records. This causes
the Elf_Rel mapping to be emitted and allows apply_relocate() to be
defined by the arch rather than have the core emit an error message.
Note that it is possible to allow both REL and RELA records: m68k and mips are
two arches that do this.
With this, some arch asm/module.h files can be deleted entirely and replaced
with a generic-y marker in the arch Kbuild file.
Additionally, I have removed the bits from m32r and score that handle the
unsupported type of relocation record as that's now handled centrally.
Signed-off-by: David Howells <dhowells@redhat.com>
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
Here's a bugfix for orion5x. Without this, PCI doesn't initialize properly
because of too small coherent pool to cover the allocations needed.
A similar fix has already been done on kirkwood.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJQZJLaAAoJEIwa5zzehBx3T/gP/AhnE+wyL8rM/Pvhg1ozfLz/
2o3n89+ThAvURXICnS02Y4DL66qP4uUV354hco8heyBffR+gu4dDCdfut5qiCZ/y
5dyjYMp5dyh441A0qHUzfCWGo+dcwX45lU0HwenIht2GFoqHyTbVtTL7Wr4o8+k5
khlXqa76YTvfEyAODT0E7IHJxaZzc+K/GCAIxSq2RYa5zmr+LYwVVAMvCWt32ohe
9zQ2S0cu8uR7pb6ZRz8YUBUTkBlw9aV22DZNT4ZYryGPzInAbypV4HpnNPB0oAZb
41SZODCmWoTMUVGN5qFSJtTsezTx8Wj10YK7Q1C0qvcHh1Cbwsbt4TLbvF6EiddG
Fmkp42XfECePsGMrwVtCPnJSCtmxUc8M91koq2lNj40PNzkGralHEY9PaGqMx31h
eIbn4brUDp5zBlwwQsCXuE7clBTt/10hoFwkzdr6IRs44kEW7C++qQEdByzEbSGa
EU2RtIcxfu98CwxadTnFkVYEjnXE1/kJsdqa4uCmJG93cLtS0cimrDt9reCoklHF
l5FuwH/DjDS5u37YxXTDiopsFBvWYiJOsw38QsQkjeupeho+Xac3w7ujGgeR3gBW
WG9sFLm74Yy6BMIBzXS/c2ptAQYxLcPjY+l8vLymHQePStf3j1Y2VYW6pYMXbqnB
fLdFti5gAdbhLu5RKKMk
=Og96
-----END PGP SIGNATURE-----
Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull one more arm-soc bugfix from Olof Johansson:
"Here's a bugfix for orion5x. Without this, PCI doesn't initialize
properly because of too small coherent pool to cover the allocations
needed.
A similar fix has already been done on kirkwood."
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: Orion5x: Fix too small coherent pool.
Pull ARM dma-mapping fix from Marek Szyprowski:
"This patch fixes a potential memory leak in the ARM dma-mapping code."
* 'fixes-for-3.6' of git://git.linaro.org/people/mszyprowski/linux-dma-mapping:
ARM: dma-mapping: Fix potential memory leak in atomic_pool_init()
This named the sleep mode pin configurations as *slpm* rather
than *sleep* to correspond better with the settings from the
datasheet. It also defines an optional sleep mode for the SPI
controller SPI2.
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Not all of the controllers support the 64 bit data width. Make it configurable
via platform data. The driver will try to get a value from the component
parameters, otherwise it will use the platform data.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
The maximum block size is a configurable parameter for the chip. So, driver
will try to get it from the encoded component parameters. Otherwise it will
come from the platform data.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
Some Orion5x devices allocate their coherent buffers from atomic
context. Increase size of atomic coherent pool to make sure such the
allocations won't fail during boot.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Olof Johansson <olof@lixom.net>
Ensure that the memory regions that are set within the segments
correspond to physical contiguous memory regions.
Reviewed-by: Simon Horman <horms@verge.net.au>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Matthew Leach <matthew.leach@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch allows a dtb to be passed to a new kernel using the kexec
mechinism.
When loading segments from userspace, scan each segment's first four
bytes for the dtb magic. If this is found set the kexec_boot_atags
parameter to the relocate_kernel code to the phyical address of this
segment.
Reviewed-by: Simon Horman <horms@verge.net.au>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Matthew Leach <matthew.leach@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The current timer-based delay loop relies on the architected timer to
initiate the switch away from the polling-based implementation. This is
unfortunate for platforms without the architected timers but with a
suitable delay source (that is, constant frequency, always powered-up
and ticking as long as the CPUs are online).
This patch introduces a registration mechanism for the delay timer
(which provides an unconditional read_current_timer implementation) and
updates the architected timer code to use the new interface.
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add device nodes for the four instances of dw_mmc controllers in
EXYNOS5250 and enable instance 0 and 2 for the SMDK5250 board.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add entries if MSHC controllers in AUXDATA table for correct
device name initialization.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add clock instances for bic("bus interface unit clock") and ciu("card
interface unit clock") of the all four MSHC controller instances.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Pull more networking fixes from David Miller:
1) Eric Dumazet discovered and fixed what turned out to be a family of
bugs. These functions were using pskb_may_pull() which might need
to reallocate the linear SKB data buffer, but the callers were not
expecting this possibility. The callers have cached pointers to the
packet header areas, and would need to reload them if we were to
continue using pskb_may_pull().
So they could end up reading garbage.
It's easier to just change these RAW4/RAW6/MIP6 routines to use
skb_header_pointer() instead of pskb_may_pull(), which won't modify
the linear SKB data area.
2) Dave Jone's syscall spammer caught a case where a non-TCP socket can
call down into the TCP keepalive code. The case basically involves
creating a raw socket with sk_protocol == IPPROTO_TCP, then calling
setsockopt(sock_fd, SO_KEEPALIVE, ...)
Fixed by Eric Dumazet.
3) Bluetooth devices do not get configured properly while being powered
on, resulting in always using legacy pairing instead of SSP. Fix
from Andrzej Kaczmarek.
4) Bluetooth cancels delayed work erroneously, put stricter checks in
place. From Andrei Emeltchenko.
5) Fix deadlock between cfg80211_mutex and reg_regdb_search_mutex in
cfg80211, from Luis R. Rodriguez.
6) Fix interrupt double release in iwlwifi, from Emmanuel Grumbach.
7) Missing module license in bcm87xx driver, from Peter Huewe.
8) Team driver can lose port changed events when adding devices to a
team, fix from Jiri Pirko.
9) Fix endless loop when trying ot unregister PPPOE device in zombie
state, from Xiaodong Xu.
10) batman-adv layer needs to set MAC address of software device
earlier, otherwise we call tt_local_add with it uninitialized.
11) Fix handling of KSZ8021 PHYs, it's matched currently by KS8051 but
that doesn't program the device properly. From Marek Vasut.
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net:
ipv6: mip6: fix mip6_mh_filter()
ipv6: raw: fix icmpv6_filter()
net: guard tcp_set_keepalive() to tcp sockets
phy/micrel: Add missing header to micrel_phy.h
phy/micrel: Rename KS80xx to KSZ80xx
phy/micrel: Implement support for KSZ8021
batman-adv: Fix symmetry check / route flapping in multi interface setups
batman-adv: Fix change mac address of soft iface.
pppoe: drop PPPOX_ZOMBIEs in pppoe_release
team: send port changed when added
ipv4: raw: fix icmp_filter()
net/phy/bcm87xx: Add MODULE_LICENSE("GPL") to GPL driver
iwlwifi: don't double free the interrupt in failure path
cfg80211: fix possible circular lock on reg_regdb_search()
Bluetooth: Fix not removing power_off delayed work
Bluetooth: Fix freeing uninitialized delayed works
Bluetooth: mgmt: Fix enabling LE while powered off
Bluetooth: mgmt: Fix enabling SSP while powered off
The ARMv7 processor setup function __v7_setup() cleans and invalidates the
CPU cache before enabling MMU to start the CPU with a clean CPU local cache.
But on ARMv7 architectures like Cortex-[A15/A8], this code will end
up flushing the L2 caches(up to level of Coherency) which is undesirable
and expensive. The setup functions are used in the CPU hotplug scenario too
and hence flushing all cache levels should be avoided.
This patch replaces the cache flushing call with the newly introduced
v7 dcache LoUIS API where only cache levels up to LoUIS are cleaned and
invalidated when a processors executes __v7_setup which is the expected
behavior.
For processors like A9 and A5 where the L2 cache is an outer one the
behavior should be unchanged.
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
When a CPU is hotplugged out caches that reside in its power domain
lose their contents and so must be cleaned to the next memory level.
Currently, __cpu_disable calls flush_cache_all() that for new generation
processor like A15/A7 ends up cleaning and invalidating all cache levels
up to Level of Coherency, which includes the unified L2.
This ends up being a waste of cycles since the L2 cache contents are not
lost on power down.
This patch updates __cpu_disable to use the new LoUIS API cache operations.
Acked-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
In processors like A15/A7 L2 cache is unified and integrated within the
processor cache hierarchy, so that it is not considered an outer cache
anymore. For processors like A15/A7 flush_cache_all() ends up cleaning
all cache levels up to Level of Coherency (LoC) that includes
the L2 unified cache.
When a single CPU is suspended (CPU idle) a complete L2 clean is not
required, so generic cpu_suspend code must clean the data cache using the
newly introduced cache LoUIS function.
The context and stack pointer (context pointer) are cleaned to main memory
using cache area functions that operate on MVA and guarantee that the data
is written back to main memory (perform cache cleaning up to the Point of
Coherency - PoC) so that the processor can fetch the context when the MMU
is off in the cpu_resume code path.
outer_cache management remains unchanged.
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
This patch renames jump labels in v7_flush_dcache_all in order to define
a specific flush cache levels entry point.
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
ARM v7 architecture introduced the concept of cache levels and related
control registers. New processors like A7 and A15 embed an L2 unified cache
controller that becomes part of the cache level hierarchy. Some operations in
the kernel like cpu_suspend and __cpu_disable do not require a flush of the
entire cache hierarchy to DRAM but just the cache levels belonging to the
Level of Unification Inner Shareable (LoUIS), which in most of ARM v7 systems
correspond to L1.
The current cache flushing API used in cpu_suspend and __cpu_disable,
flush_cache_all(), ends up flushing the whole cache hierarchy since for
v7 it cleans and invalidates all cache levels up to Level of Coherency
(LoC) which cripples system performance when used in hot paths like hotplug
and cpuidle.
Therefore a new kernel cache maintenance API must be added to cope with
latest ARM system requirements.
This patch adds flush_cache_louis() to the ARM kernel cache maintenance API.
This function cleans and invalidates all data cache levels up to the
Level of Unification Inner Shareable (LoUIS) and invalidates the instruction
cache for processors that support it (> v7).
This patch also creates an alias of the cache LoUIS function to flush_kern_all
for all processor versions prior to v7, so that the current cache flushing
behaviour is unchanged for those processors.
v7 cache maintenance code implements a cache LoUIS function that cleans and
invalidates the D-cache up to LoUIS and invalidates the I-cache, according
to the new API.
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
spi-pl022 got a further update to its devicetree support, completing properties
such that no platform data is necessary anymore. This patch adjusts phy3250.c
accordingly: The supplied platform data is deleted. However, OF_DEV_AUXDATA()
are still necessary due to device naming ("dev:ssp0").
Signed-off-by: Roland Stigge <stigge@antcom.de>
Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
This patch adjusts the PHY3250 board file to the actual LED configuration
(active high, default-state and trigger configuration).
Signed-off-by: Roland Stigge <stigge@antcom.de>
There is no such part as KS8001, KS8041 or KS8051. There are only
KSZ8001, KSZ8041 and KSZ8051. Rename these parts as such to match
the Micrel naming.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: David J. Choi <david.choi@micrel.com>
Cc: David S. Miller <davem@davemloft.net>
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Cc: Linux ARM kernel <linux-arm-kernel@lists.infradead.org>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Extends the maximum number of UART ports to 6 from 4 because AM335X
device have six UART ports.
Signed-off-by: AnilKumar Ch <anilkumar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
On OMAP4 the i2c1 bus is dedicated for the PMIC and audio related devices.
Manufacturers can opt to use different codec than twl6040 and also can add
audio related IC to the bus (external amplifier for example on SDP4430).
Make it possible to add different set of additional devices to i2c1 bus on
OMAP4 boards.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
[tony@atomide.com: updated for removal of irqs.h]
Signed-off-by: Tony Lindgren <tony@atomide.com>
Given that the xenvm machine is based on vexpress but with an extremely
limited selection of peripherals (the guest is supposed to use virtual
devices instead), add "xen,xenvm" to the list of compatible machines in
mach-vexpress.
Changes in v3:
- add comments to mark fields that are likely to be changed by the
hypervisor.
Changes in v2:
- remove include skeleton;
- use #address-cells = <2> and #size-cells = <2>;
- remove the debug bootargs;
- use memory@80000000 instead of memory;
- remove the ranges and interrupt-map from the motherboard node;
- set the machine compatible to "xen,xenvm-4.2", "xen,xenvm";
- rename the dts file to xenvm-4.2.dts;
- add "xen,xenvm" to the list of compatible DT strings to mach-vexpress.
Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Pawel Moll <pawel.moll@arm.com> (v2m changes)
There is a new flags parameter for the function.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Vinod Koul <vinod.koul@linux.intel.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
When either of __alloc_from_contiguous or __alloc_remap_buffer fails
to provide a valid pointer, allocated memory is freed up and an error
is returned. 'pages' was however not freed before returning error.
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
remove existing non-dt code.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQEcBAABAgAGBQJQXBatAAoJEAKiPfwuf9N/VZoIAI7PKNwakjM/KDiVzytwqZ+U
h9kkjYW4ra8MH+jpjFQqvSyIJ3U+t016xqW3ZbqRuZBDgH0I7Gax7QoAZ/ljPlpG
RAKl2l9WVPiBSwCESTpvR5lafBLklk6fL0Z267qIxDGld6YBiWHvTKIh1zDmeCWW
hgDeWtcb1M61VlPrj9nPnCze66h2dUk+QSxaCodv7co5kzb0Q4S7U64BCs0hGe01
kkdoUwnBjdeK0cUhDAJAP1vRyk04N16+H7yp4npmKhv/blKVc3MIRjg1iBV78ncd
Kke/G1B9TJRpNTXdySYnsDQpaCWNSAryKXKkdxP0gh6MW8CMKYc1mdKYcEP3Tk8=
=xG1+
-----END PGP SIGNATURE-----
Merge tag 'vt8500-for-next' of git://git.code.sf.net/p/linuxwmt/code into next/dt
From Tony Prisk:
Update arch-vt8500 and drivers to device tree and
remove existing non-dt code.
* tag 'vt8500-for-next' of git://git.code.sf.net/p/linuxwmt/code:
arm: vt8500: Update arch-vt8500 to devicetree support.
arm: vt8500: gpio: Devicetree support for arch-vt8500
arm: vt8500: doc: Add device tree bindings for arch-vt8500 devices
arm: vt8500: clk: Add Common Clock Framework support
video: vt8500: Add devicetree support for vt8500-fb and wm8505-fb
serial: vt8500: Add devicetree support for vt8500-serial
rtc: vt8500: Add devicetree support for vt8500-rtc
arm: vt8500: Add device tree files for VIA/Wondermedia SoC's
Resolved add/change conflict in drivers/clk/Makefile.
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch moves the sht15.h header from include/linux to
include/linux/platform_data, and update existing support (stargate2
platform) accordingly.
Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
OMAP4460 and OMAP4470 devices have dedicated PMU interrupts and so add these
interrupts to the MPU HWMOD so we can use these for PMU events on these
devices. The PMU interrupts need to be the first interrupts in the array of
interrupts as the ARM PMU driver assumes this.
By using these dedicated interrupts we only need to enable the MPU and DEBUG
sub-systems for PMU to work. This is different to OMAP4430 that did not have
dedicated interrupts and required other power domains in addition to the DEBUG
sub-system to be enabled so we could route the PMU events to the CTI interrupts.
Hence, OMAP4460 and OMAP4470 devices can use the same list of HWMODs to create
the PMU device that is using by OMAP3.
Cc: Ming Lei <ming.lei@canonical.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@ti.com>
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
[paul@pwsan.com: updated to apply]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
The original implementation of this patch was done by Ming Lei for PMU on OMAP4
[1]. Since then the PM runtime calls have been moved into the ARM PMU code and
this greatly simplifies the changes.
The another differnce since the original version, is that it is no longer
necessary to call pm_runtime_get/put during the PMU initialisation was we are no
longer accessing the hardware at this stage.
By adding runtime PM support, we can ensure that the appropriate power and clock
domains are kept on while PMU is being used.
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2011-November/074153.html
Cc: Ming Lei <ming.lei@canonical.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@ti.com>
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
For OMAP4430 PMU events are routed to the CPU via the cross trigger interface
(CTI) because there are no dedicated interrupts. In order to route the PMU
events via the CTI IRQs, the following modules must be enabled:
l3_instr, l3_main_3, debugss
Therefore, build the arm-pmu device via these three HWMODs.
However, the CTI support for this platform still needs some work. Until
that's finished, temporarily disable the PMU on OMAP4430.
Cc: Ming Lei <ming.lei@canonical.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@ti.com>
Signed-off-by: Ming Lei <ming.lei@canonical.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
[paul@pwsan.com: temporarily disabled OMAP4430 PMU support until a
better CTI interface can be implemented; added patch description note]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Convert OMAP2/3 devices to use HWMOD for creating a PMU device. To support PMU
on OMAP2 devices we only need to use MPU sub-system and so we can simply use
the MPU HWMOD to create the PMU device. To support PMU on OMAP3 devices, we need
to use the MPU and DEBUG sub-systems and so use these HWMODs to create the PMU
device for OMAP3.
The MPU HWMOD for OMAP2/3 devices is currently missing the PMU interrupt and so
add the PMU interrupt to the MPU HWMOD for these devices.
This change also moves the PMU code out of the mach-omap2/devices.c files into
its own pmu.c file as suggested by Kevin Hilman to de-clutter devices.c.
Cc: Ming Lei <ming.lei@canonical.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@ti.com>
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
[paul@pwsan.com: fixed checkpatch messages; updated to apply; dropped old-style
initial filename line in header comments]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
To enable PMU with runtime PM support on OMAP3 devices we need to be able to
dynamically enable and disable the debug sub-system at runtime. By adding HWMOD
data for the debug sub-system for OMAP3, we can build the PMU device using the
debug sub-system HWMOD and control this power domain using runtime PM.
Reviewed-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
[paul@pwsan.com: updated to apply; added L4-EMU address space]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
The idle status of the IP blocks and clocks inside the EMU clockdomain
isn't taken into account by the PRCM hardware when deciding whether
the clockdomain is idle. Add a workaround flag in the clockdomain
code, CLKDM_MISSING_IDLE_REPORTING, to deal with this problem, and add
the code necessary to support it.
If CLKDM_MISSING_IDLE_REPORTING is set on a clockdomain, the
clockdomain will be forced active whenever an IP block inside that
clockdomain is in use, even if the clockdomain supports
hardware-supervised idle. When the kernel indicates that the last
active IP block inside the clockdomain is no longer used, the
clockdomain will be forced idle, or, if that mode is not supported in
the hardware, it will be placed into hardware-supervised idle.
This patch is an equal collaboration with Jon Hunter
<jon-hunter@ti.com>. Ming Lei <ming.lei@canonical.com>, Will Deacon
<will.deacon@arm.com>, Madhav Vij <mvij@ti.com>, Kevin Hilman
<khilman@ti.com>, Benoît Cousson <b-cousson@ti.com>, and Santosh
Shilimkar <santosh.shilimkar@ti.com> all made essential contributions
to the understanding of EMU clockdomain power management on OMAP.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Jon Hunter <jon-hunter@ti.com>
Cc: Ming Lei <ming.lei@canonical.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Madhav Vij <mvij@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Jon Hunter <jon-hunter@ti.com>
Some instances of the DMTIMER peripheral on OMAP devices have the ability
to interrupt the on-chip DSP in addition to the ARM CPU. Add a DMTIMER
attribute to indicate which timers can interrupt the DSP. By using the
omap_dm_timer_request_by_cap() API, driver will now be able to allocate
a DMTIMER that can interrupt the DSP based upon this attribute and not require
the driver to know which instance has this capability.
DMTIMERs that have the ability to interrupt the DSP on OMAP devices are as
follows ...
- OMAP1 (OMAP5912/16xx/17xx) devices - All 8 DMTIMERs
- OMAP2/3/4 devices - DMTIMERs 5-8
Please note that for OMAP3+, timer8 has the ability to interrupt the DSP and
generate a PWM output.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Remove the SoC restriction code from the OMAP RNG driver. The
integration code in arch/arm/*omap* should handle this. The device
shouldn't be created if it doesn't exist on the currently-booted SoC.
This allows us to remove some OMAP-specific cpu_is_omap*() calls from
the driver. Also, if other OMAP chips have RNGs that can be used
by Linux, there will be no need to modify the driver.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Matt Mackall <mpm@selenic.com>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Move the OMAP1-specific RNG device creation off to mach-omap1/devices.c,
and create a omap_device-backed registration function for OMAP2+ devices
in mach-omap2/devices.c.
As a nice side-benefit, we can also get rid of
arch/arm/plat-omap/devices.c, thanks to some recent changes from Tony.
One change from the previous behavior is that the RNG devices are now
registered unconditionally. This should allow the RNG drivers to be
loaded as modules, even if the original kernel was not built that way.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Add integration data for the hardware random number generator IP block
on some OMAP SoCs. This appears to be present on at least OMAP2xxx
and OMAP3xxx SoCs, although it is not so easy to tell. It may also be
present on other OMAP2+ SoCs.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Create a minimal driver out of gpmc code. Responsibilities handled by
earlier gpmc initialization is now achieved in probe.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Reviewed-by: Jon Hunter <jon-hunter@ti.com>
[paul@pwsan.com: fixed some checkpatch messages]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Create API for platforms to adapt GPMC to HWMOD
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Reviewed-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Add gpmc hwmod and associated interconnect data
Signed-off-by: Afzal Mohammed <afzal@ti.com>
[paul@pwsan.com: added comments to the use of HWMOD_INIT_NO_RESET]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Add mmu hwmod data for ipu and dsp.
Cc: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Omar Ramirez Luna <omar.luna@linaro.org>
Acked-by: Benoit Cousson <b-cousson@ti.com>
[paul@pwsan.com: cleaned up whitespace]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Add mmu hwmod data for iva and isp.
Due to compatibility an ifdef CONFIG_OMAP_IOMMU_IVA2 needs to be
propagated (previously on iommu resource info) to hwmod data in OMAP3,
so users of iommu and tidspbridge can avoid issues of two modules
managing mmu data/irqs/resets; this until tidspbridge can be migrated
to iommu framework.
Cc: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Omar Ramirez Luna <omar.luna@linaro.org>
[paul@pwsan.com: fixed some kerneldoc and whitespace; ISP MMUs not present
on AM35xx so restricted these hwmods to 34xx/36xx]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
If included without IOMMU_API being selected it will break
compilation:
arch/arm/plat-omap/include/plat/iommu.h:
In function 'dev_to_omap_iommu':
arch/arm/plat-omap/include/plat/iommu.h:148:
error: 'struct dev_archdata' has no member named 'iommu'
This will be seen when hwmod includes iommu.h to get the
structure for attributes. Also needed for tidspbridge
incremental migration to use iommu code.
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Omar Ramirez Luna <omar.luna@linaro.org>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Some struct omap_hwmod records belonging to PRCM IP blocks are missing
HWMOD_NO_IDLEST flags; add them.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Made *ocp2scp_usb_phy_phy_48m* as the main_clk for ocp2scp.
Since this ocp2scp module does not have any fck but does have a
single opt_clock, it is added as the main_clk for ocp2scp. Also
removed phy_48m as the optional clock since it is now made as the
main clock. By this the driver need not enable/disable phy_48m clk
separately and runtime_get/runtime_put will take care of that.
Cc: Benoît Cousson <b-cousson@ti.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Benoît Cousson <b-cousson@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
ocp2scp_usb_phy was missing the address space data and thus
the sysconfig was not populated either.
The usb_host_hs address space was wrong.
Fix both of them and add the missing sysconfig entry.
Reported-by: Kishon Vijay Abraham <kishon@ti.com>
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
SAD2D stands for the die to die interface, and is used for communicating
with the optional stacked modem. This hwmod is added in preparation for
the d2d_idle move from pm34xx.c to hwmod data.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
[paul@pwsan.com: SAD2D presumably doesn't exist on non-OMAP34xx/OMAP36xx,
so only add it to the OMAP34xx/OMAP36xx lists]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
For a reset sequence to complete cleanly, a module needs its
associated clocks to be enabled, otherwise the timeout check
in prcm code can print a false failure (failed to hardreset)
that occurs because the clocks aren't powered ON and the status
bit checked can't transition without them.
Signed-off-by: Omar Ramirez Luna <omar.luna@linaro.org>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Some IP blocks might not be using/controlling more than one
reset line, this check loosens the restriction to fully use
hwmod framework for those drivers.
E.g.: ipu has reset lines: mmu_cache, cpu0 and cpu1.
- As of now cpu1 is not used and hence (with previous check) the
IP block isn't fully enabled by hwmod code.
- Usually ipu and dsp processors configure their mmu module first
and then enable the processors, this involves:
* Deasserting mmu reset line, and enabling the module.
* Deasserting cpu0 reset line, and enabling the processor.
The ones portrayed in this example are controlled through
rproc_fw_boot in drivers/remoteproc/remoteproc_core.c
While at it, prevent _omap4_module_disable if all the hardreset
lines on an IP block are not under reset.
This will allow the driver to:
a. Deassert the reset line.
b. Enable the hwmod through runtime PM default callbacks.
c. Do its usecase.
d. Disable hwmod through runtime PM.
e. Assert the reset line.
Signed-off-by: Omar Ramirez Luna <omar.luna@linaro.org>
[paul@pwsan.com: updated to apply]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
On OMAP4 most modules/hwmods support module level context status. On
OMAP3 and earlier, we relied on the power domain level context status.
Identify all modules that don't support 'context_offs' by adding a
flag bit, HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT. Rest have a valid
'context_offs' populated in .prcm structure already.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
[paul@pwsan.com: add flag bit rather than overloading .context_offs;
update changelog message]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Currently hwmod only provides the offset for the context lose
register, and if we attempt to share the same register between two or
more hwmods, the resulting context loss counts get wrong. Thus, we
need a way to specify which bits are used for the context loss
information for each. This is accomplished by adding a new field to
the omap4 prcm struct, 'lostcontext_mask', which specifies a bit-mask
to use for filtering the register.
Mark the affected hwmods appropriately. 'l4_abe' hwmod uses the
LOSTMEM_AESSMEM bit of RM_ABE_AESS_CONTEXT register, as l4_abe doesn't
have its own dedicated register for this purpose. This register is
shared with 'aess' hwmod, thus both hwmods must also specify which
bits of the register are used for them.
This patch only adds the hwmod data, but a future patch should add
code support such that only the specified bits are read and cleared by
the context lose counter update code. If a hwmod doesn't specify
'lostcontext_mask' (default behavior), the whole contents of the
context register should be used without any filtering.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
[paul@pwsan.com: updated to apply after conversion to use flag bit for
missing module context-loss register; combined data and code patches;
dropped code change due to serial driver breakage]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
On OMAP4, there is no support to read previous logic state
or previous memory state achieved when a power domain transitions
to RET. Instead there are module level context registers.
In order to support the powerdomain level logic/mem_off_counters
on OMAP4, instead use the previous power state achieved (RET) and
the *programmed* logic/mem RET state to derive if a powerdomain lost
logic or did not.
If the powerdomain is programmed to enter RET state and lose logic
in RET state, knowing that the powerdomain entered RET is good enough
to derive that the logic was lost as well, in such cases.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
[paul@pwsan.com: removed dependency on functional power state series for now;
bumped copyright date]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
The decision was made a few months ago to allow struct omap_hwmod
records and struct clk records to omit clockdomain information if the
clockdomain is not software-controllable. See for example commit
868c157df9 ("ARM: OMAP2+: hwmod: remove
prm_clkdm, cm_clkdm; allow hwmods to have no clockdomain").
So convert an existing pr_warning() to a pr_debug() (regarding missing
clockdomains in clocks), and add a pr_debug() for missing hwmod
clockdomains. It's still useful to enable these messages for
debugging, since missing clockdomains can cause hard-to-debug problems
with power management; see for example commit
6c4a057bff ("ARM: OMAP4: clock data:
Force a DPLL clkdm/pwrdm ON before a relock").
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
We're no longer requiring struct omap_hwmod records to contain a
clockdomain. So we shouldn't return -EINVAL any more from
_omap4_wait_target_disable() or _omap4_wait_target_ready() if there's
no clockdomain defined, since that just gets passed back to the
caller. This can result in pointless warnings under the relaxed data
format.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
This API is meant to be an interface to hwmod assert/deassert
function, omap devices can call them through their platform data to
control their reset lines, they are expected to know the name of the
reset line they are trying to control.
Signed-off-by: Omar Ramirez Luna <omar.luna@linaro.org>
[paul@pwsan.com: tweaked some documentation; fixed CodingStyle issue]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Several hwmod function prototypes appear to not have an implementation
because the corresponding functions were removed or renamed.
Those prototypes are unneeded anymore - remove them.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
[paul@pwsan.com: tweaked subject]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
AM33xx hwmod data and miscellaneous clock and hwmod fixes. AM33xx
should now boot on mainline after this is applied, according to
Vaibhav.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJQUWFsAAoJEBvUPslcq6VzI70P/2ECL6bunE1s53JInm7u3HFB
SM5RkOXsF8Sl+2zW0V2R8ZO9OQZC1co8e+6SmlPftv1pVXYP4wtNiFHy1MMQ5Nr7
O2ajKzAcGM1TAiJQ4A1yyfRZucOQQx7pPifACWkjagWy06JaYSUWGaea3z/g/n/U
2CGySqfyzwisiMnyZvIyxHD+cSDtERoweEEbFBKeLRlfecuBs91tIyHNbMqy7cc2
Bf+2G8m0AnrzMqhtzNAKCGJSzFEFDlr0umpLFxC+QLVFHKMJWJ7o2RwuAqf/Z9lw
AS8q2sqzypOPz7eW7z9WLqCW1YlJWhBJmLCJ1alvkebRvWRM0idlVVS3wKjHaP6q
NXF91mn21Xd9xzjXTtgigiDav0MpMuH6+FVWENanx1Rhn23GUIyRdKGMFQOeze2l
lS/vitiTDsCbXQ/EJNlDNHI2skv6AgbBbSpCsg+YivjF16DfZWhlZrFKSvQbWKfW
Mv5PnOnrpcIFNzcH8tGv9XUa61wM/HvRFbcICePAKOKy+vn2VkR/Q1XMmwHANhVf
+AMDtRNCfuspmed1pIdy4vOAcWFdXhL2jZFOBeX6rENJ2+rwJuziEuwsc1xQ8BZ5
KV9RZcg9NwvhEBiLK+K4nViRwTeeSC1OZGIEpIsJ6YOTOfWClYSnTW7In5gY1jNL
HetIvmP55Mm21G4L02D/
=UyqO
-----END PGP SIGNATURE-----
Merge tag 'omap-devel-am33xx-for-v3.7' into test_v3.6-rc6_ocb3.7_cff3.7_odaf3.7
From Paul Walmsley <paul@pwsan.com>:
AM33xx hwmod data and miscellaneous clock and hwmod fixes. AM33xx
should now boot on mainline after this is applied, according to
Vaibhav.
twl-core driver and to fix omap1_defconfig compile when
led driver changes and omap sparse IRQ changes are merged
together. Also fix warnings for omaps not using pinctrl
framework yet.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJQV9rrAAoJEBvUPslcq6Vz2AEQAIwbb/tKUgxubP6i31fuy/33
rP5RsgEMcnh3lD81+3G3hWECvxkfbs2LM06qi20YG90SPXYVd9koIWil407gvcTQ
Nqq+36QBDsQo06ou1Pmy0DeBJ8yo2j3YU+lB6m+Qn7WS+KPqrebt/DMFdMW3Yfc3
zZ87DMfw/5S787z2Uru2CLGLpgv3bOooLvJYv0xBgkKTsRmJGIKJQJ7QoXIQMves
0sLAm/nORu7UU7WvYHd+tU/gC4svfm3WEL+QX4vNvPszCQdTayh7kdZN02eaNLJF
vTUNiKjsW/xmda8+XS6YhP6lPFTPoCkDJWrIZqSWFaCnIIpsQZ+IBNdQMiB8uLtR
eMdngBqIDTmRo5BOLMM/6eU2yzZ/PLeJI1pMQOTylgz2qaugQEnd77mIzEj6sNVn
qSNtAwXTiBEhvA+8cjgsePnJxNtBdwcZ1c8YpEWigFC3cGOl3vHpt0XimIUfrkYX
kKMHnVe9WHQGPFXdkA48ZXrACwzrDb1/3GUVbtGM7rX6/OiS6b4iJzplvBN4j1t1
eOH670dVbU2LhkStHhzV2rbQm7LUyVECkn+CGh13VRJDQrVlzA70g6Vp2KBNkgM+
bxyE7sirHHtzeJtFelYGeuRJ1RULAPxPBrVX7kPsrwcSAshKFnuAC6f9IQjCy3jf
uYcmix5Qg14mN18H0l6S
=omEP
-----END PGP SIGNATURE-----
Merge tag 'cleanup-fixes-for-v3.7' into test_v3.6-rc6_ocb3.7_cff3.7_odaf3.7
These fixes are needed to fix non-omap build breakage for
twl-core driver and to fix omap1_defconfig compile when
led driver changes and omap sparse IRQ changes are merged
together. Also fix warnings for omaps not using pinctrl
framework yet.
These changes fix some of the more meaningful warnings that smatch
returns for the OMAP subarch code, and unwraps strings that are
wrapped at the 80-column boundary, to conform with the current
practice.
Basic build, boot, and PM logs are available here:
http://www.pwsan.com/omap/testlogs/warnings_a_cleanup_3.7/20120912025927/
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJQUKL1AAoJEMePsQ0LvSpL+a8QAJlJR9uwqUKu60GfbQEeegce
k6pr0xXYvHEmbro/v6O4ezs2o716EBgwBWnId97oOZvVnwhPbEHR87UH8FFOIWOQ
+/ui5MxXtYWNjYcDOzdF95reFM1szAAxQu8k9wXg+WBtZ4zCkhknpoftShRbOdg0
BgO0r1iY/wuoFaYgGFKSNdObPVgSTENjbtg/LVvB/V3PQjYmUBosJVH0tPO/LQio
pWhozfFuiWbARYxPg6dMOn8yQ5mCeWErpv4WZjM+dgcrkLYyPdI2uUS3Ka8F7Az2
ImC+k0gU6WwkjyKqv/SG2wg5+3Sh8ZZsX0EKXwq0gQEmLWacENS1ELRT3+HcxGru
HoAhE46URb4NGzBt7rkIkGg0HcajfORDtZSrGfsEclDmrVV5+JgUzC+PEDiwSxVU
LqpJIZ8lxjqBNPSlmXqtEgTG32M6E9fDII8JdGC64vUv+vXzuhpJCXF78I8+A+Hv
oSBbTOCzYGz1xp06G6Hzadpo5I1LocBRemsnhw2O9oNDdUZxiGo/qJcWfk2wpMQ6
4c/kHbYEsJ6/7eVe5kNtdkeptAXp1AFO5XIhQpSAs1O1Rr++nDNahaUJA56xev8x
GoEZCYLGMGpQnINW6g0Srzwp8n1ywSgt3Gt2fbDTAP+Q02DPT3IIWWs4LlIDIrjZ
w0q1kAp1+In5is3pxJvT
=ythb
-----END PGP SIGNATURE-----
Merge tag 'omap-cleanup-b-for-3.7' into test_v3.6-rc6_ocb3.7_cff3.7_odaf3.7
smatch and string-wrapping cleanups for the OMAP subarch code.
These changes fix some of the more meaningful warnings that smatch
returns for the OMAP subarch code, and unwraps strings that are
wrapped at the 80-column boundary, to conform with the current
practice.
Basic build, boot, and PM logs are available here:
http://www.pwsan.com/omap/testlogs/warnings_a_cleanup_3.7/20120912025927/
* 'for-arm-soc-next' of git://git.linaro.org/people/ljones/linux-3.0-ux500:
ARM: ux500: Fix SSP register address format
ARM: ux500: Apply tc3589x's GPIO/IRQ properties to HREF's DT
ARM: ux500: Remove redundant #gpio-cell properties from Snowball DT
ARM: ux500: Add all encompassing sound node to the HREF Device Tree
ARM: ux500: Add nodes for the MSP into the HREF Device Tree
ARM: ux500: Add all known I2C sub-device nodes to the HREF DT
ARM: ux500: Stop registering I2C sub-devices for HREF when DT is enabled
ARM: ux500: Stop registering Audio devices for HREF when DT is enabled
ARM: ux500: Add all encompassing sound node to the Snowball Device Tree
ARM: ux500: Add nodes for the MSP into Device Tree
ARM: ux500: Rename MSP board file to something more meaningful
ARM: ux500: Remove platform registration of MSP devices
ARM: ux500: Stop registering the MOP500 Audio driver from platform code
ARM: ux500: Pass MSP DMA platform data though AUXDATA
ARM: ux500: Fork MSP platform registration for step-by-step DT enablement
ARM: ux500: Add AB8500 CODEC node to DB8500 Device Tree
ARM: ux500: Clean-up MSP platform code
ARM: ux500: Pass SDI DMA information though AUX_DATA to MMCI
ARM: ux500: Add UART support to the HREF Device Tree
ARM: ux500: Add skeleton Device Tree for the HREF reference board
...
+ sync to v3.6-rc6
The platform data was moved, but this file was introduced in parallel
so didn't get caught in the sweeping changes. Fix it up now.
Signed-off-by: Olof Johansson <olof@lixom.net>
This moves a few of the newly introduced dtb targets to the common
dts/Makefile instead of the per-platform file.
Signed-off-by: Olof Johansson <olof@lixom.net>
From Jason Cooper:
New drivers:
- pinctrl (dove, kirkwood, mvebu)
- gpio (mvebu)
* 'kirkwood/drivers' of git://git.infradead.org/users/jcooper/linux:
arm: mvebu: add gpio support in defconfig
arm: mvebu: add DT information for GPIO banks on Armada 370 and XP
arm: mvebu: use GPIO support now that a driver is available
Documentation: add description of DT binding for the gpio-mvebu driver
gpio: introduce gpio-mvebu driver for Marvell SoCs
arm: mvebu: select the pinctrl drivers for Armada 370 and Armada XP platforms
arm: mvebu: split Kconfig options for Armada 370 and XP
ARM: mvebu: adjust Armada XP evaluation board DTS
ARM: mvebu: Add pinctrl support to Armada 370 SoC
ARM: mvebu: Add pinctrl support to Armada XP SoCs
pinctrl: mvebu: add pinctrl driver for Armada XP
pinctrl: mvebu: add pinctrl driver for Armada 370
pinctrl: mvebu: kirkwood pinctrl driver
pinctrl: mvebu: dove pinctrl driver
pinctrl: mvebu: pinctrl driver core
Signed-off-by: Olof Johansson <olof@lixom.net>
* 'kirkwood/addr_decode' of git://git.infradead.org/users/jcooper/linux:
arm: mvebu: add address decoding controller to the DT
arm: mvebu: add basic address decoding support to Armada 370/XP
arm: plat-orion: make bridge_virt_base non-const to support DT use case
arm: plat-orion: introduce PLAT_ORION_LEGACY hidden config option
arm: plat-orion: use void __iomem pointers for addr-map functions
arm: plat-orion: use void __iomem pointers for time functions
arm: plat-orion: use void __iomem pointers for MPP functions
arm: plat-orion: use void __iomem pointers for UART registration functions
arm: mach-mvebu: use IOMEM() for base address definitions
arm: mach-orion5x: use IOMEM() for base address definitions
arm: mach-mv78xx0: use IOMEM() for base address definitions
arm: mach-kirkwood: use IOMEM() for base address definitions
arm: mach-dove: use IOMEM() for base address definitions
arm: mach-orion5x: use plus instead of or for address definitions
arm: mach-mv78xx0: use plus instead of or for address definitions
arm: mach-kirkwood: use plus instead of or for address definitions
arm: mach-dove: use plus instead of or for address definitions
This branch had quite a few conflicts, in particular with the PCI static
map rework from Rob Herring, and a few other context conflicts due to
changes in Kconfig, etc.
I fixed up conflicts in:
arch/arm/Kconfig
arch/arm/mach-dove/common.c
arch/arm/mach-dove/include/mach/dove.h
arch/arm/mach-kirkwood/common.c
arch/arm/mach-kirkwood/include/mach/kirkwood.h
arch/arm/mach-mv78xx0/common.c
arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
arch/arm/mach-orion5x/common.c
arch/arm/mach-orion5x/include/mach/orion5x.h
Signed-off-by: Olof Johansson <olof@lixom.net>
From Jason Cooper:
Misc:
- trim includes for board-dnskw.c
* 'kirkwood/cleanup' of git://git.infradead.org/users/jcooper/linux:
ARM: kirkwood: Trim excess #includes in board-dnskw.c
From Jason Cooper:
New bindings:
- iconnect nand and keys
- mv_cesa
- gpio-fan
* 'kirkwood/dt' of git://git.infradead.org/users/jcooper/linux:
ARM: kirkwood: Use devicetree to define DNS-32[05] fan
hwmon: Add devicetree bindings to gpio-fan
Crypto: CESA: Add support for DT based instantiation.
ARM: Kirkwood: Describe iconnect nand in DT.
ARM: Kirkwood: Describe iconnect keys in DT.
From Jason Cooper:
defconfig:
- update kirkwood_defconfig via 'make oldconfig'
- Add all Kirkwood DT boards to the defconfig
- enable SERIAL_OF_PLATFORM and ORION_WATCHDOG in kirkwood_defconfig
* 'kirkwood/defconfig' of git://git.infradead.org/users/jcooper/linux:
ARM: Kirkwood: add DT boards to defconfig
ARM: Kirkwood: update defconfig
* 'kirkwood/boards' of git://git.infradead.org/users/jcooper/linux:
ARM: Dove: allow PCI to be disabled
ARM: dove: SolidRun CuBox DT
ARM: dove: add device tree descriptors
ARM: dove: add device tree based machine descriptor
ARM: dove: add crypto engine
ARM: dove: add clock gating control
ARM: dove: unify clock setup
ARM: initial DTS support for km_kirkwood
arm: add documentation describing Marvell families of SoC
ARM: kirkwood: DT descriptor for Seagate FreeAgent Dockstar
ARM: kirkwood: DT board setup for Seagate FreeAgent Dockstar
ARM: Kirkwood: Iomega ix2-200 DT support
Context conflicts in arch/arm/Kconfig and arch/arm/mach-dove/common.c.
The new device trees added to arch/arm/mach-kirkwood/Makefile.boot are
kept and dealt with in a separate changeset, since moving them out to
the new Makefile in this merge commit doesn't work well.
Signed-off-by: Olof Johansson <olof@lixom.net>
By Arnd Bergmann (21) and Wei Yongjun (1)
via Olof Johansson (2) and Haojian Zhuang (1)
* next/cleanup: (22 commits)
ARM: mmp: using for_each_set_bit to simplify the code
net: seeq: use __iomem pointers for MMIO
video: da8xx-fb: use __iomem pointers for MMIO
scsi: eesox: use __iomem pointers for MMIO
serial: ks8695: use __iomem pointers for MMIO
input: rpcmouse: use __iomem pointers for MMIO
ARM: samsung: use __iomem pointers for MMIO
ARM: spear13xx: use __iomem pointers for MMIO
ARM: sa1100: use __iomem pointers for MMIO
ARM: prima2: use __iomem pointers for MMIO
ARM: nomadik: use __iomem pointers for MMIO
ARM: msm: use __iomem pointers for MMIO
ARM: lpc32xx: use __iomem pointers for MMIO
ARM: ks8695: use __iomem pointers for MMIO
ARM: ixp4xx: use __iomem pointers for MMIO
ARM: iop32x: use __iomem pointers for MMIO
ARM: iop13xx: use __iomem pointers for MMIO
ARM: integrator: use __iomem pointers for MMIO
ARM: imx: use __iomem pointers for MMIO
ARM: ebsa110: use __iomem pointers for MMIO
...
Pull ARM and clkdev fixes from Russell King:
"Two patches for clkdev which resolve the long standing issue that the
devm_* versions were dependent on clkdev, which they shouldn't have
been. Instead, they're dependent on HAVE_CLK instead, which implies
that you're providing clk_get() and clk_put().
A small fix to the ARM decompressor to ensure that the page tables are
properly interpreted by the CPU, and reserve syscall 378 for kcmp (the
checksyscalls.sh script is unfortunately currently broken so arch
maintainers aren't getting notified of new syscalls...)
Lastly, a larger fix for an issue between the common clk subsystem and
smp_twd which causes warnings to be spat out."
* 'fixes' of git://git.linaro.org/people/rmk/linux-arm:
ARM: reserve syscall 378 for kcmp
ARM: 7535/1: Reprogram smp_twd based on new common clk framework notifiers
ARM: 7537/1: clk: Fix release in devm_clk_put()
ARM: 7532/1: decompressor: reset SCTLR.TRE for VMSA ARMv7 cores
ARM: 7534/1: clk: Make the managed clk functions generically available
__iomem annotation cleanup branch from Arnd.
* cleanup/__iomem: (21 commits)
net: seeq: use __iomem pointers for MMIO
video: da8xx-fb: use __iomem pointers for MMIO
scsi: eesox: use __iomem pointers for MMIO
serial: ks8695: use __iomem pointers for MMIO
input: rpcmouse: use __iomem pointers for MMIO
ARM: samsung: use __iomem pointers for MMIO
ARM: spear13xx: use __iomem pointers for MMIO
ARM: sa1100: use __iomem pointers for MMIO
ARM: prima2: use __iomem pointers for MMIO
ARM: nomadik: use __iomem pointers for MMIO
ARM: msm: use __iomem pointers for MMIO
ARM: lpc32xx: use __iomem pointers for MMIO
ARM: ks8695: use __iomem pointers for MMIO
ARM: ixp4xx: use __iomem pointers for MMIO
ARM: iop32x: use __iomem pointers for MMIO
ARM: iop13xx: use __iomem pointers for MMIO
ARM: integrator: use __iomem pointers for MMIO
ARM: imx: use __iomem pointers for MMIO
ARM: ebsa110: use __iomem pointers for MMIO
ARM: at91: use __iomem pointers for MMIO
...
Signed-off-by: Olof Johansson <olof@lixom.net>
The new common clk framework includes basic definitions for mux and
divider clocks. These definitions depend on shift and width values
instead of the pre-computed masks that the OMAP/AM33XX clk framework
has traditionally used when accessing the register to control the
mux or divisor.
To ease this transition the masks are left intact and
the width field is simply added alongside the shift and mask data.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Mike Turquette <mturquette@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
The new common clk framework includes basic definitions for mux and
divider clocks. These definitions depend on shift and width values
instead of the pre-computed masks that the OMAP clk framework has
traditionally used when accessing the register to control the mux or
divisor.
To ease this transition the masks are left intact and the width field is
simply added alongside the shift and mask data.
Signed-off-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
While we move to Common Clk Framework (CCF), direct deferencing of struct
clk wouldn't be possible anymore. Hence get rid of all such instances
in the current clock code and use macros/helpers similar to the ones that
are provided by CCF.
While here also concatenate some strings split across multiple lines
which seem to be needed anyway.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: simplified some compound expressions; reformatted some
messages]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Mike Turquette <mturquette@linaro.org>
Moving to Common clk framework for OMAP would mean we no longer use
internal lookup mechanism like omap_clk_get_by_name().
get rid of all its usage mostly from hwmod and omap_device
code.
Moving to clk_get() also means the respective platforms
need the clkdev tables updated with an entry for all clocks
used by hwmod to have clock name same as the alias.
Based on original changes from Mike Turquette.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Cc: Russell King - ARM Linux <linux@arm.linux.org.uk>
[paul@pwsan.com: removed IS_ERR_OR_NULL() conversion (rmk comment);
restricted omap_96m_alwon_fck_3630 to OMAP36xx; added missing AM35xx
clock aliases for emac_fck, emac_ick, vpfe_ick, vpfe_fck; added
aliases rng_ick and several emulation clocks]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
As part of Common Clk Framework (CCF) the clk_enable() operation
was split into a clk_prepare() which could sleep, and a clk_enable()
which should never sleep. Similarly the clk_disable() was
split into clk_disable() and clk_unprepare(). This was
needed to handle complex cases where in a clk gate/ungate
would require a slow and a fast part to be implemented.
None of the clocks below seem to be in the 'complex' clocks
category and are just simple clocks which are enabled/disabled
through simple register writes.
Most of the instances also seem to be called in non-atomic
context which means its safe to move all of those from
using a clk_enable() to clk_prepare_enable() and clk_disable() to
clk_disable_unprepare().
For some others, mainly the ones handled through the hwmod framework
there is a possibility that they get called in either an atomic
or a non-atomic context.
The way these get handled below work only as long as clk_prepare
is implemented as a no-op (which is the case today) since this gets
called very early at boot while most subsystems are unavailable.
Hence these are marked with a *HACK* comment, which says we need
to re-visit these once we start doing something meaningful with
clk_prepare/clk_unprepare like doing voltage scaling or something
that involves i2c.
This is in preparation of OMAP moving to CCF.
Based on initial changes from Mike Turquette.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
For OMAP4, the dmtimers are located in the Wake-up, ABE and Peripheral (PER)
power domains. Hence, when the dmtimer is configured to use the "timer_sys_ck"
as its functional clock the actual clock used is different depending on whether
the clock is in the Wake-up, ABE or PER domain. So when we look-up the dmtimer's
"timer_sys_ck" we need to specify the timer device name as well as clock alias
to find the right clock.
Currently, the device names for the timers have the format "omap_timer.X" where
X is the timer instance number. When using to device tree, the format of the
device name created by device-tree is different and has the format
"<reg-address>.<device-name>" (this is assuming that the device-tree "reg"
property is specified). This causes the look-up for the OMAP4 "timer_sys_ck" to
fail. To fix this add new timer clock alias for using device-tree.
Please note that adding a 2nd set of clock aliases for the same clocks to only
temporary until device-tree migration is complete. Then we can remove the legacy
aliases. Hence, I have marked the legacy aliases with a "TODO" to remove them.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
[paul@pwsan.com: updated to apply]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Add AM335x cpu0 clock entry to the corresponding clock data file. This
is useful in getting the correct mpu clock pointer to change the cpu
frequency in cpufreq driver.
Signed-off-by: AnilKumar Ch <anilkumar@ti.com>
[paul@pwsan.com: changed patch subject]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
These clkdev aliases should make it possible to remove the
cpu_is_omap*() calls and the omap_device*() call from
drivers/cpufreq/omap-cpufreq.c during the next merge window. Those
are interfering with multi-subarch ARM kernels.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Rafael J. Wysocki <rjw@sisk.pl>
Acked-by: Kevin Hilman <khilman@ti.com>
The platform device name "usbhs_tll" is added for the functional,
interface and channel clocks of the TLL module.
Signed-off-by: Keshava Munegowda <keshava_mgowda@ti.com>
Reviewed-by: Partha Basak <parthab@india.ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
In commit c59b537 (ARM: OMAP2+: Simplify dmtimer clock aliases) new clock
aliases were added for OMAP2+ devices. For OMAP2420, I incorrectly set the
clock flag as CK_243X instead of CK_242X. This did not introduce a regression
as the clock flags are not checked for OMAP2 devices. This also explains why
I did not catch this when testing on OMAP2420.
Fix the clock flags for these aliases for correctness.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
The file is currently called 'clock3xxx_data.c', so this comment is
out of date.
Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
[paul@pwsan.com: wrote changelog]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
AM33xx hwmod data and miscellaneous clock and hwmod fixes. AM33xx
should now boot on mainline after this is applied, according to
Vaibhav.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJQUWFsAAoJEBvUPslcq6VzI70P/2ECL6bunE1s53JInm7u3HFB
SM5RkOXsF8Sl+2zW0V2R8ZO9OQZC1co8e+6SmlPftv1pVXYP4wtNiFHy1MMQ5Nr7
O2ajKzAcGM1TAiJQ4A1yyfRZucOQQx7pPifACWkjagWy06JaYSUWGaea3z/g/n/U
2CGySqfyzwisiMnyZvIyxHD+cSDtERoweEEbFBKeLRlfecuBs91tIyHNbMqy7cc2
Bf+2G8m0AnrzMqhtzNAKCGJSzFEFDlr0umpLFxC+QLVFHKMJWJ7o2RwuAqf/Z9lw
AS8q2sqzypOPz7eW7z9WLqCW1YlJWhBJmLCJ1alvkebRvWRM0idlVVS3wKjHaP6q
NXF91mn21Xd9xzjXTtgigiDav0MpMuH6+FVWENanx1Rhn23GUIyRdKGMFQOeze2l
lS/vitiTDsCbXQ/EJNlDNHI2skv6AgbBbSpCsg+YivjF16DfZWhlZrFKSvQbWKfW
Mv5PnOnrpcIFNzcH8tGv9XUa61wM/HvRFbcICePAKOKy+vn2VkR/Q1XMmwHANhVf
+AMDtRNCfuspmed1pIdy4vOAcWFdXhL2jZFOBeX6rENJ2+rwJuziEuwsc1xQ8BZ5
KV9RZcg9NwvhEBiLK+K4nViRwTeeSC1OZGIEpIsJ6YOTOfWClYSnTW7In5gY1jNL
HetIvmP55Mm21G4L02D/
=UyqO
-----END PGP SIGNATURE-----
Merge tag 'omap-devel-am33xx-for-v3.7' into test_v3.6-rc6_cff3.7_odaf3.7
From Paul Walmsley <paul@pwsan.com>:
AM33xx hwmod data and miscellaneous clock and hwmod fixes. AM33xx
should now boot on mainline after this is applied, according to
Vaibhav.
twl-core driver and to fix omap1_defconfig compile when
led driver changes and omap sparse IRQ changes are merged
together. Also fix warnings for omaps not using pinctrl
framework yet.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJQV9rrAAoJEBvUPslcq6Vz2AEQAIwbb/tKUgxubP6i31fuy/33
rP5RsgEMcnh3lD81+3G3hWECvxkfbs2LM06qi20YG90SPXYVd9koIWil407gvcTQ
Nqq+36QBDsQo06ou1Pmy0DeBJ8yo2j3YU+lB6m+Qn7WS+KPqrebt/DMFdMW3Yfc3
zZ87DMfw/5S787z2Uru2CLGLpgv3bOooLvJYv0xBgkKTsRmJGIKJQJ7QoXIQMves
0sLAm/nORu7UU7WvYHd+tU/gC4svfm3WEL+QX4vNvPszCQdTayh7kdZN02eaNLJF
vTUNiKjsW/xmda8+XS6YhP6lPFTPoCkDJWrIZqSWFaCnIIpsQZ+IBNdQMiB8uLtR
eMdngBqIDTmRo5BOLMM/6eU2yzZ/PLeJI1pMQOTylgz2qaugQEnd77mIzEj6sNVn
qSNtAwXTiBEhvA+8cjgsePnJxNtBdwcZ1c8YpEWigFC3cGOl3vHpt0XimIUfrkYX
kKMHnVe9WHQGPFXdkA48ZXrACwzrDb1/3GUVbtGM7rX6/OiS6b4iJzplvBN4j1t1
eOH670dVbU2LhkStHhzV2rbQm7LUyVECkn+CGh13VRJDQrVlzA70g6Vp2KBNkgM+
bxyE7sirHHtzeJtFelYGeuRJ1RULAPxPBrVX7kPsrwcSAshKFnuAC6f9IQjCy3jf
uYcmix5Qg14mN18H0l6S
=omEP
-----END PGP SIGNATURE-----
Merge tag 'cleanup-fixes-for-v3.7' into test_v3.6-rc6_cff3.7_odaf3.7
These fixes are needed to fix non-omap build breakage for
twl-core driver and to fix omap1_defconfig compile when
led driver changes and omap sparse IRQ changes are merged
together. Also fix warnings for omaps not using pinctrl
framework yet.
Lots of code has now moved into the devicetree, leaving a collection of
useless header files. Tidy them up.
This applies cleanly atop of my previous patch, "[PATCH V2 2/2] ARM:
kirkwood: Use devicetree to define DNS-32[05] fan", which also removes
gpio-fan.h
Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Remove the use of set_hs_extmute callback and let the codec driver to
handle the extmute GPIO.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
To help the driver to get the correct memory range to access McPDM
registers.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The gpioX aliases are needed so that the driver can use
of_alias_get_id() to get a 0-based number of the GPIO bank, which we
then use to compute the base GPIO of the bank being probed. This is
similar to what gpio-mxs.c is doing.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This patch actually enables pinctrl drivers for Armada 370 and XP.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Until now, all the code for Armada 370 and XP was common, so we had a
single Kconfig option to support all boards using both SoCs. With the
addition of pinctrl drivers, this situation has changed: those two
SoCs are radically different in terms of pinctrl, so they have two
separate drivers. Since pinctrl drivers are typically select-ed from
the SoC Kconfig option, it makes sense to split the 370/XP option into
two separate options: one for Armada 370 and another for Armada XP.
We keep an hidden option selected by both ARMADA_370 and ARMADA_XP in
order to easily compile common code.
A followup patch actually makes use of this split to select the
appropriate pinctrl drivers.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory Clement <gregory.clement@free-electrons.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Armada XP evaluation board is based on the MV78460 Armava XP
SoC. Now that we have separate .dtsi files for the three different
SoCs of the Armada XP family, use the appropriate one as include for
the Armada XP evaluation board .dts file.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commits adds the necessary device tree information to define the
compatible property for the pinctrl driver instance of Armada 370 SoC.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commits adds the necessary device tree information to define the
compatible property for the pinctrl driver instance of Armada XP SoCs.
Until now, the device tree representation considered the Armada XP as
a single SoC. But in fact, there are three different SoCs in the
Armada XP families, with different number of CPU cores, different
number of Ethernet interfaces... and different number of muxable pins
or functions. We therefore introduce three armada-xp-mv78xx0.dtsi for
the three SoCs of the Armada XP family. The current armada-xp-db.dts
evaluation board uses the MV78460 variant of the SoC.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This patch adds a pinctrl driver core for Marvell SoCs plus DT
binding documentation. This core driver will be used by SoC family
specific drivers, i.e. Armada XP, Armada 370, Dove, Kirkwood, aso.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Conflicts:
arch/arm/Kconfig
Remove more board-specific code by using devicetree to define the fan
attached to both boards.
Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Based on work by Michael Walle and Jason Cooper.
Added support for getting the interrupt number and address of SRAM
from DT.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Conflicts:
arch/arm/mach-kirkwood/board-dt.c
Define the nand and its partitions in DT and remove them from cmdline
Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Define the 2 keys found on iconnect in DT. It's also changing the keycodes/
switches to use better ones.
Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
No real need to have a separate core.h from the common.h file. Fold
these two prototypes into the common header file.
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: David Brown <davidb@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Misc SoC-related fixes/cleanups for Samsung platforms
* 'next/devel-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: SAMSUNG: Add check for NULL in clock interface
ARM: EXYNOS: Put PCM, Slimbus, Spdif clocks to off state
ARM: EXYNOS: Add bus clock for FIMD
ARM: SAMSUNG: Fix HDMI related warnings
ARM: S3C24XX: Add .get_rate callback for "camif-upll" clock
ARM: EXYNOS: Fix incorrect help text
ARM: EXYNOS: Turn off clocks for NAND, OneNAND and TSI controllers
+ sync to 3.6-rc6
The TLL specific code such as channels clocks enable/disable,
initialization functions are removed from the USBHS core
driver. The hwmod of the usb tll is retrieved and omap device
build is performed to created the platform device for the
usb tll component.
Signed-off-by: Keshava Munegowda <keshava_mgowda@ti.com>
Reviewed-by: Partha Basak <parthab@india.ti.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
The usbhs driver invokes the enable/disable APIs of the
usb tll driver in the runtime resume/suspend callbacks
of the runtime get sync and put sync of the usbhs driver.
Signed-off-by: Keshava Munegowda <keshava_mgowda@ti.com>
Reviewed-by: Partha Basak <parthab@india.ti.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
The platform driver for the TLL component of the OMAP USB host controller
is implemented. Depending on the TLL hardware revision , the TLL channels
are configured. The USB HS core driver uses this driver through exported
APIs from the TLL platform driver.
usb_tll_enable and usb_tll_disble are the exported APIs of the USB TLL
platform driver.
Signed-off-by: Keshava Munegowda <keshava_mgowda@ti.com>
Reviewed-by: Partha Basak <parthab@india.ti.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit adds basic support for address decoding configuration for
the Armada 370 and Armada XP SoCs, re-using the infrastructure
provided in plat-orion.
For now, only a BootROM window is configured on Armada XP, which is
needed to get the non-boot CPUs started and is therefore a requirement
for SMP support.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
For the Armada 370 and XP SoCs where the DT is used, we need to fill
at runtime the bridge_virt_base field on the
orion_addr_map_cfg. Therefore, remove the 'const' qualifier on this
field.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Until now, the PLAT_ORION configuration option was common to all the
Marvell EBU SoCs, and selecting this option had the effect of enabling
the MPP code, GPIO code, address decoding and PCIe code from
plat-orion, as well as providing access to driver-specific header
files from plat-orion/include.
However, the Armada 370 and XP SoCs will not use the MPP and GPIO code
(instead some proper pinctrl and gpio drivers are in preparation), and
generally, we want to move away from plat-orion and instead have
everything in mach-mvebu.
That said, in the mean time, we want to leverage the driver-specific
headers as well as the address decoding code, so we introduce
PLAT_ORION_LEGACY. The older Marvell SoCs need to select
PLAT_ORION_LEGACY, while the newer Marvell SoCs need to select
PLAT_ORION. Of course, when PLAT_ORION_LEGACY is selected, it
automatically selects PLAT_ORION.
Then, with just PLAT_ORION, you have the address decoding code plus
the driver-specific headers. If you add PLAT_ORION_LEGACY to this, you
gain the old MPP, GPIO and PCIe code.
Again, this is only a temporary solution until we make all Marvell EBU
platforms converge into the mach-mvebu directory. This solution avoids
duplicating the existing address decoding code into mach-mvebu.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The functions for address mapping management now take void __iomem
pointers, so we remove the temporary "unsigned long" casts from the
mach-*/common.c files.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The functions for time management now take void __iomem pointers, so
we remove the temporary "unsigned long" casts from the mach-*/common.c
files.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The registration function for MPP now takes void __iomem pointers, so
we remove the temporary "unsigned long" casts from the mach-*/mpp.c
files.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The registration functions for UARTs now take void __iomem pointers,
so we remove the temporary "unsigned long" casts from the
mach-*/common.c files.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
We now define all virtual base address constants using IOMEM() so that
those are naturally typed as void __iomem pointers, and we do the
necessary adjustements in the mach-mvebu code.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
We now define all virtual base address constants using IOMEM() so that
those are naturally typed as void __iomem pointers, and we do the
necessary adjustements in the mach-orion5x code.
Note that we introduce a few temporary additional "unsigned long"
casts when calling into plat-orion functions. Those are removed by
followup patches converting plat-orion functions to void __iomem
pointers as well.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
We now define all virtual base address constants using IOMEM() so that
those are naturally typed as void __iomem pointers, and we do the
necessary adjustements in the mach-mv78xx0 code.
Note that we introduce a few temporary additional "unsigned long"
casts when calling into plat-orion functions. Those are removed by
followup patches converting plat-orion functions to void __iomem
pointers as well.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
We now define all virtual base address constants using IOMEM() so that
those are naturally typed as void __iomem pointers, and we do the
necessary adjustements in the mach-kirkwood code.
Note that we introduce a few temporary additional "unsigned long"
casts when calling into plat-orion functions. Those are removed by
followup patches converting plat-orion functions to void __iomem
pointers as well.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
We now define all virtual base address constants using IOMEM() so that
those are naturally typed as void __iomem pointers, and we do the
necessary adjustements in the mach-dove code.
Note that we introduce a few temporary additional "unsigned long"
casts when calling into plat-orion functions. Those are removed by
followup patches converting plat-orion functions to void __iomem
pointers as well.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Since we are going to use IOMEM() to define many base virtual
addresses, we can no longer use binary or to define the individual
register addresses ("binary or" arithmetic on pointers is not
allowed). Instead, use the more conventional plus operator to do so.
The binary or operators were actually not useful because the low-order
bits of the base address were always zero, so the usage of the binary
or operators was effectively identical to a plus operator.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Since we are going to use IOMEM() to define many base virtual
addresses, we can no longer use binary or to define the individual
register addresses ("binary or" arithmetic on pointers is not
allowed). Instead, use the more conventional plus operator to do so.
The binary or operators were actually not useful because the low-order
bits of the base address were always zero, so the usage of the binary
or operators was effectively identical to a plus operator.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Since we are going to use IOMEM() to define many base virtual
addresses, we can no longer use binary or to define the individual
register addresses ("binary or" arithmetic on pointers is not
allowed). Instead, use the more conventional plus operator to do so.
The binary or operators were actually not useful because the low-order
bits of the base address were always zero, so the usage of the binary
or operators was effectively identical to a plus operator.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Since we are going to use IOMEM() to define many base virtual
addresses, we can no longer use binary or to define the individual
register addresses ("binary or" arithmetic on pointers is not
allowed). Instead, use the more conventional plus operator to do so.
The binary or operators were actually not useful because the low-order
bits of the base address were always zero, so the usage of the binary
or operators was effectively identical to a plus operator.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Allow PCI support for Dove to be disabled. Some platforms do not have
anything connected to the PCIe ports, so requiring PCI support to be
built into the kernel just wastes space, and presents a lot more config
options than are necessary.
However, select USB_ARCH_HAS_EHCI so that we can still have EHCI
support.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This patch adds basic support for the SolidRun CuBox to DT based
mach-dove. There are still some issues related to ongoing orion/mvebu
development, e.g. gpio-led will not work as there is no DT pinctrl
for dove yet and we don't have board specific setup code. Nevertheless,
the DT description is already introduced here.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This patch adds device tree decriptors for dove SoC and currently
supported boards.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This adds a generic DT_MACHINE for mach-dove. As with other orion based
SoCs there still is some glue code required to make all internal devices
work, i.e. auxdata is provided to pass clocks to corresponding device
drivers.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This patch adds a dove specific setup function for the Marvell CESA
crypto engine available on orion based SoCs. Dove setup was just
missing a function to call orion_crypto_init with dove specific
setup.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This patch adds clock gates from the clock gating control register
available on dove. All clock gates are hooked up to tclk, except for
gigabit ethernet controller (ge) which is a child of gephy to allow
both enabled/disabled at the same time.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This patch synchronizes the clock setup of dove with other orion-based
platforms.
In dove_find_tclk there was a note about DOVE_SAMPLE_HI/LO register to
detect tclk. While it might be possible to set a different tclk frequency
with reset strapping the Dove datasheets don't tell anything about tclk
frequency here. Therefore, I removed that comment.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This is a first attempt to support the km_kirkwood reference design with
a device tree. This km_kirkwood design is present in many Keymile
products. It is based on the Marvell Bobcat SOC which integrates a
Kirkwood CPU next to a big L2 Ethernet Switch. The Kirkwood in the SOC
is very similar to the "normal" one, but there are a few differences.
This initial support is minimal: the kernel can boot with network
(ge0), serial port and NAND functional.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Cc: Holger Brunck <holger.brunck@keymile.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
kcmp has appeared on x86, but has not been noticed because
checksyscalls.sh is broken at the moment. Reserve ARM syscall 378
for this should we ever need it, and add an __IGNORE entry for this
unimplemented syscall.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This adds the corresponding device tree descriptor for the
Seagate FreeAgent Dockstar based on Kirkwood DT.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This add a DT compatible board specific setup for the Seagate
FreeAgent Dockstar.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Using for_each_set_bit() to simplify the code.
spatch with a semantic match is used to found this.
(http://coccinelle.lip6.fr/)
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Merged existing board files to a single dt-capable file.
Converted irq and timer code to devicetree.
Removed existing device files that are no longer required with
devicetree support.
All existing platform devices are converted to devicetree nodes
except PWM.
Removed restart.c and moved code into vt8500.c to remove
duplicate PMC code.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Being a module_init call, highbank_pm_init will cause problem with
multi-platform build running on other platforms. Call it from
.init_machine instead.
Reported-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Since the dtb targets have moved to arch/arm/boot/dts/Makefile, sweep
the platforms that have had new targets added recently and move them over.
While I was at it, I also made the dtb generation more generic, i.e. if
the platform is enabled then all dtbs for that platform will be created.
Signed-off-by: Olof Johansson <olof@lixom.net>
Cc: Tony Lindgren <tony@atomide.com>
Cc: David Brown <davidb@codeaurora.com>
Cc: Barry Song <Baohua.Song@csr.com>
Cc: Simon Horman <horms@verge.net.au>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
socfpga, picoxcell, and vexpress.
Multi-platform support is dependent on mach/gpio.h removal and
restructuring of DEBUG_LL and dtb build rules included in this branch.
This has been built for all defconfigs, and booted on highbank with
all 5 platforms enabled.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQEcBAABAgAGBQJQU4miAAoJEMhvYp4jgsXi1vMH/A4JJXe24cyo31rHJspZDSFg
nnCbnGKfDEOIHwLA8C3OeJuhswMlP/vWlGC512QXL8903XpZ2VJe63f2CLo1mN7Z
hg3JPWrp2VXZ/bqdMnUcw2CtlylrhyG9MUPapkcp+5Agjz2lwaJtRNL6LRRQX4Ei
cWjsJtaFpRj1QraFna0hpTQNO640je6s1rAIJl6eNOuX08l12ZAGDUA+IUUsa1cA
0OGeOAjH6gmkpMI89j1VPPKVRLHIdP4QcxmAZCHJ2LtvylyrlmYskctpAYibobvt
JPLnZgzMFAegnWtJhOYodhBJlfyypEeh2fsZVyDPowqRz9vaAWRjs6u/I4GYaME=
=HR3H
-----END PGP SIGNATURE-----
Merge tag 'multi-platform-for-3.7' of git://sources.calxeda.com/kernel/linux into next/multiplatform
Enable initial ARM multi-platform support for highbank, mvebu,
socfpga, picoxcell, and vexpress.
Multi-platform support is dependent on mach/gpio.h removal and
restructuring of DEBUG_LL and dtb build rules included in this branch.
This has been built for all defconfigs, and booted on highbank with
all 5 platforms enabled.
By Rob Herring (18) and Arnd Bergmann (1)
via Rob Herring
* tag 'multi-platform-for-3.7' of git://sources.calxeda.com/kernel/linux:
ARM: vexpress: convert to multi-platform
ARM: initial multiplatform support
ARM: mvebu: move armada-370-xp.h in mach dir
ARM: vexpress: remove dependency on mach/* headers
ARM: picoxcell: remove dependency on mach/* headers
ARM: move all dtb targets out of Makefile.boot
ARM: picoxcell: move debug macros to include/debug
ARM: socfpga: move debug macros to include/debug
ARM: mvebu: move debug macros to include/debug
ARM: vexpress: move debug macros to include/debug
ARM: highbank: move debug macros to include/debug
ARM: move debug macros to common location
ARM: make mach/gpio.h headers optional
ARM: orion: move custom gpio functions to orion-gpio.h
ARM: shmobile: move custom gpio functions to sh-gpio.h
ARM: pxa: use gpio_to_irq for sharppm_sl
net: pxaficp_ir: add irq resources
usb: pxa27x_udc: remove IRQ_USB define
staging: ste_rmi4: remove gpio.h include
Conflicts due to addition of bcm2835 and removal of pnx4008 in:
arch/arm/Kconfig
arch/arm/Makefile
Conflicts due to new dtb targets, moved to arch/arm/boot/dts/Makefile in:
arch/arm/mach-imx/Makefile.boot
arch/arm/mach-mxs/Makefile.boot
arch/arm/mach-tegra/Makefile.boot
Signed-off-by: Olof Johansson <olof@lixom.net>
* next/soc: (50 commits)
ARM: OMAP: AM33xx hwmod: fixup SPI after platform_data move
MAINTAINERS: add an entry for the BCM2835 ARM sub-architecture
ARM: bcm2835: instantiate console UART
ARM: bcm2835: add stub clock driver
ARM: bcm2835: add system timer
ARM: bcm2835: add interrupt controller driver
ARM: add infra-structure for BCM2835 and Raspberry Pi
ARM: tegra20: add CPU hotplug support
ARM: tegra30: add CPU hotplug support
ARM: tegra: clean up the common assembly macros into sleep.h
ARM: tegra: replace the CPU CAR access code by tegra_cpu_car_ops
ARM: tegra: introduce tegra_cpu_car_ops structures
ARM: Tegra: Add smp_twd clock for Tegra20
ARM: AM33XX: clock: Add dcan clock aliases for device-tree
ARM: OMAP2+: dpll: Add missing soc_is_am33xx() check for common functions
ARM: OMAP: omap_device: idle devices with no driver bound
ARM: OMAP: omap_device: don't attempt late suspend if no driver bound
ARM: OMAP: omap_device: keep track of driver bound status
ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
ARM: OMAP2+: hwmod: Hook-up am33xx support in omap_hwmod framework
...
Change/remove conflict in arch/arm/mach-ux500/clock.c resolved.
Signed-off-by: Olof Johansson <olof@lixom.net>
removes unnecessary semicolon
Found by Coccinelle: http://coccinelle.lip6.fr/
Signed-off-by: Peter Senna Tschudin <peter.senna@gmail.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Delete successive assignments to the same location.
A simplified version of the semantic match that finds this problem is as
follows: (http://coccinelle.lip6.fr/)
// <smpl>
@@
expression i;
@@
*i = ...;
i = ...;
// </smpl>
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This is trivial patch to mate parameter name between iommu api enabled case and
disabled case.
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: KyongHo Cho <pullip.cho@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
header files local where possible to get us closer to supporting
the ARM single zImage. After these changes mach includes are
pretty much out of the way for omap2+, but still lots of manual
work remains to sort through the remaining plat includes.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJQW5i3AAoJEBvUPslcq6Vzhf0P/295RFraSeKbgT0cc0GhjDsk
a30tqn2B1yAKZcuoe9kAr7MR55pA5wm7C6neBsu0+DqrZZ7v5sczl6kkb4415fbb
IgHZVL7ggeCKQaC2bq2bdbUSur2fj2uuIJoy5h6rfZFV5uuPeKggXI4PqrdgiBX9
Y8C+dTzNpWLG7evoREs0E8yzFnSh1OKizcxXzCvYhCM6ObjlQVpePnSs/tpxd0mw
4qmYc5QYTs7MEUzTxoyntQAYhE5vmTpLW4VrblWf/pCF2XnpIhn1I+sA8h4dte+i
txYJaLmouz5a7YNiEEFYztSsjhOWH3tJ5nxLZjcLm8IOlMM11zMaeCr+G0j18288
/ZMHNHdiwVk4RiG8WNk+gr0SM7nOEoqNsdMrIAmVt7P0QSasCBiZx/zh8JhmkNlX
XBsUvAOXmx8k4coF4ZCJ3E/aoxQBTZozbS1m0YrnRHkWJoexfXhXPp05uPFnJTQ0
bg6V6A12J9EWnHDAwN5JSkQCL35LR9+3KkxYnMZcq03Q2cfrQSyML0UYLTVPBKYa
cDyRAyuWooho6k5hyJiaCP6B1U/UzC5JGRz7XQ6bwweGbEgzGVjnW/EF/IJp7sGo
PzSRtb2WovCFNTywBhLLEnuHB+pKOvnflRn5KrNWkJfp5VDIzgaleMFBS98kn/tI
+ekNhimXe/QAsWzvq99q
=TZVo
-----END PGP SIGNATURE-----
Merge tag 'omap-cleanup-local-headers-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/cleanup
From Tony Lindgren:
This branch contains mostly scripted changes to make omap
header files local where possible to get us closer to supporting
the ARM single zImage. After these changes mach includes are
pretty much out of the way for omap2+, but still lots of manual
work remains to sort through the remaining plat includes.
* tag 'omap-cleanup-local-headers-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (26 commits)
ARM: OMAP2+: Make omap4-keypad.h local
ARM: OMAP2+: Make l4_3xxx.h local
ARM: OMAP2+: Make l4_2xxx.h local
ARM: OMAP2+: Make l3_3xxx.h local
ARM: OMAP2+: Make l3_2xxx.h local
ARM: OMAP1: Move irda.h from plat to mach
ARM: OMAP2+: Make hdq1w.h local
ARM: OMAP2+: Make gpmc-smsc911x.h local
ARM: OMAP2+: Make gpmc-smc91x.h local
ARM: OMAP1: Move flash.h from plat to mach
ARM: OMAP2+: Make debug-devices.h local
ARM: OMAP1: Move board-voiceblue.h from plat to mach
ARM: OMAP1: Move board-sx1.h from plat to mach
ARM: OMAP2+: Make omap-wakeupgen.h local
ARM: OMAP2+: Make omap-secure.h local
ARM: OMAP2+: Make ctrl_module_wkup_44xx.h local
ARM: OMAP2+: Make ctrl_module_pad_wkup_44xx.h local
ARM: OMAP2+: Make ctrl_module_pad_core_44xx.h local
ARM: OMAP2+: Make ctrl_module_core_44xx.h local
ARM: OMAP2+: Make board-rx51.h local
...
and imx-dt-3.7 and imx-clk-dt-lookup which have already been pulled.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQEcBAABAgAGBQJQW8LwAAoJEFBXWFqHsHzOtVgIAJN8Y2vHgI4kqMmMlXW8QhGj
7YNdFiWlLdhJL9jMOw2v8GwacUZ6x9HsgdK0h6DW3jERi54P7iafdsiFjRH2x8CI
PBNT8Qk9wyZnLNHq1bEUQIg7Nra1aZY9btEzqq0tpRYeJ9PMrgWOrI0ndQiSkTK7
xiYmJATBeQWFPUCGKUDtb9wuDLQ0gQSe1aE0zRkKoIgMn8/cKrbHO1TXh50QC4rt
hie0TkkCvPqeBGae6CTBd0AHFglNMCprwXIsHnnsmPrQdUZCLg9Eum+SDNRR2g19
g3COd+ecUfxtZpsJjdj/iV078nRPqg4GNCj3KO4dgmzHOe72Aed0xNcHNiTJoC0=
=5dum
-----END PGP SIGNATURE-----
Merge tag 'imx-dt-3.7-2' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/dt
From Shawn Guo:
This is the second round of imx-dt patches for 3.7. It's based on
and imx-dt-3.7 and imx-clk-dt-lookup which have already been pulled.
* tag 'imx-dt-3.7-2' of git://git.linaro.org/people/shawnguo/linux-2.6:
ARM: imx6q: use pll2_pfd2_396m as the enfc_sel's parent
ARM: dts: imx6q-sabrelite: add usbotg pinctrl support
ARM: dts: imx6q-sabrelite: add usbmisc device
mxs-dt-3.7 and mxs-clk-dt-lookup which have been pulled into arm-soc.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQEcBAABAgAGBQJQW8PHAAoJEFBXWFqHsHzO4GYH/jMaG4hFP4Epmxo88WJGhU4l
6ZNI1Gz90XGnx+EKJY7B30cRkvO/ydWrlUB0lMMnKdXuM/okAV66TFWrNTaEWjq1
15xlfn7jlpxY2lu2zflw3sM00jAL65AJDG3G4hA+ZnQlRo4G5MHYHAAGUawwxBJl
J0P0ZSGrVvZ82wGnW2FhvjrF0WR6Ni0mrhRnWQhsub9lykc4YUgOhG0IgxAh8jMx
RW7cR1o4St8ro4vm4joJdEa+ZQDprQDQsMJBOkacTb3SH4uDNpJpSeFVXa7BMSZ+
A8UpG+aHELyCJKU3gHuApcxS0tiK+vd1p0dikRGu6y167hHcKkzqZyVqOYTMrOU=
=/jro
-----END PGP SIGNATURE-----
Merge tag 'mxs-dt-3.7-2' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/dt
From Shawn Guo:
This is the second round of mxs-dt patches for 3.7. It's based on
mxs-dt-3.7 and mxs-clk-dt-lookup which have been pulled into arm-soc.
* tag 'mxs-dt-3.7-2' of git://git.linaro.org/people/shawnguo/linux-2.6:
ARM: mxs: m28evk: Disable OCOTP OUI loading
ARM: dts: imx23-olinuxino: Add USB host support
ARM: dts: mx23: Add USB resources
ARM: dts: mxs: Add ethernetX to macX aliases
This branch mainly removes dead code following the removal of all board
files. The removals depend on various changes in other branches, so they
are all merged together and form the basis of this branch, as enumerated
below.
Finally, there are no remaining users of pinconf-tegra.h outside the
pinctrl subsystem, so that header is incorporated into an existing file
there. This reduces the number of headers in mach-tegra/include, and so
helps move towards single zImage.
This branch is based on tegra-for-3.7-cleanup, followed by a merge of
tegra-for-3.7-board-removal, followed by a merge of
tegra-for-3.7-common-clk, followed by a merge of:
git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git xceiv-for-v3.7
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.10 (GNU/Linux)
iQIcBAABAgAGBQJQU4LUAAoJEMzrak5tbycxtgUQAK1eJnHOZOyoa/2p91C57xcQ
rgBVW5pxgYRsJy7T8ES8a/22xZWf7VMKbk7MYYdUBiHfQYXZe68tGPDP0pqckbYz
B3kfjpI1b/pgEv1e5QSDTZ56CF9fLJZqyjr7gZ18ZRoKebmKHX4eYDCcm9G3AX9/
8+JoCYieN2GpyytK7rqzXkwhq4WkHlGBtWFGC86FM/REVxoElT+9o+4eO8YmFU9d
i7sle37kMI0esNEPTWXRLIqBBMuESp2mlzDauuo3QRaU9ICDW061bgb6Jnrjif3o
gTEeoAMk9KDO/YMSYu3/aYl1x3Qaljm021Ppi2OPZbE21EskBMmK3Zn5Yzv3eYCJ
6NO4PyR19dcG8J6jKBglgyGsNrJ4etXsqryHnlkw+bBF1OpaieRdXnmmb4s9Xy1/
7gIcggDt9klOCnirM3MYYjb9xmMmKlyi78wv3Sj8T5dZbqXoEmsahYxKO/whUcaO
LoHZqtZ0uwj2E7c81sqIXe3N2OG/zPSblndBZFc84hOg2MwDFQkgLbinThPYtvMQ
9cMm88ZdDeBZYWGv/qwhOtCUwNprhumggDkg/XbhX7oeZVKQfmMZ0Vom65AFMcGz
if/teYoej7JC9jrf9w81n7RL8gh/bPjJi+71ogeitBZc7RJVQfH2XnaD2StWqPqM
WSppjgDf3ZmC9eMHA2TZ
=ltZ+
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-3.7-cleanup2' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/cleanup2
ARM: tegra: second round of cleanups
This branch mainly removes dead code following the removal of all board
files. The removals depend on various changes in other branches, so they
are all merged together and form the basis of this branch, as enumerated
below.
Finally, there are no remaining users of pinconf-tegra.h outside the
pinctrl subsystem, so that header is incorporated into an existing file
there. This reduces the number of headers in mach-tegra/include, and so
helps move towards single zImage.
This branch is based on tegra-for-3.7-cleanup, followed by a merge of
tegra-for-3.7-board-removal, followed by a merge of
tegra-for-3.7-common-clk, followed by a merge of:
git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git xceiv-for-v3.7
By Stephen Warren (16) and others
via Stephen Warren
* tag 'tegra-for-3.7-cleanup2' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (29 commits)
pinctrl: tegra: move pinconf-tegra.h content into drivers/pinctrl
ARM: tegra: delete unused headers
ARM: tegra: remove useless includes of <mach/*.h>
ARM: tegra: remove dead code
ARM: dt: tegra: harmony: configure power off
ARM: dt: tegra: harmony: add regulators
ARM: tegra: remove board (but not DT) support for Harmony
ARM: tegra: remove board (but not DT) support for Paz00
ARM: tegra: remove board (but not DT) support for TrimSlice
ARM: Tegra: Add smp_twd clock for Tegra20
ARM: tegra: cpu-tegra: explicitly manage re-parenting
ARM: tegra: fix overflow in tegra20_pll_clk_round_rate()
ARM: tegra: Fix data type for io address
ARM: tegra: remove tegra_timer from tegra_list_clks
ARM: tegra30: clocks: fix the wrong tegra_audio_sync_clk_ops name
ARM: tegra: clocks: separate tegra_clk_32k_ops from Tegra20 and Tegra30
ARM: tegra: Remove duplicate code
ARM: tegra: Port tegra to generic clock framework
ARM: tegra: Add clk_tegra structure and helper functions
ARM: tegra: Rename tegra20 clock file
...
nop xceiv got its own header to avoid polluting otg.h. It has also
learned to work as USB2 and USB3 phys so we can use it on USB3
controllers.
Together with those two changes to nop xceiv, we're adding basic
PHY support to dwc3 driver, this is to allow platforms which actually
have a SW-controllable PHY talk to them through dwc3 driver.
We're adding a new phy driver for the OMAP architecture. This driver
is for the PHY found in OMAP4 SoCs, and a new phy driver for the
marvell architecture. An extra phy driver - for Tegra SoCs - is now
moving from arch/arm/mach-tegra* to drivers/usb/phy.
Also here, there's the creation of <linux/usb/phy.h> which should be
used from now on for PHY drivers, even those which don't support
OTG.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJQThmRAAoJEIaOsuA1yqRE2U4P+gJHJsQZUIqTkCi6GyutMLUX
HUYVgaCXAbt4sSB5s0OK7AsB8uQ82GO6ZGyPfxNlYr6LXYlQWZ1OIig8PNhyn4en
lt0TolGL53fDOrwvQ0MIJBB1rgCk81UoFwJaPYkhKDNQLndl4hxlrFTsAvaIu7H0
pMMLt3E0Jz7018NxvVN23OV3EXnb2GF9K2Jt/NJNkZPanJaWXz0T/6DvBG24du2x
t3ALiKnpAC51wHPB5T88tefmVNApz7DPwK/Bm/VKW66LZ61Y+nZtZ+QMxj//uTt9
c3JXCvGscKSBcSfSFNMeYBdiPOZIFXTRVLr7CzxplvY9j5u8DTGArz5nvj/8ajbW
OeU0DMMaStfFqd12/BFUQeixbH8NUSoR5luWVMzBhB5+MF493gHvsu2ooorpR2hP
jQgMY146RdVbXNDJmuLRlVZbHQZfJBqvVUpk+3mdSSOtpy4IpKvlzPkYL1YjyOMt
x8WF+shSBvOMhg5C/HlGbDLzTiTv8zWef/aJ7OP9yUwYIz/map3lax749+M0Yzcj
trQgbLYrc8OeMVuCYGqjw1m96/YmcIxvzI/OnAMPbrPxK2hjy5jAu64/gOAZiZNY
oQis5G5qw/24LkXfLNQFTl8nYmaDko03+wazCg39D11bWZbLgKs9YJPZd78EwpJy
s+gU0+RYAQHgo+EChLY+
=/qVp
-----END PGP SIGNATURE-----
Merge tag 'xceiv-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into next/cleanup2
usb: xceiv: patches for v3.7 merge window
nop xceiv got its own header to avoid polluting otg.h. It has also
learned to work as USB2 and USB3 phys so we can use it on USB3
controllers.
Together with those two changes to nop xceiv, we're adding basic
PHY support to dwc3 driver, this is to allow platforms which actually
have a SW-controllable PHY talk to them through dwc3 driver.
We're adding a new phy driver for the OMAP architecture. This driver
is for the PHY found in OMAP4 SoCs, and a new phy driver for the
marvell architecture. An extra phy driver - for Tegra SoCs - is now
moving from arch/arm/mach-tegra* to drivers/usb/phy.
Also here, there's the creation of <linux/usb/phy.h> which should be
used from now on for PHY drivers, even those which don't support
OTG.
* tag 'xceiv-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb:
usb: otg: mxs-phy: Fix mx23 operation
usb: dwc3: add basic PHY support
usb: dwc3: exynos: add nop transceiver support
usb: dwc3: omap: add nop transceiver support
usb: dwc3: pci: add nop transceiver support
usb: otg: move the dereference below the NULL test
arm: omap: phy: remove unused functions from omap-phy-internal.c
usb: twl4030: Add device tree support for twl4030 usb
usb: twl6030: Add dt support for twl6030 usb
usb: otg: make twl6030_usb as a comparator driver to omap_usb2
usb: phy: add a new driver for omap usb2 phy
usb: phy: fix build break
usb: move phy driver from mach-tegra to drivers/usb
usb: otg: Move phy interface to separate file.
usb: phy: isp1301: Remove unused static array and define
usb: phy: mv_u3d: Add usb phy driver for mv_u3d
usb: otg: Remove the unneeded NULL check
usb: xceiv: nop: let it work as USB2 and USB3 phy
usb: xceiv: create nop-usb-xceiv.h and avoid pollution on otg.h
Signed-off-by: Olof Johansson <olof@lixom.net>
The Tegra code-base has contained both a legacy DMA and a dmaengine
driver since v3.6-rcX. This series flips Tegra's defconfig to enable
dmaengine rather than the legacy driver, and removes the legacy driver
and all client code.
The branch is based on v3.6-rc6 in order to pick up a bug-fix to the
ASoC Tegra PCM driver that's required for audio to work correctly when
using dmaengine.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.10 (GNU/Linux)
iQIcBAABAgAGBQJQV0gxAAoJEMzrak5tbycx9mIP/0uU4fVrAyIgbRkJ7nrPS/K7
vRKEfYJlXqr4zM79i3flpD/QPK6ImWcj0RptrdU3851yjVGkSehp8wbozKoBVDXQ
ZqPEBG039Vshmum/AD6Km3LSl4LBYurNJp/OC7ms5r0jIsU2IxZYaoofLGPXmgwn
LTlsG35Y/Bug6P4bbSNPhR/9CFAe695oQgvkIMnYROwVZTmQwu7Xh1CE2moKMEJN
top1Z3tZ+gtbb84eU1KR9BSNXAhQi7S7d4vWJe3RjnrhuSTVMIxiyNZSFjt8DrLL
7THzpmY/K2qV9k6CAO7bTl9X6m9cw8j+IbN6Ljc1NjbBiMcFe3TQRwFXicmt/Pma
VPjppGIfTUzC9WJI5Tj8GOV6I6B6X5oCSILcXjeJpNE3TEvdLnVXhiclbhiVuB/0
j9x0+w1SMfRr8RtsMvZyZHy1XQ+WJg/rXojGxLEsKJrZmmJ7yRkfqIr/Q9nSrh87
KYHhy8lsOuSPXq1qEVKQLwenc1VPbbDcDow1fBURPmz1CFCvNnR/mWtY2uCu5gk/
XPcqZu5I/T7DlrNGTfYCZbOow67tfHgAxW5MYLPXV+Fqkj1l9EimUGW5fIq7S6bA
2ouTuCS1e79d9kFLjgAzdbfqtdjy93v7G5vlBV7gUIrMg5PtGnQvQK9ab/YzasOt
XtP5p/eeV8NDo3MCw3+b
=4eRL
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-3.7-dmaengine' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/cleanup
ARM: tegra: switch to dmaengine
The Tegra code-base has contained both a legacy DMA and a dmaengine
driver since v3.6-rcX. This series flips Tegra's defconfig to enable
dmaengine rather than the legacy driver, and removes the legacy driver
and all client code.
* tag 'tegra-for-3.7-dmaengine' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ASoC: tegra: remove support of legacy DMA driver based access
spi: tegra: remove support of legacy DMA driver based access
ARM: tegra: apbio: remove support of legacy DMA driver based access
ARM: tegra: dma: remove legacy APB DMA driver
ARM: tegra: config: enable dmaengine based APB DMA driver
+ sync to 3.6-rc6
On Harmony, LDO7 does not feed vdd_fuse. Correct the regulator name.
This issue was probably the result of copying Ventana's regulator setup
when creating the Harmony .dts file. No other naming issues appear to
exist.
Reported-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
On board keys on Origen board can serve as wakeup sources,
hence they are marked accordingly in the device tree file.
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The clock instance parameter in Samsung clock interface is not being checked
for NULL pointers. Add checks for NULL pointers.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Acked-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The clocks for PCM, Slimbus, Spdif added to off list in order
to turn them off at boot time.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Acked-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Sangbeom Kim <sbkim73@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds the bus clock for FIMD and changes the device name
for lcd clock
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
Reviewed-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit adds basic device tree for Exynos4210-based Trats board.
Currently it provides support for eMMC over sdhci and MAX8997 PMIC.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Currently all boards must explicitly disable all unused device tree
nodes of unused components (e.g. i2c, sdhci, etc...). This makes it
necessary to all boards to be aware of all components on the SoC, which
in turns makes board dts files longer and more difficult to maintain
(e.g. adding new components to SoC-level tree requires adding nodes with
status="disabled" to every board).
This patch changes "status" of all optional components in SoC-level dts
file to "disabled", adds status="okay" to respective nodes of used
components in dts of all boards and removes all nodes with only
status="disabled" from boards dts.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Since mach-exynos4-dt.c is also going to be used for other SoCs from EXYNOS4
line, rename internal structures and functions to use exynos4_ prefix, instead
of exynos4210_.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Most definitions from exynos4210.dtsi can be applied for other SoCs from
EXYNOS4 line as well, so move the common part into separate file that
can be included by dtsi files of other EXYNOS4 SoCs (as well as current
exynos4210.dtsi).
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Thomas Abraham <thomas.abraham@linaro.org>
[kgene.kim@samsung.com: Dongjin Kim <dongjin.kim@agreeyamobility.net>
submitted a similar patch 'Add DTS files derived from common EXYNOS4'
before this but I picked this up because of included exynos4x12 stuff]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This branch includes some late device tree changes for Tegra:
A property is added to Whistler's device tree to enable the PMIC to
act as the pm_power_off() implementation.
A number of new device tree are added for boards from Avionic Design.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.10 (GNU/Linux)
iQIcBAABAgAGBQJQWzknAAoJEMzrak5tbycx5xgP+gMwuLEEd9YFTm8s2lpco8F8
k6hDy/5a7LSgmYgrVa8U7dooQSZyDQE8/Arfzw/uXKbhHY77+B06aqz6doCLjQ2s
UZp9TGqS9rFcItNipeYbqxKMU0QYzHAX+ZCgld2Sq9TI9STCJjmB1Rhb9zmcr+zv
kYGp73b8fjDI/44bRGsF3AOwKjQjB4hmAyFY+ybjUENFU7pFIR1V1bGsczhDvwzs
Bp2JilSKPrS9kf+pzMDWON8/0HHoKnKfLE/Cx7iwYbKgt9Czl4wUUqeFzNI5CCnw
/FquASmefo3JUPRR2Q7A8IwCF6YksJCDO6nQSa6wD0k4tuC/5qHm7x+pZkWDZwBM
iWovqYFEMgN1rhzdxb6BJVt3I6zVSzkhF8+gcw5rRSakZgKSVsJqsNU20hrkRx5A
mW0F2vCwEzKZa2v9wHpqJ7YjJdr4X6ISKWbipDmmTXxBBUyXIpJTSjkTd969J9iQ
XFvPK3VI4LRgw/Nu5qMbPIyIIbGWLkIY6dKJNOHY1aDZGuntDqVWen4OTrX57S/E
XC00MR7WAZtLbternGj6WA6UiyuYU+JQ825CfLs8PS5a9+xLSntyaPeQtMkEpz6p
7kDBSBOBg9O5KxgJNT/6ufk7qogWpe461OyQsAt6BHfmjXStQM0ZN2DmZhaYaqkm
hxGAq/7/0F1R7kUvyw3j
=s7Ln
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-3.7-dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/dt
ARM: tegra: second round of device tree changes
This branch includes some late device tree changes for Tegra:
A property is added to Whistler's device tree to enable the PMIC to
act as the pm_power_off() implementation.
A number of new device tree are added for boards from Avionic Design.
* tag 'tegra-for-3.7-dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: tegra: Add Avionic Design Tamonten Evaluation Carrier support
ARM: tegra: Add Avionic Design Medcom-Wide support
ARM: tegra: Add Avionic Design Plutux support
ARM: tegra: Add Avionic Design Tamonten support
ARM: tegra: dts: Add pwm label
ARM: dt: tegra: whistler: configure power off
The BCM2835 is an ARM SoC from Broadcom. This patch adds very basic
support for this SoC; enough to boot the system into an initrd with
UART console, interrupt controller, timers, and a stub clock driver.
Also provided is a similarly basic device tree for the Raspberry Pi
Model B board.
This series was written by Simon Arlott, Chris Boot, and Dom Cobley
downstream, with reference to a Broadcom tree, and modified for upstream
and submitted by Stephen Warren.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJQWnCOAAoJEJuNpwkmVCGcQS8P/01yZOE2QhW/S4ap1voLyRuI
T7wcjla6UXckuz72qnLitJCDHxwDAF6Kgc/anibQfgambqjOAA5YuXBkJlUaBQF1
3u6k8pNJ7cI3R44BznnLN4U8QXw/w5IlUdFu7Y7Xg4xyb1Fdx11QJelYmiPIdXEQ
fFVqO5JQoMWXz7i9fYU/jXHcbINyljgSqhBOM9O1R2W3kayPm3OdmyAXHzmt7rSw
XPta3QlrkI/fCgolI2A9LMhrfaJVRQe59H9b+fP2R9baWs7BnkZywjO8mwipR8eI
d4tRH8cy+Aa/RobLe5DnorxZ9abj3vlSv0kG0qBhcieqXZmGKlum3J4h1cBAvs8p
Cv0Gm7GFxeqCJ3RaLfn1mX2OESmGQ9KH33J3PFQUcNmd82saXz6Kas7YZ5KRlMAI
+TS3n9Er7P2HlpYF/3ckE3aYrN/iHJaZ/2pa2ZiR8KRnRTY3DMTxgvNIaz044zud
gHUbQpttzNV0aiqMDqMvpVqBhUMCVF0LWlhQyewQHHdVSS9XNq1lrfbXPc4k54Fs
Tkz4JT5S1Vhv+iqakwKQvNVpO8XWvj0Z5t5/3IqLpzdYWRp6kQh8giJXhLEQSoVl
38sJ2v6MzNmyx1yggO58Qq+OpelNDowhY0tGcOrSl6uR786gcivw9T2wd8V0iwbw
uMeZ6apUnOseOaKU9mrm
=vqsx
-----END PGP SIGNATURE-----
Merge tag 'rpi-for-3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi into next/soc
ARM: add basic BCM2835 SoC and Raspberry Pi board support
The BCM2835 is an ARM SoC from Broadcom. This patch adds very basic
support for this SoC; enough to boot the system into an initrd with
UART console, interrupt controller, timers, and a stub clock driver.
Also provided is a similarly basic device tree for the Raspberry Pi
Model B board.
This series was written by Simon Arlott, Chris Boot, and Dom Cobley
downstream, with reference to a Broadcom tree, and modified for upstream
and submitted by Stephen Warren.
* tag 'rpi-for-3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi:
MAINTAINERS: add an entry for the BCM2835 ARM sub-architecture
ARM: bcm2835: instantiate console UART
ARM: bcm2835: add stub clock driver
ARM: bcm2835: add system timer
ARM: bcm2835: add interrupt controller driver
ARM: add infra-structure for BCM2835 and Raspberry Pi
From Kukjin Kim:
This is for updating s3c6400_defconfig to build every s3c64xx stuff.
This helps to know at least building error before merging them.
* 'next/defconfig-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: s3c6400_defconfig: enable more boards in defconfig
Signed-off-by: Olof Johansson <olof@lixom.net>
From Kukjin Kim:
This is for updating non-DT Samsung board files for v3.7, there are adding
generic PWM lookup support and some updates.
* 'next/board-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: Add generic PWM lookup support for SMDKV310
ARM: EXYNOS: Add generic PWM lookup support for SMDK4X12
ARM: EXYNOS: Use generic pwm driver in Origen board
ARM: dts: Add heartbeat gpio-leds support to Origen
ARM: dts: Use active low flag for gpio-keys on Origen
ARM: S3C64XX: Register audio platform devices for Bells on Cragganmore
ARM: S3C64XX: Update configuration for WM5102 module on Cragganmore
Fixed trivial merge conflict in arch/arm/mach-exynos/mach-smdkv310.c.
Signed-off-by: Olof Johansson <olof@lixom.net>
From Kukjin Kim:
Here is G-Scaler DT for supporting EXYNOS5 SoCs.
* 'next/dt-gscaler' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: Adds G-Scaler device from Device Tree
ARM: EXYNOS: Add clock support for G-Scaler
From Kukjin Kim:
This branch is for supporting pinctrl for Samsung EXYNOS. Now this can
support EXYNOS4210 and other EXYNOS SoCs such as EXYNOS4X12 will be
supported next time.
* 'next/pinctrl-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: Enable pinctrl driver support for EXYNOS4 device tree enabled platform
ARM: dts: Add pinctrl node entries for SAMSUNG EXYNOS4210 SoC
ARM: EXYNOS: skip wakeup interrupt setup if pinctrl driver is used
gpio: exynos4: skip gpiolib registration if pinctrl driver is used
pinctrl: add exynos4210 specific extensions for samsung pinctrl driver
pinctrl: add samsung pinctrl and gpiolib driver
From Kukjin Kim:
Here, there are cleanup patches for Samsung v3.7 and most of them are
related to cleanup Samsung specific gpio API.
* samsung/cleanup:
gpio: samsung: Update documentation
ARM: S3C24XX: Use module_platform_driver macro in mach-osiris-dvs.c
ARM: S3C24XX: Use module_platform_driver macro in h1940-bluetooth.c
gpio-samsung: Remove now unused s3c2410_gpio* API
ARM: S3C24XX: Remove obsolete GPIO API declarations
ARM: S3C24XX: Convert users of s3c2410_gpio_setpin to gpiolib API
ARM: EXYNOS: cleanup unused code related to GPS
Silences the following warnings:
arch/arm/plat-samsung/devs.c:765:31: warning:
symbol 's5p_hdmi_def_platdata' was not declared. Should it be static?
arch/arm/plat-samsung/devs.c:767:13: warning:
symbol 's5p_hdmi_set_platdata' was not declared. Should it be static?
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add missing get_rate callback for the "camif-upll" clock, so frequency
of this clock is properly reported with clk_get_rate().
Signed-off-by: Sylwester Nawrocki <sylvester.nawrocki@gmail.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The clocks for NAND, OneNAND and Transport Stream Interface(TSI)
controllers could be either enabled or disabled at boot. To ensure
that these are turned off until used, add them to the list of clocks
to be turned off during boot.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
AM33xx hwmod data includes "mcspi.h" which has now been moved after
the platform_data move. Fix it.
Signed-off-by: Kevin Hilman <khilman@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This is only used by omap1.
And to fix things properly, this should not be included
from the drivers at all.
Acked-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: linux-fbdev@vger.kernel.org
Cc: Artem Bityutskiy <Artem.Bityutskiy@linux.intel.com>
Cc: linux-mtd@lists.infradead.org
Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Cc: linux-input@vger.kernel.org
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Cc: Liam Girdwood <lrg@ti.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: alsa-devel@alsa-project.org
Signed-off-by: Tony Lindgren <tony@atomide.com>
We are moving omap2+ to use the device tree based pinctrl-single.c
and will be removing the old mux framework. This will remove the
omap1 specific parts from plat-omap.
Acked-by: Felipe Balbi <balbi@ti.com>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Alan Stern <stern@rowland.harvard.edu>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Richard Purdie <rpurdie@rpsys.net>
Cc: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: linux-usb@vger.kernel.org
Cc: linux-pcmcia@lists.infradead.org
Cc: spi-devel-general@lists.sourceforge.net
Signed-off-by: Tony Lindgren <tony@atomide.com>
Note that this branch is based on omap-cleanup-sparseirq-for-v3.7
to avoid merge conflicts with the sparseirq changes for gpio-twl4030
driver.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJQVlRgAAoJEBvUPslcq6VzbSwP/RNdw33WTv7slY8v2x9C+jfe
fzpJltqtWf1xLQ5ixAMwzBxc4/I+m/fz3ZhxG15amqD1sQuwDNNVwI6D5F4pIH4K
ZfyaeA8jteH487f7PxMlurtVYgPRqLrMXBahxKgcM6WwJ0tFspGuXQeKMhjhRnYJ
4+0GQ/R60UmexyAF4Ish4YfVfe0Iy8deVuGjOO7xIdsKrC1uymXbT7HB0o7Tz4tj
btsEUXs4UMCh2VoYzqVxaP1uMumOnuVOFOuWjcNOni3TMdjmllPpoApsXE27rNKC
0D/MzCyutFEO7q7/8TSUs3TOy+my18Z6Fz9hEkw7fUOOXQ3iUDqI79FbvMv9mWe+
nW2BFZZCeuTqErGNakgluGtasLOfvqOqzSO7U68XGgHp86G42N2EDs4raTDAeKTN
YXzLSiPYvV5QOUFbP5uagiKFcFUbcfNYZytTPwZ8hBk4hXtDmwqhSEgzxhAKGtgx
y0ljt3iQNxk3EVhIv7oi0FxCFX2ioikYPTOlHkpvNwkXa7ruvvU1CudIGSdZ/Nn3
SoEkRDwx6CpA37aAusfWioYKWhrctfDBl9Nt0IXwZy1b0MO1QIUaL0RY3Y5FsES+
25MP+5Ns6nkmzzTs72Gu+W9bL6E3eHAkAoaDb9JPH2Jix8vXRMgIISyu9Fzze504
ypeFe5TtLc/uYkviZhi6
=fzT6
-----END PGP SIGNATURE-----
Merge tag 'omap-devel-dt-merged-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
Device tree related changes for omaps.
Note that this branch is based on omap-cleanup-sparseirq-for-v3.7
to avoid merge conflicts with the sparseirq changes for gpio-twl4030
driver.
* tag 'omap-devel-dt-merged-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
arm/dts: Mux uart pins for omap4-sdp
ARM: OMAP2+: select PINCTRL in Kconfig
arm/dts: Add pinctrl driver entries for omap2/3/4
arm/dts: Add omap36xx.dtsi file and rename omap3-beagle to omap3-beagle-xm
ARM: dts: omap3-overo: Add support for the blue LED
Documentation: dt: Update the OMAP documentation with Overo/Toby
ARM: dts: OMAP3: Add support for Gumstix Overo with Tobi expansion board
ARM: dts: OMAP4: Add reg and interrupts for every nodes
ARM: dts: AM33XX: Specify reg and interrupt property for all nodes
ARM: dts: AM33XX: Convert all hex numbers to lower-case
ARM: dts: omap3-beagle: Enable audio support
ARM: dts: omap5: Add McPDM and DMIC section to the dtsi file
ARM: dts: omap5: Add McBSP entries
ARM: dts: omap4: Add reg-names for McPDM and DMIC
ARM: dts: omap4: Add McBSP entries
ARM: dts: omap3: Add McBSP entries
ARM: dts: omap2420-h4: Include omap2420.dtsi file instead the common omap2
ARM: dts: omap2: Add McBSP entries for OMAP2420 and OMAP2430 SoC
ARM: dts: omap3-beagle: Add heartbeat and mmc LEDs support
ARM: dts: omap3: Add gpio-twl4030 properties for BeagleBoard and omap3-EVM
...
Olof Johansson