Describe the RPCSRC internal clock and the RPC[D2] clocks derived from
it, as well as the RPC-IF module clock, in the R-Car H3 (R8A7795)
CPG/MSSR driver.
Inspired by commit 94e3935b57 ("clk: renesas: r8a77980: Add RPC clocks").
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Link: https://lore.kernel.org/r/20200203072901.31548-1-dirk.behme@de.bosch.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch adds the TPU clock on the R-Car r8a7795/r8a7796/r8a77965
SoCs.
Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
According to the R-Car Gen3 Hardware Manual Errata for Rev. 1.50 of Feb
12, 2019, the DRIF clocks have been renamed as follows:
DRIF0 to DRIF00
DRIF1 to DRIF01
DRIF2 to DRIF10
DRIF3 to DRIF11
DRIF4 to DRIF20
DRIF5 to DRIF21
DRIF6 to DRIF30
DRIF7 to DRIF31
Therefore, this patch renames the DRIF clocks from DRIFn to DRIFmm.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
The clock sources of the AXI-bus clock (266.66 MHz) used for Audio-DMAC
DMA transfers are:
Channel R-Car H3 R-Car M3-W R-Car M3-N R-Car E3
---------------------------------------------------------------
Audio-DMAC0 S1D2 S1D2 S1D2 S1D2
Audio-DMAC1 S1D2 S1D2 S1D2 -
As a result, change the parent clocks of the Audio-DMAC{0,1} module
clocks on R-Car H3, R-Car M3-W, and R-Car M3-N to S1D2, and change the
parent clock of the Audio-DMAC0 module on R-Car E3 to S1D2.
NOTE: This information will be reflected in a future revision of the
R-Car Gen3 Hardware Manual.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Update R-Car D3, RZ/G2M, and RZ/G2E]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
The clock sources of the AXI BUS clock (266.66 MHz) used for SYS-DMAC
DMA transfers are:
Channel R-Car H3 R-Car M3-W R-Car M3-N
-------------------------------------------------
SYS-DMAC0 S0D3 S0D3 S0D3
SYS-DMAC1 S3D1 S3D1 S3D1
SYS-DMAC2 S3D1 S3D1 S3D1
As a result, change the parent clocks of the SYS-DMAC{1,2} module clocks
on R-Car H3, R-Car M3-W, and R-Car M3-N to S3D1.
NOTE: This information will be reflected in a future revision of the
R-Car Gen3 Hardware Manual.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Update RZ/G2M]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
According to the R-Car Gen3 Hardware Manual Rev. 1.00, and the RZ/G2
Hardware Manual Rev. 0.61, the parent clock of the HS-USB module
clocks on R-Car Gen3 and RZ/G2 SoCs is S3D2.
Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
[takeshi: Update R-Car H3, M3-N, and E3]
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Update RZ/G2M and RZ/G2E]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
According to the R-Car Gen3 Hardware Manual Rev. 1.00, and the RZ/G2
Hardware Manual Rev. 0.61, the parent clock of the EHCI/OHCI module
clocks on R-Car Gen3 and RZ/G2 SoCs is S3D2.
Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
[takeshi: Update R-Car H3, M3-N, and E3]
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Update RZ/G2M and RZ/G2E]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
After recent reworking of Z and Z2 clk handling
CLK_TYPE_GEN3_Z and CLK_TYPE_GEN3_Z2 have come to have precisely
the same meaning. Remove this redundancy by eliminating the latter.
This is not expected to have any run-time effect.
As suggested by Geert Uytterhoeven.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Parameterise the offset of control bits within the FRQCRC register
for Z and Z2 clocks.
This is in preparation for supporting the Z2 clock on the R-Car E3
(r8a77990) SoC which uses a different offset for control bits to
other, already, supported SoCs.
As suggested by Geert Uytterhoeven.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Parameterise Z and Z2 clock fixed divisor to allow clocks with a fixed
divisor other than 2, the value used by all such clocks supported to date.
This is in preparation for supporting the Z2 clock on the R-Car E3
(r8a77990) SoC which has a fixed divisor of 4.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[simon: squashed several patches; rewrote changelog; added r8a774a1 change]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Implement support for the CPEX clock on R-Car H3. This clock can be
selected as a clock source for CMT1 (Compare Match Timer Type 1).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
R-Car Gen3 Hardware Manual Rev.0.52 documents the relation between the
MD13 and MD14 mode pins, and the OSC EXTAL predivider, as used by the
OSC and RINT RCLK clocks. Hence augment the configuration structure
with all documented predivider values.
According to R-Car Gen3 Hardware Manual Rev.0.53, the CPG_RCKCR
register was removed in R-Car H3 ES2.0. Change the OSC and RINT
clock definitions to use the OSC EXTAL predivider instead, which is
supported on all R-Car H3 SoC revisions.
Inspired by a patch in the BSP by Takeshi Kihara
<takeshi.kihara.df@renesas.com>.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
All other internal clock names have a period prepended.
Hence rename the internal RCLK from "rint" to ".r", and move it to the
section where all other internal clocks are defined.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds the clock used by the CryptoCell 630p instance in the
SoC.
Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add the CR core clock, which is used by the Secure Engine (SCEG).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Tested-by: Gilad Ben-Yossef <gilad@benyossef.com>
This patch adds Z clock for R8A7795 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
According to the R-Car Gen3 Hardware Manual Errata for Rev 0.55 of
September 8, 2017, the parent clock of the INTC-AP module clock on R-Car
H3 ES2.0 is S0D3.
This change has no functional impact.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
On some R-Car Gen3 SoCs (e.g. R-Car D3), PLL1 and PLL3 use a divider
value different from one. Extend struct rcar_gen3_cpg_pll_config to handle
this. As all multipliers and dividers are small, table size increase
can be kept limited by storing them in u8s instead of unsigned ints,
which saves ca. 0.5 KiB for a generic kernel.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Cfr. the errata of April 14, 2017, for the R-Car Gen3 Hardware Manual
Rev. 0.53E.
These have no user-visible effect, as the clock frequencies stay the
same.
Fixes: 5573d19412 ("clk: renesas: r8a7795: Add support for R-Car H3 ES2.0")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
The Clock Pulse Generator / Module Standby and Software Reset module in
R-Car H3 ES2.0 differs from ES1.x in the following areas:
- More core clocks (S0D2, S0D3, S0D6, S0D8, S0D12),
- Different parent clocks for AUDMAC, EtherAVB, FCP, FDP, IMR,
SYS-DMAC, VIN, VSPB, VSPI,
- Removal of modules CSI21, FCPCI, FCPF2, FCPVD3, FCPVI2, FDP1-2,
USB3-IF1, VSPD3, VSPI2,
- Addition of modules EHCI3, HS-USB-IF3, USB-DMAC3-0, USB-DMAC3-1.
The goal is twofold:
1. Support both the ES1.x and ES2.0 SoC revisions in a single binary
for now,
2. Make it clear which code supports ES1.x, so it can easily be
identified and removed later, when production SoCs are deemed
ubiquitous.
This is achieved by:
- Updating the clock tables for the latest revision (ES2.0), but not
removing clocks that only exist on earlier revisions (ES1.x),
- Detecting the SoC revision at runtime using the new soc_device_match()
API, and fixing up the clocks tables to match the actual SoC
revision, by:
- NULLifying core and module clocks of modules that do not exist,
- Reparenting module clocks that have a different parent on ES1.x.
Based on R-Car Gen3 Hardware User's Manual rev. 0.53E.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Pass the mode pin states from the SoC-specific CPG/MSSR driver to the
R-Car Gen3 CPG driver core, as their state will be needed to make some
core clock configuration decisions.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The parent clock of the Audio DMACs is the "ZS" AXI bus clock, which
maps to S3D1 on R-Car H3 ES1.x.
All module clocks must be sorted by clock ID.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Add the IMR[0-3] clocks to the R8A7795 CPG/MSSR driver.
Based on the original (and large) patch by Konstantin Kozhevnikov
<Konstantin.Kozhevnikov@cogentembedded.com>.
Signed-off-by: Konstantin Kozhevnikov <Konstantin.Kozhevnikov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Correct HDMI parent clock so that the rate of the
HDMI clock is 1/4 rather than 1/2 of the rate of PLL1
as per the v0.52 (Jun, 15) manual.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Obtain the values of the mode pins from the R-Car RST driver, which
relies on the presence in DT of a device node for the RST module.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
According to the datasheet, SDn clocks are from the SDSRC clock. And
the SDSRC has a 1/2 divider. So, we should have ".sdsrc" as an internal
core clock. Otherwise, since the sdhi driver will calculate clock for
a sd card using the wrong parent clock rate, and then performance will
be not good.
Fixes: 90c073e539 ("clk: shmobile: r8a7795: Add SD divider support")
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: stable@vger.kernel.org
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
According to the latest information, the parent clock of the LVDS module
clock is the S0D4 clock, not the S2D1 clock.
Note that this change has no influence on actual operation, as the
rcar-du LVDS encoder driver doesn't use the parent clock's rate.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Extract the code to support parts common to all members of the R-Car
Gen3 SoC family into a separate file, to ease sharing among SoC-specific
drivers.
Note that while the cpg_pll_configs[] arrays and the selection of the
config based on the MODE bits are identical on R-Car H3 and R-Car M3-W,
they are not common, and may be different on other R-Car Gen3 SoCs.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
R can select between two parents. We deal with it like this: During
initialization, check if EXTALR is populated. If so, use it for R. If
not, use R_Internal. clk_mux doesn't help here because we don't want to
switch parents depending on the clock rate. The clock rate (and source)
should stay constant for the watchdog, so I think a setup like this
during initialization makes sense.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
About SD clocks: The clock type is Gen3 specific, the callbacks are all
Gen3 specific; I think the clock definition should also be Gen3 specific
and not in the general header file.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Dirk Behme