Christoph Hellwig 9e80635619 riscv: clear the instruction cache and all registers when booting ... When we get booted we want a clear slate without any leaks from previous supervisors or the firmware. Flush the instruction cache and then clear all registers to known good values. This is really important for the upcoming nommu support that runs on M-mode, but can't really harm when running in S-mode either. Vaguely based on the concepts from opensbi. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>		2019-11-17 15:17:39 -08:00
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boot	riscv: dts: HiFive Unleashed: add default chosen/stdout-path	2019-10-14 12:30:30 -07:00
configs	RISC-V: Enable VIRTIO drivers in RV64 and RV32 defconfig	2019-09-19 05:44:35 -07:00
include	riscv: clear the instruction cache and all registers when booting	2019-11-17 15:17:39 -08:00
kernel	riscv: clear the instruction cache and all registers when booting	2019-11-17 15:17:39 -08:00
lib	riscv: abstract out CSR names for supervisor vs machine mode	2019-11-05 09:20:42 -08:00
mm	riscv: implement remote sfence.i using IPIs	2019-11-13 13:24:21 -08:00
net	bpf, riscv: Enable zext optimization for more RV64G ALU ops	2019-07-05 23:55:41 +02:00
Kbuild	riscv: add arch/riscv/Kbuild	2019-08-30 17:34:00 -07:00
Kconfig	riscv: don't allow selecting SBI based drivers for M-mode	2019-11-13 13:20:02 -08:00
Kconfig.debug	RISC-V: Remove EARLY_PRINTK support	2018-12-17 10:23:46 -08:00
Kconfig.socs	riscv: select SiFive platform drivers with SOC_SIFIVE	2019-07-01 13:20:01 -07:00
Makefile	Kbuild updates for v5.4	2019-09-20 08:36:47 -07:00