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88 lines
1.8 KiB
Plaintext
88 lines
1.8 KiB
Plaintext
Binding for IDT VersaClock 5,6 programmable i2c clock generators.
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The IDT VersaClock 5 and VersaClock 6 are programmable i2c clock
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generators providing from 3 to 12 output clocks.
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==I2C device node==
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Required properties:
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- compatible: shall be one of
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"idt,5p49v5923"
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"idt,5p49v5933"
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"idt,5p49v5935"
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"idt,5p49v6901"
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- reg: i2c device address, shall be 0x68 or 0x6a.
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- #clock-cells: from common clock binding; shall be set to 1.
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- clocks: from common clock binding; list of parent clock handles,
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- 5p49v5923 and
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5p49v6901: (required) either or both of XTAL or CLKIN
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reference clock.
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- 5p49v5933 and
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- 5p49v5935: (optional) property not present (internal
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Xtal used) or CLKIN reference
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clock.
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- clock-names: from common clock binding; clock input names, can be
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- 5p49v5923 and
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5p49v6901: (required) either or both of "xin", "clkin".
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- 5p49v5933 and
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- 5p49v5935: (optional) property not present or "clkin".
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==Mapping between clock specifier and physical pins==
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When referencing the provided clock in the DT using phandle and
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clock specifier, the following mapping applies:
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5P49V5923:
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0 -- OUT0_SEL_I2CB
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1 -- OUT1
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2 -- OUT2
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5P49V5933:
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0 -- OUT0_SEL_I2CB
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1 -- OUT1
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2 -- OUT4
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5P49V5935:
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0 -- OUT0_SEL_I2CB
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1 -- OUT1
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2 -- OUT2
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3 -- OUT3
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4 -- OUT4
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5P49V6901:
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0 -- OUT0_SEL_I2CB
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1 -- OUT1
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2 -- OUT2
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3 -- OUT3
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4 -- OUT4
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==Example==
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/* 25MHz reference crystal */
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ref25: ref25m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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i2c-master-node {
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/* IDT 5P49V5923 i2c clock generator */
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vc5: clock-generator@6a {
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compatible = "idt,5p49v5923";
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reg = <0x6a>;
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#clock-cells = <1>;
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/* Connect XIN input to 25MHz reference */
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clocks = <&ref25m>;
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clock-names = "xin";
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};
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};
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/* Consumer referencing the 5P49V5923 pin OUT1 */
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consumer {
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...
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clocks = <&vc5 1>;
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...
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}
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